net: fec_mxc: add 1000 Mbps selection
authorTroy Kisky <troy.kisky@boundarydevices.com>
Tue, 7 Feb 2012 14:08:46 +0000 (14:08 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 27 Feb 2012 20:19:24 +0000 (21:19 +0100)
Define FEC_QUIRK_ENET_MAC and add to
arch-mx6/imx-regs.h

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
arch/arm/include/asm/arch-mx6/imx-regs.h
drivers/net/fec_mxc.c
drivers/net/fec_mxc.h

index 3b5fd25e363da00431533219e97f9714e8265f21..6b7589b78a3e76f00bc0c4705160693dbe3088eb 100644 (file)
 #define CHIP_REV_1_0                 0x10
 #define IRAM_SIZE                    0x00040000
 #define IMX_IIM_BASE                 OCOTP_BASE_ADDR
+#define FEC_QUIRK_ENET_MAC
 
 #define GPIO_NUMBER(port, index)               ((((port)-1)*32)+((index)&31))
 #define GPIO_TO_PORT(number)           (((number)/32)+1)
index ed733535d54045f1926a0b205dfa65f8f8f7c866..db8ebfaf8a2af5dc229436751ba255634e7a1ad5 100644 (file)
@@ -379,13 +379,14 @@ static int fec_set_hwaddr(struct eth_device *dev)
 static int fec_open(struct eth_device *edev)
 {
        struct fec_priv *fec = (struct fec_priv *)edev->priv;
+       int speed;
 
        debug("fec_open: fec_open(dev)\n");
        /* full-duplex, heartbeat disabled */
        writel(1 << 2, &fec->eth->x_cntrl);
        fec->rbd_index = 0;
 
-#if defined(CONFIG_MX6Q)
+#ifdef FEC_QUIRK_ENET_MAC
        /* Enable ENET HW endian SWAP */
        writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
                &fec->eth->ecntrl);
@@ -428,9 +429,25 @@ static int fec_open(struct eth_device *edev)
 #endif
 
        miiphy_wait_aneg(edev);
-       miiphy_speed(edev->name, fec->phy_id);
+       speed = miiphy_speed(edev->name, fec->phy_id);
        miiphy_duplex(edev->name, fec->phy_id);
 
+#ifdef FEC_QUIRK_ENET_MAC
+       {
+               u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
+               u32 rcr = (readl(&fec->eth->r_cntrl) &
+                               ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
+                               FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+               if (speed == _1000BASET)
+                       ecr |= FEC_ECNTRL_SPEED;
+               else if (speed != _100BASET)
+                       rcr |= FEC_RCNTRL_RMII_10T;
+               writel(ecr, &fec->eth->ecntrl);
+               writel(rcr, &fec->eth->r_cntrl);
+       }
+#endif
+       debug("%s:Speed=%i\n", __func__, speed);
+
        /*
         * Enable SmartDMA receive task
         */
index 9825eab2918f3eff1aa21a6ce5e038e080dbd7d9..af33d2169ced0323ca84ce0ef999a38aa3ef21fd 100644 (file)
@@ -198,6 +198,7 @@ struct ethernet_regs {
 #define FEC_RCNTRL_FCE                 0x00000020
 #define FEC_RCNTRL_RGMII               0x00000040
 #define FEC_RCNTRL_RMII                        0x00000100
+#define FEC_RCNTRL_RMII_10T            0x00000200
 
 #define FEC_TCNTRL_GTS                 0x00000001
 #define FEC_TCNTRL_HBC                 0x00000002
@@ -207,6 +208,7 @@ struct ethernet_regs {
 
 #define FEC_ECNTRL_RESET               0x00000001      /* reset the FEC */
 #define FEC_ECNTRL_ETHER_EN            0x00000002      /* enable the FEC */
+#define FEC_ECNTRL_SPEED               0x00000020
 #define FEC_ECNTRL_DBSWAP              0x00000100
 
 #define FEC_X_WMRK_STRFWD              0x00000100