armv8/ls1043ardb: add DSPI support
authorGong Qianyu <Qianyu.Gong@freescale.com>
Wed, 11 Nov 2015 09:58:39 +0000 (17:58 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 30 Nov 2015 17:11:11 +0000 (09:11 -0800)
Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/dts/fsl-ls1043a-rdb.dts
arch/arm/dts/fsl-ls1043a.dtsi
configs/ls1043ardb_defconfig
configs/ls1043ardb_nand_defconfig
configs/ls1043ardb_sdcard_defconfig
include/configs/ls1043ardb.h

index 17a06812c571942bdc8d67f72c3e51257fe68b3f..16c5c89d7c799c1c2d94c6e62e058e1151e993e5 100644 (file)
 
 / {
        model = "LS1043A RDB Board";
+
+        aliases {
+               spi1 = &dspi0;
+        };
+
+};
+
+&dspi0 {
+       bus-num = <0>;
+       status = "okay";
+
+       dspiflash: n25q12a {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               reg = <0>;
+               spi-max-frequency = <1000000>; /* input clock */
+       };
+
 };
 
 &i2c0 {
index 280e9592ec8cd25244eb9de07df7f85d27da2b79..85ea81e2a6896ca1d61f5ab43498b97522915eae 100644 (file)
                        clocks = <&sysclk>;
                };
 
+               dspi0: dspi@2100000 {
+                       compatible = "fsl,vf610-dspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2100000 0x0 0x10000>;
+                       interrupts = <0 64 0x4>;
+                       clock-names = "dspi";
+                       clocks = <&clockgen 4 0>;
+                       num-cs = <6>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+               dspi1: dspi@2110000 {
+                       compatible = "fsl,vf610-dspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2110000 0x0 0x10000>;
+                       interrupts = <0 65 0x4>;
+                       clock-names = "dspi";
+                       clocks = <&clockgen 4 0>;
+                       num-cs = <6>;
+                       big-endian;
+                       status = "disabled";
+               };
+
                ifc: ifc@1530000 {
                        compatible = "fsl,ifc", "simple-bus";
                        reg = <0x0 0x1530000 0x0 0x10000>;
index 64c1c861429f5b13c272aa47f66531b6f145d10d..8622ce7c407b63359b5bd27f8ba568bb9a32e53a 100644 (file)
@@ -4,3 +4,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
index 605dbc0d6a7c292d635f9f3207ccdad486c1aee2..c4f5f60c098b3d893f7765b47ec37ad4faa50ddf 100644 (file)
@@ -3,3 +3,8 @@ CONFIG_TARGET_LS1043ARDB=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
 CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
index ea925c33f40f0e3e45fbc50a8d4975766fc89735..6c7eda36eb7311251f872441ad041c86c600d9b5 100644 (file)
@@ -3,3 +3,8 @@ CONFIG_TARGET_LS1043ARDB=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
 CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
index 307d947405ce673a8fe8b29748bfbf1019000066..3fa9b3b611eebd888ae43ad3e7afc8150e0d272f 100644 (file)
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
 
+/* DSPI */
+#define CONFIG_FSL_DSPI
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS          1
+#define CONFIG_SF_DEFAULT_CS           0
+#endif
+
 /*
  * Environment
  */