ARM64: zynqmp: Do not enable DM_MMC by default
authorMichal Simek <michal.simek@xilinx.com>
Mon, 1 Aug 2016 06:49:12 +0000 (08:49 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 2 Aug 2016 05:19:09 +0000 (07:19 +0200)
The patch:
"dm: mmc: zynq: Convert zynq to use driver model for MMC"
(sha1: 329a449f2c289b4de8f892fca1d9379ce5fd81b8)
added dependency on enabling some MMC options by default.
There are minimal ZynqMP configurations which require
only minimal configurations to be enabled to keep u-boot size
as lower as possible.

Move options to defconfig instead.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/Kconfig
configs/xilinx_zynqmp_ep_defconfig
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
configs/xilinx_zynqmp_zcu102_defconfig
configs/xilinx_zynqmp_zcu102_revB_defconfig

index 6de734f8f20f04b604294d45bc3f68bfbc89e513..a0a866ef48648899f185835d179cd06efb216be4 100644 (file)
@@ -675,9 +675,6 @@ config ARCH_ZYNQMP
        select CLK
        select SPL_CLK
        select DM_USB if USB
-       select DM_MMC
-       select DM_MMC_OPS
-       select BLK
 
 config TEGRA
        bool "NVIDIA Tegra"
index f702381f5756ba7380e97ffbdf8ada85e97816fd..c975c1435c650a1fb5c694b69d59640c7b75d8ce 100644 (file)
@@ -46,9 +46,11 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SPI_FLASH=y
index 0700ec24ede6af88cb58d1fe2a70815a731e618b..52eb8c9329c891902fa66643506b1e1eac515482 100644 (file)
@@ -37,9 +37,11 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
index afcae994874b1ee9352754f9fb3b3885706e9391..928806b2c42cc82f2b5bc69c6f3edee314294d8d 100644 (file)
@@ -37,9 +37,11 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
index 28d35c1edc4355920ab7c971819ae7ed94b30f1a..6a648dafe13388829e33600490ccb95c4e4bb519 100644 (file)
@@ -33,9 +33,11 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
index 2d55ae03d1930189e86c456e7b32e151dcd2e71f..c6521e87136e1dd796bebaac6c6776a406cb305a 100644 (file)
@@ -32,9 +32,11 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_DM_ETH=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
index 2c6ceb35a589de93e12040e0e34e6bb8a9d4edf5..f0378fee6879dafbb6ae717f964b98bf636af0ed 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
 CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
index 0b42734e0bc358f634ecbfe36c3f66b1e2840c23..cb810cfff7043ba3f89f500eb3bf218bac3313d7 100644 (file)
@@ -37,7 +37,9 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
 CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y