stm32f7: use stm32f7 gpio driver supporting driver model
authorVikas Manocha <vikas.manocha@st.com>
Mon, 10 Apr 2017 22:02:59 +0000 (15:02 -0700)
committerTom Rini <trini@konsulko.com>
Mon, 8 May 2017 15:57:21 +0000 (11:57 -0400)
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.

Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch/arm/include/asm/arch-stm32f7/gpio.h
board/st/stm32f746-disco/stm32f746-disco.c
configs/stm32f746-disco_defconfig
drivers/clk/clk_stm32f7.c
drivers/pinctrl/pinctrl_stm32.c
include/configs/stm32f746-disco.h

index 45999b4d2e34761083ae094fa5e0680053f9cb46..56e469e3023821b9d6843340080e40929cfa31a8 100644 (file)
@@ -7,6 +7,7 @@
 
 #ifndef _STM32_GPIO_H_
 #define _STM32_GPIO_H_
+#include <asm/gpio.h>
 
 enum stm32_gpio_port {
        STM32_GPIO_PORT_A = 0,
index 370db15bea900100dc127322beba9590f34dba62..45a2c47aa281964f3321723dd4186cc0afc7325d 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-const struct stm32_gpio_ctl gpio_ctl_gpout = {
-       .mode = STM32_GPIO_MODE_OUT,
-       .otype = STM32_GPIO_OTYPE_PP,
-       .speed = STM32_GPIO_SPEED_50M,
-       .pupd = STM32_GPIO_PUPD_NO,
-       .af = STM32_GPIO_AF0
-};
-
-static int fmc_setup_gpio(void)
-{
-       clock_setup(GPIO_B_CLOCK_CFG);
-       clock_setup(GPIO_C_CLOCK_CFG);
-       clock_setup(GPIO_D_CLOCK_CFG);
-       clock_setup(GPIO_E_CLOCK_CFG);
-       clock_setup(GPIO_F_CLOCK_CFG);
-       clock_setup(GPIO_G_CLOCK_CFG);
-       clock_setup(GPIO_H_CLOCK_CFG);
-
-       return 0;
-}
-
 int dram_init(void)
 {
        struct udevice *dev;
        struct ram_info ram;
        int rv;
 
-       rv = fmc_setup_gpio();
-       if (rv)
-               return rv;
-
        rv = uclass_get_device(UCLASS_RAM, 0, &dev);
        if (rv) {
                debug("DRAM init failed: %d\n", rv);
@@ -73,37 +48,21 @@ int dram_init(void)
        return rv;
 }
 
-int uart_setup_gpio(void)
-{
-       clock_setup(GPIO_A_CLOCK_CFG);
-       clock_setup(GPIO_B_CLOCK_CFG);
-       return 0;
-}
-
 #ifdef CONFIG_ETH_DESIGNWARE
-
 static int stmmac_setup(void)
 {
        clock_setup(SYSCFG_CLOCK_CFG);
        /* Set >RMII mode */
        STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
-
-       clock_setup(GPIO_A_CLOCK_CFG);
-       clock_setup(GPIO_C_CLOCK_CFG);
-       clock_setup(GPIO_G_CLOCK_CFG);
        clock_setup(STMMAC_CLOCK_CFG);
 
        return 0;
 }
-#endif
 
-#ifdef CONFIG_STM32_QSPI
-
-static int qspi_setup(void)
+int board_early_init_f(void)
 {
-       clock_setup(GPIO_B_CLOCK_CFG);
-       clock_setup(GPIO_D_CLOCK_CFG);
-       clock_setup(GPIO_E_CLOCK_CFG);
+       stmmac_setup();
+
        return 0;
 }
 #endif
@@ -113,29 +72,6 @@ u32 get_board_rev(void)
        return 0;
 }
 
-int board_early_init_f(void)
-{
-       int res;
-
-       res = uart_setup_gpio();
-       if (res)
-               return res;
-
-#ifdef CONFIG_ETH_DESIGNWARE
-       res = stmmac_setup();
-       if (res)
-               return res;
-#endif
-
-#ifdef CONFIG_STM32_QSPI
-       res = qspi_setup();
-       if (res)
-               return res;
-#endif
-
-       return 0;
-}
-
 int board_init(void)
 {
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
index 57a0d610df3f01bbb7ef467a6f3228ecbe80ccff..4322aad14d2054647f9094c5e422cf92113d1706 100644 (file)
@@ -24,6 +24,7 @@ CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIMER=y
 CONFIG_OF_CONTROL=y
+CONFIG_DM_SEQ_ALIAS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_CLK=y
@@ -49,3 +50,6 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_STM32=y
 CONFIG_RAM=y
 CONFIG_STM32_SDRAM=y
+CONFIG_DM_GPIO=y
+CONFIG_STM32F7_GPIO=y
+CONFIG_SYS_MALLOC_F_LEN=0xC00
index 0d86395d4761ce88d1b5a8863badd669641c86c8..da3c204ff50310983418548c55785c258b46f7fb 100644 (file)
@@ -228,56 +228,17 @@ static int stm32_clk_enable(struct clk *clk)
 void clock_setup(int peripheral)
 {
        switch (peripheral) {
-       case GPIO_A_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN);
-               break;
-       case GPIO_B_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN);
-               break;
-       case GPIO_C_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN);
-               break;
-       case GPIO_D_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN);
-               break;
-       case GPIO_E_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN);
-               break;
-       case GPIO_F_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN);
-               break;
-       case GPIO_G_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN);
-               break;
-       case GPIO_H_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN);
-               break;
-       case GPIO_I_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN);
-               break;
-       case GPIO_J_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN);
-               break;
-       case GPIO_K_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN);
-               break;
        case SYSCFG_CLOCK_CFG:
                setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
                break;
        case TIMER2_CLOCK_CFG:
                setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
                break;
-       case FMC_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN);
-               break;
        case STMMAC_CLOCK_CFG:
                setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
                setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
                setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
                break;
-       case QSPI_CLOCK_CFG:
-               setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_QSPI_EN);
-               break;
        default:
                break;
        }
index 0e74d051c30475d2903a4acbcb7289c0a5a724de..01f0429a39925457f49a73e7b1142a117ffe602a 100644 (file)
@@ -121,11 +121,16 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev,
                if (len < 0)
                        return -EINVAL;
                for (i = 0; i < len; i++) {
+                       struct gpio_desc desc;
                        debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
                        prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
                        prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node);
-
-                       rv = stm32_gpio_config(&gpio_dsc, &gpio_ctl);
+                       rv = uclass_get_device_by_seq(UCLASS_GPIO,
+                                                     gpio_dsc.port, &desc.dev);
+                       if (rv)
+                               return rv;
+                       desc.offset = gpio_dsc.pin;
+                       rv = stm32_gpio_config(&desc, &gpio_ctl);
                        debug("%s: rv = %d\n\n", __func__, rv);
                        if (rv)
                                return rv;
index de3d661d60a856cce2769f97d7fd7d0bff2b627e..e917ba9162fb1d1261851957f329d69ea2ec384a 100644 (file)
@@ -30,7 +30,6 @@
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_SIZE                        (8 << 10)
 
-#define CONFIG_STM32_GPIO
 #define CONFIG_STM32_FLASH
 #define CONFIG_STM32X7_SERIAL