bool "Support bcmnsp"
select CPU_V7
+config TARGET_BCMNS2
+ bool "Support Broadcom Northstar2"
+ select ARM64
+ help
+ Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
+ ARMv8 Cortex-A57 processors targeting a broad range of networking
+ applications
+
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
+source "board/broadcom/bcmns2/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
--- /dev/null
+/*
+ * (C) Copyright 2016 Broadcom Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region ns2_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0xff80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = ns2_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
--- /dev/null
+/*
+ * Configuration for Broadcom NS2.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BCM_NORTHSTAR2_H
+#define __BCM_NORTHSTAR2_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_HOSTNAME northstar2
+
+/* Physical Memory Map */
+#define V2M_BASE 0x80000000
+#define PHYS_SDRAM_1 V2M_BASE
+
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1_SIZE (4UL * SZ_1G)
+#define PHYS_SDRAM_2_SIZE (4UL * SZ_1G)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* define text_base for U-boot image */
+#define CONFIG_SYS_TEXT_BASE 0x85000000
+#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00)
+#define CONFIG_SYS_LOAD_ADDR 0x90000000
+#define CONFIG_SYS_MALLOC_LEN SZ_16M
+
+/* Serial Configuration */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 25000000
+#define CONFIG_SYS_NS16550_COM1 0x66100000
+#define CONFIG_SYS_NS16550_COM2 0x66110000
+#define CONFIG_SYS_NS16550_COM3 0x66120000
+#define CONFIG_SYS_NS16550_COM4 0x66130000
+#define CONFIG_CONS_INDEX 4
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_NOWHERE
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE SZ_1K
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* version string, parser, etc */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_SYS_LONGHELP
+
+#endif /* __BCM_NORTHSTAR2_H */