F: drivers/mtd/jedec_flash.c
COLDFIRE
-M: Jason Jin <jason.jin@freescale.com>
+M: Huan Wang <alison.wang@freescale.com>
+M: Angelo Dureghello <angelo@sysam.it>
S: Maintained
T: git git://git.denx.de/u-boot-coldfire.git
F: arch/m68k/
UBI
M: Kyungmin Park <kmpark@infradead.org>
+M: Heiko Schocher <hs@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-ubi.git
F: drivers/mtd/ubi/
-path ./include/config/auto.conf -newer $(KCONFIG_CONFIG)))
ifneq ($(autoconf_is_current),)
include $(srctree)/config.mk
+include $(srctree)/arch/$(ARCH)/Makefile
endif
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
#########################################################################
# U-Boot objects....order is important (i.e. start must be first)
-head-y := $(CPUDIR)/start.o
-head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
-head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
-
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
libs-y += lib/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
-libs-y += $(CPUDIR)/
libs-$(CONFIG_OF_EMBED) += dts/
-libs-y += arch/$(ARCH)/lib/
libs-y += fs/
libs-y += net/
libs-y += disk/
libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
libs-y += common/
-libs-y += lib/libfdt/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
libs-y += test/dm/
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
-libs-y += arch/$(ARCH)/imx-common/
-endif
-
-ifneq (,$(filter $(SOC), armada-xp kirkwood))
-libs-y += arch/$(ARCH)/mvebu-common/
-endif
-
-libs-$(CONFIG_ARM) += arch/arm/cpu/
-libs-$(CONFIG_PPC) += arch/powerpc/cpu/
-
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-y := $(sort $(libs-y))
$(objtree)/tools/ifdtool -w \
$(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) \
+ u-boot.tmp
mv u-boot.tmp $@
OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION
- Address, size and partition on the MMC to load U-Boot from
+ Address and partition on the MMC to load U-Boot from
when the MMC is being used in raw mode.
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+ Partition on the MMC to load U-Boot from when the MMC is being
+ used in raw mode
+
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
Sector to load kernel uImage from when MMC is being
used in raw mode (for Falcon mode)
parameters from when MMC is being used in raw mode
(for falcon mode)
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
+ Partition on the MMC to load U-Boot from when the MMC is being
+ used in fs mode
+
CONFIG_SPL_FAT_SUPPORT
Support for fs/fat/libfat.o in SPL binary
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/arc/cpu/$(CPU)/start.o
+
+libs-y += arch/arc/cpu/$(CPU)/
+libs-y += arch/arc/lib/
bool "Support mx35pdk"
select CPU_ARM1136
-config TARGET_RPI_B
- bool "Support rpi_b"
+config TARGET_RPI
+ bool "Support rpi"
select CPU_ARM1176
config TARGET_TNETV107X_EVM
bool "Panasonic UniPhier platform"
select CPU_V7
select SUPPORT_SPL
+ select OF_CONTROL if !SPL_BUILD
endchoice
source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/pxa255_idp/Kconfig"
-source "board/raspberrypi/rpi_b/Kconfig"
+source "board/raspberrypi/rpi/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
source "board/ronetix/pm9g45/Kconfig"
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/arm/cpu/$(CPU)/start.o
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+endif
+endif
+
+libs-y += arch/arm/cpu/$(CPU)/
+libs-y += arch/arm/cpu/
+libs-y += arch/arm/lib/
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+libs-y += arch/arm/imx-common/
+endif
+else
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
+libs-y += arch/arm/imx-common/
+endif
+endif
+
+ifneq (,$(filter $(SOC), armada-xp kirkwood))
+libs-y += arch/arm/mvebu-common/
+endif
* used. But it not correct to assume that romcode structure
* encoding would be same as u-boot. So use the defined offsets.
*/
- gd->arch.omap_boot_params.omap_bootdevice = boot_device =
- *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+ boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+#if defined(BOOT_DEVICE_NAND_I2C)
+ /*
+ * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
+ * Otherwise the SPL boot IF can't handle this device correctly.
+ * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
+ * Draco leads to this boot-device passed to SPL from the BootROM.
+ */
+ if (boot_device == BOOT_DEVICE_NAND_I2C)
+ boot_device = BOOT_DEVICE_NAND;
+#endif
+ gd->arch.omap_boot_params.omap_bootdevice = boot_device;
gd->arch.omap_boot_params.ch_flags =
*((u8 *)(rom_params + CH_FLAGS_OFFSET));
}
}
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
/*
* We get different values for QSPI_1 and QSPI_4 being used, but
* don't actually care about this difference. Rather than
emif1_enabled = 1;
emif2_enabled = 1;
break;
- } else if (valid == 1) {
+ }
+
+ if (valid == 1)
emif1_enabled = 1;
- } else if (valid == 2) {
+
+ if (valid == 2)
emif2_enabled = 1;
- }
}
-
}
static void do_bug0039_workaround(u32 base)
config TARGET_DRA7XX_EVM
bool "TI DRA7XX"
+config TARGET_BEAGLE_X15
+ bool "BeagleBoard X15"
+
endchoice
config SYS_SOC
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
+source "board/ti/beagle_x15/Kconfig"
endif
.mpu.value = VDD_MPU_DRA752,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.eve.value = VDD_EVE_DRA752,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.gpu.value = VDD_GPU_DRA752,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.core.value = VDD_CORE_DRA752,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
.iva.value = VDD_IVA_DRA752,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
};
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
-void hw_data_init(void)
+void __weak hw_data_init(void)
{
u32 omap_rev = omap_revision();
struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_status = 0x4A002134,
+ .control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518,
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
.cm_clkmode_dpll_gmac = 0x4a0052a8,
+ .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
/* cm1.mpu */
.cm_gmac_gmac_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
+ .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700,
.mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
const u32 **regs,
u32 *size)
{
default "uniphier"
config SYS_CONFIG_NAME
- default "ph1_pro4" if MACH_PH1_PRO4
- default "ph1_ld4" if MACH_PH1_LD4
- default "ph1_sld8" if MACH_PH1_SLD8
+ default "uniphier"
+
+config UNIPHIER_SMP
+ bool
choice
prompt "UniPhier SoC select"
config MACH_PH1_PRO4
bool "PH1-Pro4"
+ select UNIPHIER_SMP
config MACH_PH1_LD4
bool "PH1-LD4"
endchoice
+choice
+ prompt "UniPhier Support Card select"
+ optional
+
+config PFC_MICRO_SUPPORT_CARD
+ bool "Support card with PFC CPLD"
+ help
+ This option provides support for the expansion board with PFC
+ original address mapping.
+
+ Say Y to use the on-board UART, Ether, LED devices.
+
+config DCC_MICRO_SUPPORT_CARD
+ bool "Support card with DCC CPLD"
+ help
+ This option provides support for the expansion board with DCC-
+ arranged address mapping that is compatible with legacy UniPhier
+ reference boards.
+
+ Say Y to use the on-board UART, Ether, LED devices.
+
+endchoice
+
config CMD_PINMON
bool "Enable boot mode pins monitor command"
depends on !SPL_BUILD
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
obj-y += dram_init.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
+obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/board.h>
+
+int board_early_init_r(void)
+{
+ uniphier_board_late_init();
+ return 0;
+}
#endif
}
-static void nand_denali_fixup(void)
-{
-#if defined(CONFIG_NAND_DENALI) && \
- (defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4))
- /*
- * The Denali NAND controller on some of UniPhier SoCs does not
- * automatically query the device parameters. For those SoCs,
- * some registers must be set after the device is probed.
- */
- void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
- struct mtd_info *mtd;
- struct nand_chip *chip;
-
- if (nand_curr_device < 0 ||
- nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
- /* NAND was not detected. Just return. */
- return;
- }
-
- mtd = &nand_info[nand_curr_device];
- chip = mtd->priv;
-
- writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK);
- writel(0, denali_reg + DEVICE_WIDTH);
- writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE);
- writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE);
- writel(1, denali_reg + DEVICES_CONNECTED);
-
- /*
- * chip->scan_bbt in nand_scan_tail() has been skipped.
- * It should be done in here.
- */
- chip->scan_bbt(mtd);
-#endif
-}
-
int board_late_init(void)
{
puts("MODE: ");
case BOOT_DEVICE_MMC1:
printf("eMMC Boot\n");
setenv("bootmode", "emmcboot");
- nand_denali_fixup();
break;
case BOOT_DEVICE_NAND:
printf("NAND Boot\n");
case BOOT_DEVICE_NOR:
printf("NOR Boot\n");
setenv("bootmode", "norboot");
- nand_denali_fixup();
break;
default:
printf("Unsupported Boot Mode\n");
#define IS_SSC(x) ((IS_SPL_TEXT_AREA(x)) || \
(IS_INIT_STACK_AREA(x)))
#define IS_EXT(x) ((x) < 0x100)
-#define IS_REG(x) (0x500 <= (x) && (x) < 0x700)
+
+/* 0x20000000-0x2fffffff, 0xf0000000-0xffffffff are only used by PH1-sLD3 */
+#define IS_REG(x) (0x200 <= (x) && (x) < 0x300) || \
+ (0x500 <= (x) && (x) < 0x700) || \
+ (0xf00 <= (x))
+
#define IS_DDR(x) (0x800 <= (x) && (x) < 0xf00)
#define MMU_FLAGS(x) (IS_SSC(x)) ? SSC : \
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
- if (readl(SBBASE0) & 0x1) {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x3effffff: memory bank (31MB)
- * 0x03f00000-0x3fffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- } else {
+ if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x00000000-0x01ffffff: mask ROM
+ * 0x02000000-0x3effffff: memory bank (31MB)
+ * 0x03f00000-0x3fffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
}
#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#if !defined(CONFIG_SPL_BUILD)
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
}
#endif
+int check_support_card(void)
+{
+ printf("SC: Micro Support Card ");
+ return support_card_show_revision();
+}
+
void support_card_init(void)
{
/*
support_card_reset_deassert();
}
-int check_support_card(void)
-{
- printf("SC: Micro Support Card ");
- return support_card_show_revision();
-}
-
#if defined(CONFIG_SMC911X)
#include <netdev.h>
#if !defined(CONFIG_SYS_NO_FLASH)
#include <mtd/cfi_flash.h>
+#include <asm/arch/sbc-regs.h>
-#if CONFIG_SYS_MAX_FLASH_BANKS > 1
-static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] =
- CONFIG_SYS_FLASH_BANKS_LIST;
+struct memory_bank {
+ phys_addr_t base;
+ unsigned long size;
+};
-phys_addr_t cfi_flash_bank_addr(int i)
-{
- return flash_banks_list[i];
-}
-#endif
-
-int mem_is_flash(phys_addr_t base)
+static int mem_is_flash(const struct memory_bank *mem)
{
const int loop = 128;
u32 *scratch_addr;
int ret = 1;
int i;
- scratch_addr = map_physmem(base + 0x01e00000,
- sizeof(u32) * loop, MAP_NOCACHE);
+ /* just in case, use the tail of the memory bank */
+ scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
+ sizeof(u32) * loop, MAP_NOCACHE);
for (i = 0; i < loop; i++, scratch_addr++) {
saved_value = readl(scratch_addr);
return ret;
}
-int board_flash_wp_on(void)
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+ /* {address, size} */
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+ {0x02000000, 0x01f00000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+ {0x00000000, 0x01f00000},
+};
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+ {0x04000000, 0x04000000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+ {0x00000000, 0x04000000},
+ {0x04000000, 0x04000000},
+};
+#endif
+
+static const struct memory_bank
+*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
+
+phys_addr_t cfi_flash_bank_addr(int i)
{
- int i;
- int ret = 1;
+ return flash_banks_list[i]->base;
+}
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- if (mem_is_flash(cfi_flash_bank_addr(i))) {
- /*
- * We found at least one flash.
- * We need to return 0 and call flash_init().
- */
- ret = 0;
- }
-#if CONFIG_SYS_MAX_FLASH_BANKS > 1
- else {
- /*
- * We might have a SRAM here.
- * To prevent SRAM data from being destroyed,
- * we set dummy address (SDRAM).
- */
- flash_banks_list[i] = 0x80000000 + 0x10000 * i;
+unsigned long cfi_flash_bank_size(int i)
+{
+ return flash_banks_list[i]->size;
+}
+
+static void detect_num_flash_banks(void)
+{
+ const struct memory_bank *memory_bank, *end;
+
+ cfi_flash_num_flash_banks = 0;
+
+ if (boot_is_swapped()) {
+ memory_bank = memory_banks_boot_swap_on;
+ end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
+ } else {
+ memory_bank = memory_banks_boot_swap_off;
+ end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
+ }
+
+ for (; memory_bank < end; memory_bank++) {
+ if (cfi_flash_num_flash_banks >=
+ CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
+ break;
+
+ if (mem_is_flash(memory_bank)) {
+ flash_banks_list[cfi_flash_num_flash_banks] =
+ memory_bank;
+
+ debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
+ memory_bank->base, memory_bank->size);
+ cfi_flash_num_flash_banks++;
}
-#endif
}
- return ret;
+ debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
+}
+#else /* ONFIG_SYS_NO_FLASH */
+void detect_num_flash_banks(void)
+{
+};
+#endif /* ONFIG_SYS_NO_FLASH */
+
+void support_card_late_init(void)
+{
+ detect_num_flash_banks();
}
-#endif
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-venice2.dtb
+dtb-$(CONFIG_ARCH_UNIPHIER) += \
+ uniphier-ph1-sld3-ref.dtb \
+ uniphier-ph1-pro4-ref.dtb \
+ uniphier-ph1-ld4-ref.dtb \
+ uniphier-ph1-sld8-ref.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-LD4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld4.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-LD4 Reference Board";
+ compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-LD4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-ld4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-Pro4 Reference Board";
+ compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-pro4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58780000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58781000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58782000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58783000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ /* i2c4 does not exist */
+
+ i2c5: i2c@58785000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58785000 0x80>;
+ clock-frequency = <400000>;
+ status = "ok";
+ };
+
+ i2c6: i2c@58786000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58786000 0x80>;
+ clock-frequency = <400000>;
+ status = "ok";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-sLD3 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld3.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-sLD3 Reference Board";
+ compatible = "panasonic,ph1-sld3-ref", "panasonic,ph1-sld3";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-sLD3 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-sld3";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ usb3: usb@5a830100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a830100 0x100>;
+ };
+
+ nand: nand@f8000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld8.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-sLD8 Reference Board";
+ compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-sld8";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
#else
#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
+#define BOOT_DEVICE_NAND_I2C 6
#if defined(CONFIG_AM33XX)
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
* };
*/
+#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
+
+/*
+ * 0x2..0xf from:
+ * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733
+ * 0x10, 0x11 from swarren's testing
+ */
+#define BCM2835_BOARD_REV_B_I2C0_2 0x2
+#define BCM2835_BOARD_REV_B_I2C0_3 0x3
+#define BCM2835_BOARD_REV_B_I2C1_4 0x4
+#define BCM2835_BOARD_REV_B_I2C1_5 0x5
+#define BCM2835_BOARD_REV_B_I2C1_6 0x6
+#define BCM2835_BOARD_REV_A_7 0x7
+#define BCM2835_BOARD_REV_A_8 0x8
+#define BCM2835_BOARD_REV_A_9 0x9
+#define BCM2835_BOARD_REV_B_REV2_d 0xd
+#define BCM2835_BOARD_REV_B_REV2_e 0xe
+#define BCM2835_BOARD_REV_B_REV2_f 0xf
+#define BCM2835_BOARD_REV_B_PLUS 0x10
+#define BCM2835_BOARD_REV_CM 0x11
+
+struct bcm2835_mbox_tag_get_board_rev {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ } req;
+ struct {
+ u32 rev;
+ } resp;
+ } body;
+};
+
#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003
struct bcm2835_mbox_tag_get_mac_address {
/* TPS659038 */
#define TPS659038_I2C_SLAVE_ADDR 0x58
-#define TPS659038_REG_ADDR_SMPS12_MPU 0x23
-#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B
-#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F
-#define TPS659038_REG_ADDR_SMPS7_CORE 0x33
-#define TPS659038_REG_ADDR_SMPS8_IVA 0x37
+#define TPS659038_REG_ADDR_SMPS12 0x23
+#define TPS659038_REG_ADDR_SMPS45 0x2B
+#define TPS659038_REG_ADDR_SMPS6 0x2F
+#define TPS659038_REG_ADDR_SMPS7 0x33
+#define TPS659038_REG_ADDR_SMPS8 0x37
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define V_OSCK 20000000 /* Clock output from T2 */
#else
#define V_OSCK 19200000 /* Clock output from T2 */
#define CONTROL_CORE_ID_CODE 0x4A002204
#define CONTROL_WKUP_ID_CODE 0x4AE0C204
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
#else
#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
* much larger) and do not, at this time, make use of the additional
* space.
*/
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
#else
defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
+void support_card_late_init(void);
int check_support_card(void);
#else
#define support_card_reset() do {} while (0)
#define support_card_init() do {} while (0)
+#define support_card_late_init() do {} while (0)
static inline int check_support_card(void)
{
return 0;
support_card_init();
}
+static inline void uniphier_board_late_init(void)
+{
+ support_card_late_init();
+}
+
#endif /* ARCH_BOARD_H */
--- /dev/null
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h even if GPIO is not supported.
+ */
extern struct prcm_regs const omap4_prcm;
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
+extern struct dplls dra7xx_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+extern struct pmic_data tps659038;
+
void hw_data_init(void);
const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/avr32/cpu/start.o
+
+libs-y += arch/avr32/cpu/
+libs-y += arch/avr32/lib/
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/blackfin/cpu/start.o
+
+libs-y += arch/blackfin/cpu/
+libs-y += arch/blackfin/lib/
#ifdef __KERNEL__
+#include <linux/compiler.h>
#include <asm/blackfin.h>
-#define __iomem
-
static inline void sync(void)
{
SSYNC();
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/m68k/cpu/$(CPU)/start.o
+
+libs-y += arch/m68k/cpu/$(CPU)/
+libs-y += arch/m68k/lib/
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/microblaze/cpu/start.o
+
+libs-y += arch/microblaze/cpu/
+libs-y += arch/microblaze/lib/
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/mips/cpu/$(CPU)/start.o
+
+libs-y += arch/mips/cpu/$(CPU)/
+libs-y += arch/mips/lib/
#ifndef _ASM_MIPS_UNALIGNED_H
#define _ASM_MIPS_UNALIGNED_H
-#include <compiler.h>
+#include <linux/compiler.h>
#if defined(__MIPSEB__)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/nds32/cpu/$(CPU)/start.o
+
+libs-y += arch/nds32/cpu/$(CPU)/
+libs-y += arch/nds32/lib/
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/nios2/cpu/start.o
+
+libs-y += arch/nios2/cpu/
+libs-y += arch/nios2/lib/
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/openrisc/cpu/start.o
+
+libs-y += arch/openrisc/cpu/
+libs-y += arch/openrisc/lib/
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/powerpc/cpu/$(CPU)/start.o
+head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
+head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
+
+libs-y += arch/powerpc/cpu/$(CPU)/
+libs-y += arch/powerpc/cpu/
+libs-y += arch/powerpc/lib/
config TARGET_ESTEEM192E
bool "Support ESTEEM192E"
-config TARGET_HERMES
- bool "Support hermes"
-
config TARGET_IP860
bool "Support IP860"
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
-source "board/hermes/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/kup/kup4k/Kconfig"
* I owe him a free beer. - wd]
*/
-#if defined(CONFIG_HERMES) || \
- defined(CONFIG_IP860) || \
+#if defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
mac_read_from_eeprom();
#endif
-#ifdef CONFIG_HERMES
- if ((gd->board_type >> 16) == 2)
- bd->bi_ethspeed = gd->board_type & 0xFFFF;
- else
- bd->bi_ethspeed = 0xFFFF;
-#endif
-
#ifdef CONFIG_CMD_NET
/* kept around for legacy kernels only ... ignore the next section */
eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
misc_init_r();
#endif
-#ifdef CONFIG_HERMES
- if (bd->bi_ethspeed != 0xFFFF)
- hermes_start_lxt980((int) bd->bi_ethspeed);
-#endif
-
#if defined(CONFIG_CMD_KGDB)
WATCHDOG_RESET();
puts("KGDB: ");
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sandbox/cpu/start.o
+
+libs-y += arch/sandbox/cpu/
+libs-y += arch/sandbox/lib/
done:
closedir(dir);
+ free(fname);
return ret;
}
state->write_ram_buf = true;
state->ram_buf_fname = arg;
- if (os_read_ram_buf(arg)) {
+ err = os_read_ram_buf(arg);
+ if (err) {
printf("Failed to read RAM buffer\n");
return err;
}
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sh/cpu/$(CPU)/start.o
+
+libs-y += arch/sh/cpu/$(CPU)/
+libs-y += arch/sh/lib/
#include <asm/unaligned-sh4a.h>
#else
/* Otherwise, SH can't handle unaligned accesses. */
-#include <compiler.h>
+#include <linux/compiler.h>
#if defined(__BIG_ENDIAN__)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sparc/cpu/$(CPU)/start.o
+
+libs-y += arch/sparc/cpu/$(CPU)/
+libs-y += arch/sparc/lib/
to work correctly. It is not exhaustive but can save time by
detecting obvious failures.
+config MARK_GRAPHICS_MEM_WRCOMB
+ bool "Mark graphics memory as write-combining."
+ default n
+ help
+ The graphics performance may increase if the graphics
+ memory is set as write-combining cache type. This option
+ enables marking the graphics memory as write-combining.
+
+menu "Display"
+
+config FRAMEBUFFER_SET_VESA_MODE
+ prompt "Set framebuffer graphics resolution"
+ bool
+ help
+ Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
+
+choice
+ prompt "framebuffer graphics resolution"
+ default FRAMEBUFFER_VESA_MODE_117
+ depends on FRAMEBUFFER_SET_VESA_MODE
+ help
+ This option sets the resolution used for the coreboot framebuffer (and
+ bootsplash screen).
+
+config FRAMEBUFFER_VESA_MODE_100
+ bool "640x400 256-color"
+
+config FRAMEBUFFER_VESA_MODE_101
+ bool "640x480 256-color"
+
+config FRAMEBUFFER_VESA_MODE_102
+ bool "800x600 16-color"
+
+config FRAMEBUFFER_VESA_MODE_103
+ bool "800x600 256-color"
+
+config FRAMEBUFFER_VESA_MODE_104
+ bool "1024x768 16-color"
+
+config FRAMEBUFFER_VESA_MODE_105
+ bool "1024x7686 256-color"
+
+config FRAMEBUFFER_VESA_MODE_106
+ bool "1280x1024 16-color"
+
+config FRAMEBUFFER_VESA_MODE_107
+ bool "1280x1024 256-color"
+
+config FRAMEBUFFER_VESA_MODE_108
+ bool "80x60 text"
+
+config FRAMEBUFFER_VESA_MODE_109
+ bool "132x25 text"
+
+config FRAMEBUFFER_VESA_MODE_10A
+ bool "132x43 text"
+
+config FRAMEBUFFER_VESA_MODE_10B
+ bool "132x50 text"
+
+config FRAMEBUFFER_VESA_MODE_10C
+ bool "132x60 text"
+
+config FRAMEBUFFER_VESA_MODE_10D
+ bool "320x200 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_10E
+ bool "320x200 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_10F
+ bool "320x200 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_110
+ bool "640x480 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_111
+ bool "640x480 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_112
+ bool "640x480 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_113
+ bool "800x600 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_114
+ bool "800x600 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_115
+ bool "800x600 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_116
+ bool "1024x768 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_117
+ bool "1024x768 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_118
+ bool "1024x768 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_119
+ bool "1280x1024 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_11A
+ bool "1280x1024 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_11B
+ bool "1280x1024 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_USER
+ bool "Manually select VESA mode"
+
+endchoice
+
+# Map the config names to an integer (KB).
+config FRAMEBUFFER_VESA_MODE
+ prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
+ hex
+ default 0x100 if FRAMEBUFFER_VESA_MODE_100
+ default 0x101 if FRAMEBUFFER_VESA_MODE_101
+ default 0x102 if FRAMEBUFFER_VESA_MODE_102
+ default 0x103 if FRAMEBUFFER_VESA_MODE_103
+ default 0x104 if FRAMEBUFFER_VESA_MODE_104
+ default 0x105 if FRAMEBUFFER_VESA_MODE_105
+ default 0x106 if FRAMEBUFFER_VESA_MODE_106
+ default 0x107 if FRAMEBUFFER_VESA_MODE_107
+ default 0x108 if FRAMEBUFFER_VESA_MODE_108
+ default 0x109 if FRAMEBUFFER_VESA_MODE_109
+ default 0x10A if FRAMEBUFFER_VESA_MODE_10A
+ default 0x10B if FRAMEBUFFER_VESA_MODE_10B
+ default 0x10C if FRAMEBUFFER_VESA_MODE_10C
+ default 0x10D if FRAMEBUFFER_VESA_MODE_10D
+ default 0x10E if FRAMEBUFFER_VESA_MODE_10E
+ default 0x10F if FRAMEBUFFER_VESA_MODE_10F
+ default 0x110 if FRAMEBUFFER_VESA_MODE_110
+ default 0x111 if FRAMEBUFFER_VESA_MODE_111
+ default 0x112 if FRAMEBUFFER_VESA_MODE_112
+ default 0x113 if FRAMEBUFFER_VESA_MODE_113
+ default 0x114 if FRAMEBUFFER_VESA_MODE_114
+ default 0x115 if FRAMEBUFFER_VESA_MODE_115
+ default 0x116 if FRAMEBUFFER_VESA_MODE_116
+ default 0x117 if FRAMEBUFFER_VESA_MODE_117
+ default 0x118 if FRAMEBUFFER_VESA_MODE_118
+ default 0x119 if FRAMEBUFFER_VESA_MODE_119
+ default 0x11A if FRAMEBUFFER_VESA_MODE_11A
+ default 0x11B if FRAMEBUFFER_VESA_MODE_11B
+ default 0x117 if FRAMEBUFFER_VESA_MODE_USER
+
+endmenu
+
source "arch/x86/cpu/ivybridge/Kconfig"
source "board/coreboot/coreboot/Kconfig"
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/x86/cpu/start.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+head-y += arch/x86/cpu/start16.o
+head-y += arch/x86/cpu/resetvec.o
+endif
+
+libs-y += arch/x86/cpu/
+libs-y += arch/x86/lib/
obj-y += interrupts.o cpu.o call64.o
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
+obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
+obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
+obj-y += lapic.o
obj-$(CONFIG_PCI) += pci.o
+obj-y += turbo.o
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
LDPPFLAGS += -DRESET_SEG_START=0xffff0000
LDPPFLAGS += -DRESET_SEG_SIZE=0x10000
-LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
-LDPPFLAGS += -DSTART_16=0xf800
+LDPPFLAGS += -DRESET_VEC_LOC=0xfffffff0
+LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16)
+LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)"
return 0;
}
-int board_early_init_r(void)
-{
- /* CPU Speed to 100MHz */
- gd->cpu_clk = 100000000;
-
- /* Crystal is 33.000MHz */
- gd->bus_clk = 33000000;
-
- return 0;
-}
-
int print_cpuinfo(void)
{
return default_print_cpuinfo();
* SUCH DAMAGE.
*/
-#include <compiler.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
#include <asm/arch/ipchecksum.h>
unsigned short ipchksum(const void *vptr, unsigned long nbytes)
{
struct gdt_ptr gdt;
- gdt.len = (num_entries * 8) - 1;
+ gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
gdt.ptr = (u32)boot_gdt;
asm volatile("lgdtl %0\n" : : "m" (gdt));
(ulong)&id->arch.gd_addr, 0xfffff);
/* 16-bit CS: code, read/execute, 64 kB, base 0 */
- gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
/* 16-bit DS: data, read/write, 64 kB, base 0 */
- gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
+
+ gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
load_ds(X86_GDT_ENTRY_32BIT_DS);
return 0;
}
-int x86_cpu_init_r(void)
-{
- /* Initialize core interrupt and exception functionality of CPU */
- cpu_init_interrupts();
- return 0;
-}
-int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
-
void x86_enable_caches(void)
{
unsigned long cr0;
#include <linux/compiler.h>
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
+#include <asm/i8259.h>
DECLARE_GLOBAL_DATA_PTR;
int irq_entry_size = irq_1 - irq_0;
void *irq_entry = (void *)irq_0;
- /* Just in case... */
- disable_interrupts();
-
/* Setup the IDT */
for (i = 0; i < 256; i++) {
idt[i].access = 0x8e;
load_idt(&idt_ptr);
- /* It is now safe to enable interrupts */
- enable_interrupts();
-
return 0;
}
return flags & X86_EFLAGS_IF;
}
+int interrupt_init(void)
+{
+ /* Just in case... */
+ disable_interrupts();
+
+#ifdef CONFIG_SYS_PCAT_INTERRUPTS
+ /* Initialize the master/slave i8259 pic */
+ i8259_init();
+#endif
+
+ /* Initialize core interrupt and exception functionality of CPU */
+ cpu_init_interrupts();
+
+ /* It is now safe to enable interrupts */
+ enable_interrupts();
+
+ return 0;
+}
+
/* IRQ Low-Level Service Routine */
void irq_llsr(struct irq_regs *regs)
{
DECLARE_INTERRUPT(253) \
DECLARE_INTERRUPT(254) \
DECLARE_INTERRUPT(255));
-
-#if defined(CONFIG_INTEL_CORE_ARCH)
-/*
- * Get the number of CPU time counter ticks since it was read first time after
- * restart. This yields a free running counter guaranteed to take almost 6
- * years to wrap around even at 100GHz clock rate.
- */
-u64 get_ticks(void)
-{
- u64 now_tick = rdtsc();
-
- if (!gd->arch.tsc_base)
- gd->arch.tsc_base = now_tick;
-
- return now_tick - gd->arch.tsc_base;
-}
-
-#define PLATFORM_INFO_MSR 0xce
-
-unsigned long get_tbclk(void)
-{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
-
- ratio = (platform_info >> 8) & 0xff;
- return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */
-}
-#endif
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += bd82x6x.o
obj-y += car.o
obj-y += cpu.o
obj-y += early_init.o
obj-y += early_me.o
+obj-y += gma.o
obj-y += lpc.o
obj-y += me_status.o
+obj-y += model_206ax.o
obj-y += microcode_intel.o
+obj-y += northbridge.o
+obj-y += pch.o
obj-y += pci.o
obj-y += report_platform.o
+obj-y += sata.o
obj-y += sdram.o
+obj-y += usb_ehci.o
+obj-y += usb_xhci.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/lapic.h>
+#include <asm/pci.h>
+#include <asm/arch/bd82x6x.h>
+#include <asm/arch/model_206ax.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+void bd82x6x_pci_init(pci_dev_t dev)
+{
+ u16 reg16;
+ u8 reg8;
+
+ debug("bd82x6x PCI init.\n");
+ /* Enable Bus Master */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MASTER;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /* This device has no interrupt */
+ pci_write_config8(dev, INTR, 0xff);
+
+ /* disable parity error response and SERR */
+ reg16 = pci_read_config16(dev, BCTRL);
+ reg16 &= ~(1 << 0);
+ reg16 &= ~(1 << 1);
+ pci_write_config16(dev, BCTRL, reg16);
+
+ /* Master Latency Count must be set to 0x04! */
+ reg8 = pci_read_config8(dev, SMLT);
+ reg8 &= 0x07;
+ reg8 |= (0x04 << 3);
+ pci_write_config8(dev, SMLT, reg8);
+
+ /* Will this improve throughput of bus masters? */
+ pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+
+ /* Clear errors in status registers */
+ reg16 = pci_read_config16(dev, PSTS);
+ /* reg16 |= 0xf900; */
+ pci_write_config16(dev, PSTS, reg16);
+
+ reg16 = pci_read_config16(dev, SECSTS);
+ /* reg16 |= 0xf900; */
+ pci_write_config16(dev, SECSTS, reg16);
+}
+
+#define PCI_BRIDGE_UPDATE_COMMAND
+void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
+{
+ uint16_t command;
+
+ command = pci_read_config16(dev, PCI_COMMAND);
+ command |= PCI_COMMAND_IO;
+#ifdef PCI_BRIDGE_UPDATE_COMMAND
+ /*
+ * If we write to PCI_COMMAND, on some systems this will cause the
+ * ROM and APICs to become invisible.
+ */
+ debug("%x cmd <- %02x\n", dev, command);
+ pci_write_config16(dev, PCI_COMMAND, command);
+#else
+ printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+#endif
+}
+
+void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
+{
+ uint16_t ctrl;
+
+ ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ ctrl |= PCI_COMMAND_IO;
+ ctrl |= PCI_BRIDGE_CTL_VGA;
+ debug("%x bridge ctrl <- %04x\n", dev, ctrl);
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+
+ bd82x6x_pci_dev_enable_resources(dev);
+}
+
+int bd82x6x_init_pci_devices(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct pci_controller *hose;
+ struct x86_cpu_priv *cpu;
+ int sata_node, gma_node;
+ int ret;
+
+ hose = pci_bus_to_hose(0);
+ lpc_enable(PCH_LPC_DEV);
+ lpc_init(hose, PCH_LPC_DEV);
+ sata_node = fdtdec_next_compatible(blob, 0,
+ COMPAT_INTEL_PANTHERPOINT_AHCI);
+ if (sata_node < 0) {
+ debug("%s: Cannot find SATA node\n", __func__);
+ return -EINVAL;
+ }
+ bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
+ bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
+ bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
+
+ cpu = calloc(1, sizeof(*cpu));
+ if (!cpu)
+ return -ENOMEM;
+ model_206ax_init(cpu);
+
+ gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
+ if (gma_node < 0) {
+ debug("%s: Cannot find GMA node\n", __func__);
+ return -EINVAL;
+ }
+ ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob,
+ gma_node);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int bd82x6x_init(void)
+{
+ const void *blob = gd->fdt_blob;
+ int sata_node;
+
+ sata_node = fdtdec_next_compatible(blob, 0,
+ COMPAT_INTEL_PANTHERPOINT_AHCI);
+ if (sata_node < 0) {
+ debug("%s: Cannot find SATA node\n", __func__);
+ return -EINVAL;
+ }
+
+ bd82x6x_pci_init(PCH_DEV);
+ bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
+ northbridge_enable(PCH_DEV);
+ northbridge_init(PCH_DEV);
+
+ return 0;
+}
--- /dev/null
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pci_rom.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+struct gt_powermeter {
+ u16 reg;
+ u32 value;
+};
+
+static const struct gt_powermeter snb_pm_gt1[] = {
+ { 0xa200, 0xcc000000 },
+ { 0xa204, 0x07000040 },
+ { 0xa208, 0x0000fe00 },
+ { 0xa20c, 0x00000000 },
+ { 0xa210, 0x17000000 },
+ { 0xa214, 0x00000021 },
+ { 0xa218, 0x0817fe19 },
+ { 0xa21c, 0x00000000 },
+ { 0xa220, 0x00000000 },
+ { 0xa224, 0xcc000000 },
+ { 0xa228, 0x07000040 },
+ { 0xa22c, 0x0000fe00 },
+ { 0xa230, 0x00000000 },
+ { 0xa234, 0x17000000 },
+ { 0xa238, 0x00000021 },
+ { 0xa23c, 0x0817fe19 },
+ { 0xa240, 0x00000000 },
+ { 0xa244, 0x00000000 },
+ { 0xa248, 0x8000421e },
+ { 0 }
+};
+
+static const struct gt_powermeter snb_pm_gt2[] = {
+ { 0xa200, 0x330000a6 },
+ { 0xa204, 0x402d0031 },
+ { 0xa208, 0x00165f83 },
+ { 0xa20c, 0xf1000000 },
+ { 0xa210, 0x00000000 },
+ { 0xa214, 0x00160016 },
+ { 0xa218, 0x002a002b },
+ { 0xa21c, 0x00000000 },
+ { 0xa220, 0x00000000 },
+ { 0xa224, 0x330000a6 },
+ { 0xa228, 0x402d0031 },
+ { 0xa22c, 0x00165f83 },
+ { 0xa230, 0xf1000000 },
+ { 0xa234, 0x00000000 },
+ { 0xa238, 0x00160016 },
+ { 0xa23c, 0x002a002b },
+ { 0xa240, 0x00000000 },
+ { 0xa244, 0x00000000 },
+ { 0xa248, 0x8000421e },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt1[] = {
+ { 0xa800, 0x00000000 },
+ { 0xa804, 0x00021c00 },
+ { 0xa808, 0x00000403 },
+ { 0xa80c, 0x02001700 },
+ { 0xa810, 0x05000200 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00690500 },
+ { 0xa81c, 0x0000007f },
+ { 0xa820, 0x01002501 },
+ { 0xa824, 0x00000300 },
+ { 0xa828, 0x01000331 },
+ { 0xa82c, 0x0000000c },
+ { 0xa830, 0x00010016 },
+ { 0xa834, 0x01100101 },
+ { 0xa838, 0x00010103 },
+ { 0xa83c, 0x00041300 },
+ { 0xa840, 0x00000b30 },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0x7f000000 },
+ { 0xa84c, 0x05000008 },
+ { 0xa850, 0x00000001 },
+ { 0xa854, 0x00000004 },
+ { 0xa858, 0x00000007 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00010000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00001c00 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x06000000 },
+ { 0xa910, 0x09000200 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00590000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x04002501 },
+ { 0xa924, 0x00000100 },
+ { 0xa928, 0x03000410 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00020000 },
+ { 0xa934, 0x02070106 },
+ { 0xa938, 0x00010100 },
+ { 0xa93c, 0x00401c00 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x10000e00 },
+ { 0xa94c, 0x02000004 },
+ { 0xa950, 0x00000001 },
+ { 0xa954, 0x00000004 },
+ { 0xa960, 0x00060000 },
+ { 0xaa3c, 0x00001c00 },
+ { 0xaa54, 0x00000004 },
+ { 0xaa60, 0x00060000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2[] = {
+ { 0xa800, 0x10000000 },
+ { 0xa804, 0x00033800 },
+ { 0xa808, 0x00000902 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x12000400 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20800 },
+ { 0xa81c, 0x00000002 },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00010032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x0000151d },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0x20001b00 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000000 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x00000008 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003500 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000500 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000200 },
+ { 0xa928, 0x07000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x050f020d },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_17w[] = {
+ { 0xa800, 0x20000000 },
+ { 0xa804, 0x000e3800 },
+ { 0xa808, 0x00000806 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x0c000800 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20d00 },
+ { 0xa81c, 0x000000ff },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00020032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x000016ff },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0xff000000 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000002 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x0000000f },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003800 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000800 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000300 },
+ { 0xa928, 0x01000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x15150406 },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_35w[] = {
+ { 0xa800, 0x00000000 },
+ { 0xa804, 0x00030400 },
+ { 0xa808, 0x00000806 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x0c000300 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20d00 },
+ { 0xa81c, 0x000000ff },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00020032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x000016ff },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0xff000000 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000001 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x00000008 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003800 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000800 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000300 },
+ { 0xa928, 0x01000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x15150406 },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+/*
+ * Some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ */
+
+u32 map_oprom_vendev(u32 vendev)
+{
+ u32 new_vendev = vendev;
+
+ switch (vendev) {
+ case 0x80860102: /* GT1 Desktop */
+ case 0x8086010a: /* GT1 Server */
+ case 0x80860112: /* GT2 Desktop */
+ case 0x80860116: /* GT2 Mobile */
+ case 0x80860122: /* GT2 Desktop >=1.3GHz */
+ case 0x80860126: /* GT2 Mobile >=1.3GHz */
+ case 0x80860156: /* IVB */
+ case 0x80860166: /* IVB */
+ /* Set to GT1 Mobile */
+ new_vendev = 0x80860106;
+ break;
+ }
+
+ return new_vendev;
+}
+
+static inline u32 gtt_read(void *bar, u32 reg)
+{
+ return readl(bar + reg);
+}
+
+static inline void gtt_write(void *bar, u32 reg, u32 data)
+{
+ writel(data, bar + reg);
+}
+
+static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
+{
+ for (; pm && pm->reg; pm++)
+ gtt_write(bar, pm->reg, pm->value);
+}
+
+#define GTT_RETRY 1000
+static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
+{
+ unsigned try = GTT_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = gtt_read(bar, reg);
+ if ((data & mask) == value)
+ return 1;
+ udelay(10);
+ }
+
+ printf("GT init timeout\n");
+ return 0;
+}
+
+static int gma_pm_init_pre_vbios(void *gtt_bar)
+{
+ u32 reg32;
+
+ debug("GT Power Management Init, silicon = %#x\n",
+ bridge_silicon_revision());
+
+ if (bridge_silicon_revision() < IVB_STEP_C0) {
+ /* 1: Enable force wake */
+ gtt_write(gtt_bar, 0xa18c, 0x00000001);
+ gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
+ } else {
+ gtt_write(gtt_bar, 0xa180, 1 << 5);
+ gtt_write(gtt_bar, 0xa188, 0xffff0001);
+ gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
+ }
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
+ reg32 = gtt_read(gtt_bar, 0x42004);
+ reg32 |= (1 << 14) | (1 << 15);
+ gtt_write(gtt_bar, 0x42004, reg32);
+ }
+
+ if (bridge_silicon_revision() >= IVB_STEP_A0) {
+ /* Display Reset Acknowledge Settings */
+ reg32 = gtt_read(gtt_bar, 0x45010);
+ reg32 |= (1 << 1) | (1 << 0);
+ gtt_write(gtt_bar, 0x45010, reg32);
+ }
+
+ /* 2: Get GT SKU from GTT+0x911c[13] */
+ reg32 = gtt_read(gtt_bar, 0x911c);
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (reg32 & (1 << 13)) {
+ debug("SNB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, snb_pm_gt1);
+ } else {
+ debug("SNB GT2 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, snb_pm_gt2);
+ }
+ } else {
+ u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
+
+ if (reg32 & (1 << 13)) {
+ /* GT1 SKU */
+ debug("IVB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
+ } else {
+ /* GT2 SKU */
+ u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
+ tdp /= (1 << unit);
+
+ if (tdp <= 17) {
+ /* <=17W ULV */
+ debug("IVB GT2 17W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
+ } else if ((tdp >= 25) && (tdp <= 35)) {
+ /* 25W-35W */
+ debug("IVB GT2 25W-35W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
+ } else {
+ /* All others */
+ debug("IVB GT2 35W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
+ }
+ }
+ }
+
+ /* 3: Gear ratio map */
+ gtt_write(gtt_bar, 0xa004, 0x00000010);
+
+ /* 4: GFXPAUSE */
+ gtt_write(gtt_bar, 0xa000, 0x00070020);
+
+ /* 5: Dynamic EU trip control */
+ gtt_write(gtt_bar, 0xa080, 0x00000004);
+
+ /* 6: ECO bits */
+ reg32 = gtt_read(gtt_bar, 0xa180);
+ reg32 |= (1 << 26) | (1 << 31);
+ /* (bit 20=1 for SNB step D1+ / IVB A0+) */
+ if (bridge_silicon_revision() >= SNB_STEP_D1)
+ reg32 |= (1 << 20);
+ gtt_write(gtt_bar, 0xa180, reg32);
+
+ /* 6a: for SnB step D2+ only */
+ if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
+ (bridge_silicon_revision() >= SNB_STEP_D2)) {
+ reg32 = gtt_read(gtt_bar, 0x9400);
+ reg32 |= (1 << 7);
+ gtt_write(gtt_bar, 0x9400, reg32);
+
+ reg32 = gtt_read(gtt_bar, 0x941c);
+ reg32 &= 0xf;
+ reg32 |= (1 << 1);
+ gtt_write(gtt_bar, 0x941c, reg32);
+ gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
+ }
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ reg32 = gtt_read(gtt_bar, 0x907c);
+ reg32 |= (1 << 16);
+ gtt_write(gtt_bar, 0x907c, reg32);
+
+ /* 6b: Clocking reset controls */
+ gtt_write(gtt_bar, 0x9424, 0x00000001);
+ } else {
+ /* 6b: Clocking reset controls */
+ gtt_write(gtt_bar, 0x9424, 0x00000000);
+ }
+
+ /* 7 */
+ if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
+ gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
+ /* Mailbox Cmd for RC6 VID */
+ gtt_write(gtt_bar, 0x138124, 0x80000004);
+ if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
+ gtt_write(gtt_bar, 0x138124, 0x8000000a);
+ gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
+ }
+
+ /* 8 */
+ gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
+ gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
+ gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
+
+ /* 9 */
+ gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
+ gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
+ gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
+
+ /* 10 */
+ gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
+ gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
+ gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
+ gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
+ gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
+
+ /* 11 */
+ gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
+ gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
+ gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
+ gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
+ gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
+ gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
+ gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
+
+ /* 11a: Enable Render Standby (RC6) */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ /*
+ * IvyBridge should also support DeepRenderStandby.
+ *
+ * Unfortunately it does not work reliably on all SKUs so
+ * disable it here and it can be enabled by the kernel.
+ */
+ gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
+ } else {
+ gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
+ }
+
+ /* 12: Normal Frequency Request */
+ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
+ reg32 = readl(MCHBAR_REG(0x5998));
+ reg32 >>= 16;
+ reg32 &= 0xef;
+ reg32 <<= 25;
+ gtt_write(gtt_bar, 0xa008, reg32);
+
+ /* 13: RP Control */
+ gtt_write(gtt_bar, 0xa024, 0x00000592);
+
+ /* 14: Enable PM Interrupts */
+ gtt_write(gtt_bar, 0x4402c, 0x03000076);
+
+ /* Clear 0x6c024 [8:6] */
+ reg32 = gtt_read(gtt_bar, 0x6c024);
+ reg32 &= ~0x000001c0;
+ gtt_write(gtt_bar, 0x6c024, reg32);
+
+ return 0;
+}
+
+int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node)
+{
+ u32 reg32, cycle_delay;
+
+ debug("GT Power Management Init (post VBIOS)\n");
+
+ /* 15: Deassert Force Wake */
+ if (bridge_silicon_revision() < IVB_STEP_C0) {
+ gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
+ gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
+ } else {
+ gtt_write(gtt_bar, 0xa188, 0x1fffe);
+ if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
+ gtt_write(gtt_bar, 0xa188,
+ gtt_read(gtt_bar, 0xa188) | 1);
+ }
+ }
+
+ /* 16: SW RC Control */
+ gtt_write(gtt_bar, 0xa094, 0x00060000);
+
+ /* Setup Digital Port Hotplug */
+ reg32 = gtt_read(gtt_bar, 0xc4030);
+ if (!reg32) {
+ u32 dp_hotplug[3];
+
+ if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
+ dp_hotplug, ARRAY_SIZE(dp_hotplug)))
+ return -EINVAL;
+
+ reg32 = (dp_hotplug[0] & 0x7) << 2;
+ reg32 |= (dp_hotplug[0] & 0x7) << 10;
+ reg32 |= (dp_hotplug[0] & 0x7) << 18;
+ gtt_write(gtt_bar, 0xc4030, reg32);
+ }
+
+ /* Setup Panel Power On Delays */
+ reg32 = gtt_read(gtt_bar, 0xc7208);
+ if (!reg32) {
+ reg32 = (unsigned)fdtdec_get_int(blob, node,
+ "panel-port-select", 0) << 30;
+ reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
+ << 16;
+ reg32 |= fdtdec_get_int(blob, node,
+ "panel-power-backlight-on-delay", 0);
+ gtt_write(gtt_bar, 0xc7208, reg32);
+ }
+
+ /* Setup Panel Power Off Delays */
+ reg32 = gtt_read(gtt_bar, 0xc720c);
+ if (!reg32) {
+ reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
+ << 16;
+ reg32 |= fdtdec_get_int(blob, node,
+ "panel-power-backlight-off-delay", 0);
+ gtt_write(gtt_bar, 0xc720c, reg32);
+ }
+
+ /* Setup Panel Power Cycle Delay */
+ cycle_delay = fdtdec_get_int(blob, node,
+ "intel,panel-power-cycle-delay", 0);
+ if (cycle_delay) {
+ reg32 = gtt_read(gtt_bar, 0xc7210);
+ reg32 &= ~0xff;
+ reg32 |= cycle_delay;
+ gtt_write(gtt_bar, 0xc7210, reg32);
+ }
+
+ /* Enable Backlight if needed */
+ reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
+ if (reg32) {
+ gtt_write(gtt_bar, 0x48250, (1 << 31));
+ gtt_write(gtt_bar, 0x48254, reg32);
+ }
+ reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
+ if (reg32) {
+ gtt_write(gtt_bar, 0xc8250, (1 << 31));
+ gtt_write(gtt_bar, 0xc8254, reg32);
+ }
+
+ return 0;
+}
+
+/*
+ * Some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ */
+
+uint32_t board_map_oprom_vendev(uint32_t vendev)
+{
+ switch (vendev) {
+ case 0x80860102: /* GT1 Desktop */
+ case 0x8086010a: /* GT1 Server */
+ case 0x80860112: /* GT2 Desktop */
+ case 0x80860116: /* GT2 Mobile */
+ case 0x80860122: /* GT2 Desktop >=1.3GHz */
+ case 0x80860126: /* GT2 Mobile >=1.3GHz */
+ case 0x80860156: /* IVB */
+ case 0x80860166: /* IVB */
+ return 0x80860106; /* GT1 Mobile */
+ }
+
+ return vendev;
+}
+
+static int int15_handler(void)
+{
+ int res = 0;
+
+ debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0x00; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0003; /* eDP */
+ res = 1;
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ debug("Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ break;
+ }
+ break;
+ case 0x5fac:
+ res = 1;
+ break;
+ default:
+ debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
+ break;
+ }
+ return res;
+}
+
+int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
+ const void *blob, int node)
+{
+ void *gtt_bar;
+ u32 reg32;
+ int ret;
+
+ /* IGD needs to be Bus Master */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
+ debug("GT bar %p\n", gtt_bar);
+ ret = gma_pm_init_pre_vbios(gtt_bar);
+ if (ret)
+ return ret;
+
+ ret = pci_run_vga_bios(dev, int15_handler, false);
+
+ /* Post VBIOS init */
+ ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
+ if (ret)
+ return ret;
+
+ return 0;
+}
--- /dev/null
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/* mailbox 0: header */
+__packed struct opregion_header {
+ u8 signature[16];
+ u32 size;
+ u32 version;
+ u8 sbios_version[32];
+ u8 vbios_version[16];
+ u8 driver_version[16];
+ u32 mailboxes;
+ u8 reserved[164];
+};
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION 2
+
+#define IGD_MBOX1 (1 << 0)
+#define IGD_MBOX2 (1 << 1)
+#define IGD_MBOX3 (1 << 2)
+#define IGD_MBOX4 (1 << 3)
+#define IGD_MBOX5 (1 << 4)
+
+#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+ IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public acpi methods */
+__packed struct opregion_mailbox1 {
+ u32 drdy;
+ u32 csts;
+ u32 cevt;
+ u8 reserved1[20];
+ u32 didl[8];
+ u32 cpdl[8];
+ u32 cadl[8];
+ u32 nadl[8];
+ u32 aslp;
+ u32 tidx;
+ u32 chpd;
+ u32 clid;
+ u32 cdck;
+ u32 sxsw;
+ u32 evts;
+ u32 cnot;
+ u32 nrdy;
+ u8 reserved2[60];
+};
+
+/* mailbox 2: software sci interface */
+__packed struct opregion_mailbox2 {
+ u32 scic;
+ u32 parm;
+ u32 dslp;
+ u8 reserved[244];
+};
+
+/* mailbox 3: power conservation */
+__packed struct opregion_mailbox3 {
+ u32 ardy;
+ u32 aslc;
+ u32 tche;
+ u32 alsi;
+ u32 bclp;
+ u32 pfit;
+ u32 cblv;
+ u16 bclm[20];
+ u32 cpfm;
+ u32 epfm;
+ u8 plut[74];
+ u32 pfmb;
+ u32 ccdv;
+ u32 pcft;
+ u8 reserved[94];
+};
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID (1 << 31)
+#define IGD_WORD_FIELD_VALID (1 << 15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+__packed struct {
+ u8 gvd1[7168];
+} opregion_vbt_t;
+
+/* IGD OpRegion */
+__packed struct igd_opregion {
+ opregion_header_t header;
+ opregion_mailbox1_t mailbox1;
+ opregion_mailbox2_t mailbox2;
+ opregion_mailbox3_t mailbox3;
+ opregion_vbt_t vbt;
+};
+
+/* Intel Video BIOS (Option ROM) */
+__packed struct optionrom_header {
+ u16 signature;
+ u8 size;
+ u8 reserved[21];
+ u16 pcir_offset;
+ u16 vbt_offset;
+};
+
+#define OPROM_SIGNATURE 0xaa55
+
+__packed struct optionrom_pcir {
+ u32 signature;
+ u16 vendor;
+ u16 device;
+ u16 reserved1;
+ u16 length;
+ u8 revision;
+ u8 classcode[3];
+ u16 imagelength;
+ u16 coderevision;
+ u8 codetype;
+ u8 indicator;
+ u16 reserved2;
+};
+
+__packed struct optionrom_vbt {
+ u8 hdr_signature[20];
+ u16 hdr_version;
+ u16 hdr_size;
+ u16 hdr_vbt_size;
+ u8 hdr_vbt_checksum;
+ u8 hdr_reserved;
+ u32 hdr_vbt_datablock;
+ u32 hdr_aim[4];
+ u8 datahdr_signature[16];
+ u16 datahdr_version;
+ u16 datahdr_size;
+ u16 datahdr_datablocksize;
+ u8 coreblock_id;
+ u16 coreblock_size;
+ u16 coreblock_biossize;
+ u8 coreblock_biostype;
+ u8 coreblock_releasestatus;
+ u8 coreblock_hwsupported;
+ u8 coreblock_integratedhw;
+ u8 coreblock_biosbuild[4];
+ u8 coreblock_biossignon[155];
+};
+
+#define VBT_SIGNATURE 0x54425624
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
+#include <rtc.h>
#include <pci.h>
+#include <asm/acpi.h>
+#include <asm/interrupt.h>
+#include <asm/io.h>
+#include <asm/ioapic.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
+#define NMI_OFF 0
+
+#define ENABLE_ACPI_MODE_IN_COREBOOT 0
+#define TEST_SMM_FLASH_LOCKDOWN 0
+
+static int pch_enable_apic(pci_dev_t dev)
+{
+ u32 reg32;
+ int i;
+
+ /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
+ pci_write_config8(dev, ACPI_CNTL, 0x80);
+
+ writel(0, IO_APIC_INDEX);
+ writel(1 << 25, IO_APIC_DATA);
+
+ /* affirm full set of redirection table entries ("write once") */
+ writel(1, IO_APIC_INDEX);
+ reg32 = readl(IO_APIC_DATA);
+ writel(1, IO_APIC_INDEX);
+ writel(reg32, IO_APIC_DATA);
+
+ writel(0, IO_APIC_INDEX);
+ reg32 = readl(IO_APIC_DATA);
+ debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+ if (reg32 != (1 << 25)) {
+ printf("APIC Error - cannot write to registers\n");
+ return -EPERM;
+ }
+
+ debug("Dumping IOAPIC registers\n");
+ for (i = 0; i < 3; i++) {
+ writel(i, IO_APIC_INDEX);
+ debug(" reg 0x%04x:", i);
+ reg32 = readl(IO_APIC_DATA);
+ debug(" 0x%08x\n", reg32);
+ }
+
+ /* Select Boot Configuration register. */
+ writel(3, IO_APIC_INDEX);
+
+ /* Use Processor System Bus to deliver interrupts. */
+ writel(1, IO_APIC_DATA);
+
+ return 0;
+}
+
+static void pch_enable_serial_irqs(pci_dev_t dev)
+{
+ u32 value;
+
+ /* Set packet length and toggle silent mode bit for one frame. */
+ value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
+#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
+ pci_write_config8(dev, SERIRQ_CNTL, value);
+#else
+ pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
+#endif
+}
+
+static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
+{
+ uint8_t route[8], *ptr;
+
+ if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
+ sizeof(route)))
+ return -EINVAL;
+ ptr = route;
+ pci_write_config8(dev, PIRQA_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQB_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQC_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQD_ROUT, *ptr++);
+
+ pci_write_config8(dev, PIRQE_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQF_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQG_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQH_ROUT, *ptr++);
+
+ /*
+ * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
+ * here. It's unclear if it is needed
+ */
+ return 0;
+}
+
+static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
+{
+ u8 route[16];
+ u32 reg;
+ int gpi;
+
+ if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
+ sizeof(route)))
+ return -EINVAL;
+
+ for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
+ reg |= route[gpi] << (gpi * 2);
+
+ pci_write_config32(dev, 0xb8, reg);
+
+ return 0;
+}
+
+static int pch_power_options(const void *blob, int node, pci_dev_t dev)
+{
+ u8 reg8;
+ u16 reg16, pmbase;
+ u32 reg32;
+ const char *state;
+ int pwr_on;
+ int nmi_option;
+ int ret;
+
+ /*
+ * Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use Kconfig setting.
+ * TODO(sjg@chromium.org): Make this configurable
+ */
+ pwr_on = MAINBOARD_POWER_ON;
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_3);
+ reg16 &= 0xfffe;
+ switch (pwr_on) {
+ case MAINBOARD_POWER_OFF:
+ reg16 |= 1;
+ state = "off";
+ break;
+ case MAINBOARD_POWER_ON:
+ reg16 &= ~1;
+ state = "on";
+ break;
+ case MAINBOARD_POWER_KEEP:
+ reg16 &= ~1;
+ state = "state keep";
+ break;
+ default:
+ state = "undefined";
+ }
+
+ reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
+ reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
+
+ reg16 &= ~(1 << 10);
+ reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
+
+ reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
+
+ pci_write_config16(dev, GEN_PMCON_3, reg16);
+ debug("Set power %s after power failure.\n", state);
+
+ /* Set up NMI on errors. */
+ reg8 = inb(0x61);
+ reg8 &= 0x0f; /* Higher Nibble must be 0 */
+ reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
+ reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+ outb(reg8, 0x61);
+
+ reg8 = inb(0x70);
+ /* TODO(sjg@chromium.org): Make this configurable */
+ nmi_option = NMI_OFF;
+ if (nmi_option) {
+ debug("NMI sources enabled.\n");
+ reg8 &= ~(1 << 7); /* Set NMI. */
+ } else {
+ debug("NMI sources disabled.\n");
+ /* Can't mask NMI from PCI-E and NMI_NOW */
+ reg8 |= (1 << 7);
+ }
+ outb(reg8, 0x70);
+
+ /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
+ reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
+#if DEBUG_PERIODIC_SMIS
+ /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
+ reg16 |= (3 << 0); /* Periodic SMI every 8s */
+#endif
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ /* Set the board's GPI routing. */
+ ret = pch_gpi_routing(blob, node, dev);
+ if (ret)
+ return ret;
+
+ pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+ writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
+ "intel,gpe0-enable", 0));
+ writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
+ "intel,alt-gp-smi-enable", 0));
+
+ /* Set up power management block and determine sleep mode */
+ reg32 = inl(pmbase + 0x04); /* PM1_CNT */
+ reg32 &= ~(7 << 10); /* SLP_TYP */
+ reg32 |= (1 << 0); /* SCI_EN */
+ outl(reg32, pmbase + 0x04);
+
+ /* Clear magic status bits to prevent unexpected wake */
+ setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
+ clrbits_le32(RCB_REG(0x3f02), 0xf);
+
+ return 0;
+}
+
+static void pch_rtc_init(pci_dev_t dev)
+{
+ int rtc_failed;
+ u8 reg8;
+
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ rtc_failed = reg8 & RTC_BATTERY_DEAD;
+ if (rtc_failed) {
+ reg8 &= ~RTC_BATTERY_DEAD;
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ }
+ debug("rtc_failed = 0x%x\n", rtc_failed);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Avoid clearing pending interrupts and resetting the RTC control
+ * register in the resume path because the Linux kernel relies on
+ * this to know if it should restart the RTC timerqueue if the wake
+ * was due to the RTC alarm.
+ */
+ if (acpi_get_slp_type() == 3)
+ return;
+#endif
+ /* TODO: Handle power failure */
+ if (rtc_failed)
+ printf("RTC power failed\n");
+ rtc_init();
+}
+
+/* CougarPoint PCH Power Management init */
+static void cpt_pm_init(pci_dev_t dev)
+{
+ debug("CougarPoint PM init\n");
+ pci_write_config8(dev, 0xa9, 0x47);
+ setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
+
+ setbits_le32(RCB_REG(0x228c), 1 << 0);
+ setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
+ setbits_le32(RCB_REG(0x0900), 1 << 14);
+ writel(0xc0388400, RCB_REG(0x2304));
+ setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
+ setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
+ clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
+ writel(0x050f0000, RCB_REG(0x3318));
+ writel(0x04000000, RCB_REG(0x3324));
+ setbits_le32(RCB_REG(0x3340), 0xfffff);
+ setbits_le32(RCB_REG(0x3344), 1 << 1);
+
+ writel(0x0001c000, RCB_REG(0x3360));
+ writel(0x00061100, RCB_REG(0x3368));
+ writel(0x7f8fdfff, RCB_REG(0x3378));
+ writel(0x000003fc, RCB_REG(0x337c));
+ writel(0x00001000, RCB_REG(0x3388));
+ writel(0x0001c000, RCB_REG(0x3390));
+ writel(0x00000800, RCB_REG(0x33a0));
+ writel(0x00001000, RCB_REG(0x33b0));
+ writel(0x00093900, RCB_REG(0x33c0));
+ writel(0x24653002, RCB_REG(0x33cc));
+ writel(0x062108fe, RCB_REG(0x33d0));
+ clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
+ writel(0x01010000, RCB_REG(0x3a28));
+ writel(0x01010404, RCB_REG(0x3a2c));
+ writel(0x01041041, RCB_REG(0x3a80));
+ clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
+ setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
+ setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
+ writel(0x00000001, RCB_REG(0x3a6c));
+ clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
+ clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
+ writel(0, RCB_REG(0x33c8));
+ setbits_le32(RCB_REG(0x21b0), 0xf);
+}
+
+/* PantherPoint PCH Power Management init */
+static void ppt_pm_init(pci_dev_t dev)
+{
+ debug("PantherPoint PM init\n");
+ pci_write_config8(dev, 0xa9, 0x47);
+ setbits_le32(RCB_REG(0x2238), 1 << 0);
+ setbits_le32(RCB_REG(0x228c), 1 << 0);
+ setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
+ setbits_le16(RCB_REG(0x0900), 1 << 14);
+ writel(0xc03b8400, RCB_REG(0x2304));
+ setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
+ setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
+ clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
+ writel(0x054f0000, RCB_REG(0x3318));
+ writel(0x04000000, RCB_REG(0x3324));
+ setbits_le32(RCB_REG(0x3340), 0xfffff);
+ setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
+ writel(0x0001c000, RCB_REG(0x3360));
+ writel(0x00061100, RCB_REG(0x3368));
+ writel(0x7f8fdfff, RCB_REG(0x3378));
+ writel(0x000003fd, RCB_REG(0x337c));
+ writel(0x00001000, RCB_REG(0x3388));
+ writel(0x0001c000, RCB_REG(0x3390));
+ writel(0x00000800, RCB_REG(0x33a0));
+ writel(0x00001000, RCB_REG(0x33b0));
+ writel(0x00093900, RCB_REG(0x33c0));
+ writel(0x24653002, RCB_REG(0x33cc));
+ writel(0x067388fe, RCB_REG(0x33d0));
+ clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
+ writel(0x01010000, RCB_REG(0x3a28));
+ writel(0x01010404, RCB_REG(0x3a2c));
+ writel(0x01040000, RCB_REG(0x3a80));
+ clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
+ /* SATA 2/3 disabled */
+ setbits_le32(RCB_REG(0x3a84), 1 << 24);
+ /* SATA 4/5 disabled */
+ setbits_le32(RCB_REG(0x3a88), 1 << 0);
+ writel(0x00000001, RCB_REG(0x3a6c));
+ clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
+ clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
+ setbits_le32(RCB_REG(0x33a4), (1 << 0));
+ writel(0, RCB_REG(0x33c8));
+ setbits_le32(RCB_REG(0x21b0), 0xf);
+}
+
+static void enable_hpet(void)
+{
+ /* Move HPET to default address 0xfed00000 and enable it */
+ clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
+}
+
+static void enable_clock_gating(pci_dev_t dev)
+{
+ u32 reg32;
+ u16 reg16;
+
+ setbits_le32(RCB_REG(0x2234), 0xf);
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 |= (1 << 2) | (1 << 11);
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
+ pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
+ pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
+ pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+
+ reg32 = readl(RCB_REG(CG));
+ reg32 |= (1 << 31);
+ reg32 |= (1 << 29) | (1 << 28);
+ reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
+ reg32 |= (1 << 16);
+ reg32 |= (1 << 17);
+ reg32 |= (1 << 18);
+ reg32 |= (1 << 22);
+ reg32 |= (1 << 23);
+ reg32 &= ~(1 << 20);
+ reg32 |= (1 << 19);
+ reg32 |= (1 << 0);
+ reg32 |= (0xf << 1);
+ writel(reg32, RCB_REG(CG));
+
+ setbits_le32(RCB_REG(0x38c0), 0x7);
+ setbits_le32(RCB_REG(0x36d4), 0x6680c004);
+ setbits_le32(RCB_REG(0x3564), 0x3);
+}
+
+#if CONFIG_HAVE_SMI_HANDLER
+static void pch_lock_smm(pci_dev_t dev)
+{
+#if TEST_SMM_FLASH_LOCKDOWN
+ u8 reg8;
+#endif
+
+ if (acpi_slp_type != 3) {
+#if ENABLE_ACPI_MODE_IN_COREBOOT
+ debug("Enabling ACPI via APMC:\n");
+ outb(0xe1, 0xb2); /* Enable ACPI mode */
+ debug("done.\n");
+#else
+ debug("Disabling ACPI via APMC:\n");
+ outb(0x1e, 0xb2); /* Disable ACPI mode */
+ debug("done.\n");
+#endif
+ }
+
+ /* Don't allow evil boot loaders, kernels, or
+ * userspace applications to deceive us:
+ */
+ smm_lock();
+
+#if TEST_SMM_FLASH_LOCKDOWN
+ /* Now try this: */
+ debug("Locking BIOS to RO... ");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+ reg8 &= ~(1 << 0); /* clear BIOSWE */
+ pci_write_config8(dev, 0xdc, reg8);
+ reg8 |= (1 << 1); /* set BLE */
+ pci_write_config8(dev, 0xdc, reg8);
+ debug("ok.\n");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+
+ debug("Writing:\n");
+ writeb(0, 0xfff00000);
+ debug("Testing:\n");
+ reg8 |= (1 << 0); /* set BIOSWE */
+ pci_write_config8(dev, 0xdc, reg8);
+
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+ debug("Done.\n");
+#endif
+}
+#endif
+
+static void pch_disable_smm_only_flashing(pci_dev_t dev)
+{
+ u8 reg8;
+
+ debug("Enabling BIOS updates outside of SMM... ");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 &= ~(1 << 5);
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void pch_fixups(pci_dev_t dev)
+{
+ u8 gen_pmcon_2;
+
+ /* Indicate DRAM init done for MRC S3 to know it can resume */
+ gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
+ gen_pmcon_2 |= (1 << 7);
+ pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
+
+ /* Enable DMI ASPM in the PCH */
+ clrbits_le32(RCB_REG(0x2304), 1 << 10);
+ setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
+ setbits_le32(RCB_REG(0x21a8), 0x3);
+}
+
int lpc_early_init(const void *blob, int node, pci_dev_t dev)
{
struct reg_info {
int count;
int i;
- count = fdtdec_get_int_array_count(blob, node, "gen-dec",
+ count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
(u32 *)values, sizeof(values) / sizeof(u32));
if (count < 0)
return -EINVAL;
return 0;
}
+
+int lpc_init(struct pci_controller *hose, pci_dev_t dev)
+{
+ const void *blob = gd->fdt_blob;
+ int node;
+
+ debug("pch: lpc_init\n");
+ pci_write_bar32(hose, dev, 0, 0);
+ pci_write_bar32(hose, dev, 1, 0xff800000);
+ pci_write_bar32(hose, dev, 2, 0xfec00000);
+ pci_write_bar32(hose, dev, 3, 0x800);
+ pci_write_bar32(hose, dev, 4, 0x900);
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+ if (node < 0)
+ return -ENOENT;
+
+ /* Set the value for PCI command register. */
+ pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+ /* IO APIC initialization. */
+ pch_enable_apic(dev);
+
+ pch_enable_serial_irqs(dev);
+
+ /* Setup the PIRQ. */
+ pch_pirq_init(blob, node, dev);
+
+ /* Setup power options. */
+ pch_power_options(blob, node, dev);
+
+ /* Initialize power management */
+ switch (pch_silicon_type()) {
+ case PCH_TYPE_CPT: /* CougarPoint */
+ cpt_pm_init(dev);
+ break;
+ case PCH_TYPE_PPT: /* PantherPoint */
+ ppt_pm_init(dev);
+ break;
+ default:
+ printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
+ PCI_FUNC(dev));
+ return -ENOSYS;
+ }
+
+ /* Initialize the real time clock. */
+ pch_rtc_init(dev);
+
+ /* Initialize the High Precision Event Timers, if present. */
+ enable_hpet();
+
+ /* Initialize Clock Gating */
+ enable_clock_gating(dev);
+
+ pch_disable_smm_only_flashing(dev);
+
+#if CONFIG_HAVE_SMI_HANDLER
+ pch_lock_smm(dev);
+#endif
+
+ pch_fixups(dev);
+
+ return 0;
+}
+
+void lpc_enable(pci_dev_t dev)
+{
+ /* Enable PCH Display Port */
+ writew(0x0010, RCB_REG(DISPBDF));
+ setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
+}
--- /dev/null
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/acpi.h>
+#include <asm/cpu.h>
+#include <asm/lapic.h>
+#include <asm/lapic_def.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/processor.h>
+#include <asm/speedstep.h>
+#include <asm/turbo.h>
+#include <asm/arch/model_206ax.h>
+
+static void enable_vmx(void)
+{
+ struct cpuid_result regs;
+#ifdef CONFIG_ENABLE_VMX
+ int enable = true;
+#else
+ int enable = false;
+#endif
+ msr_t msr;
+
+ regs = cpuid(1);
+ /* Check that the VMX is supported before reading or writing the MSR. */
+ if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
+ return;
+
+ msr = msr_read(MSR_IA32_FEATURE_CONTROL);
+
+ if (msr.lo & (1 << 0)) {
+ debug("VMX is locked, so %s will do nothing\n", __func__);
+ /* VMX locked. If we set it again we get an illegal
+ * instruction
+ */
+ return;
+ }
+
+ /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
+ * It must be cleared regardless of VMX config setting.
+ */
+ msr.hi = 0;
+ msr.lo = 0;
+
+ debug("%s VMX\n", enable ? "Enabling" : "Disabling");
+
+ /*
+ * Even though the Intel manual says you must set the lock bit in
+ * addition to the VMX bit in order for VMX to work, it is incorrect.
+ * Thus we leave it unlocked for the OS to manage things itself.
+ * This is good for a few reasons:
+ * - No need to reflash the bios just to toggle the lock bit.
+ * - The VMX bits really really should match each other across cores,
+ * so hard locking it on one while another has the opposite setting
+ * can easily lead to crashes as code using VMX migrates between
+ * them.
+ * - Vendors that want to "upsell" from a bios that disables+locks to
+ * one that doesn't is sleazy.
+ * By leaving this to the OS (e.g. Linux), people can do exactly what
+ * they want on the fly, and do it correctly (e.g. across multiple
+ * cores).
+ */
+ if (enable) {
+ msr.lo |= (1 << 2);
+ if (regs.ecx & CPUID_SMX)
+ msr.lo |= (1 << 1);
+ }
+
+ msr_write(MSR_IA32_FEATURE_CONTROL, msr);
+}
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+ [0] = 0x00,
+ [1] = 0x0a,
+ [2] = 0x0b,
+ [3] = 0x4b,
+ [4] = 0x0c,
+ [5] = 0x2c,
+ [6] = 0x4c,
+ [7] = 0x6c,
+ [8] = 0x0d,
+ [10] = 0x2d,
+ [12] = 0x4d,
+ [14] = 0x6d,
+ [16] = 0x0e,
+ [20] = 0x2e,
+ [24] = 0x4e,
+ [28] = 0x6e,
+ [32] = 0x0f,
+ [40] = 0x2f,
+ [48] = 0x4f,
+ [56] = 0x6f,
+ [64] = 0x10,
+ [80] = 0x30,
+ [96] = 0x50,
+ [112] = 0x70,
+ [128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+ [0x00] = 0,
+ [0x0a] = 1,
+ [0x0b] = 2,
+ [0x4b] = 3,
+ [0x0c] = 4,
+ [0x2c] = 5,
+ [0x4c] = 6,
+ [0x6c] = 7,
+ [0x0d] = 8,
+ [0x2d] = 10,
+ [0x4d] = 12,
+ [0x6d] = 14,
+ [0x0e] = 16,
+ [0x2e] = 20,
+ [0x4e] = 24,
+ [0x6e] = 28,
+ [0x0f] = 32,
+ [0x2f] = 40,
+ [0x4f] = 48,
+ [0x6f] = 56,
+ [0x10] = 64,
+ [0x30] = 80,
+ [0x50] = 96,
+ [0x70] = 112,
+ [0x11] = 128,
+};
+
+int cpu_config_tdp_levels(void)
+{
+ struct cpuid_result result;
+ msr_t platform_info;
+
+ /* Minimum CPU revision */
+ result = cpuid(1);
+ if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
+ return 0;
+
+ /* Bits 34:33 indicate how many levels supported */
+ platform_info = msr_read(MSR_PLATFORM_INFO);
+ return (platform_info.hi >> 1) & 3;
+}
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void set_power_limits(u8 power_limit_1_time)
+{
+ msr_t msr = msr_read(MSR_PLATFORM_INFO);
+ msr_t limit;
+ unsigned power_unit;
+ unsigned tdp, min_power, max_power, max_time;
+ u8 power_limit_1_val;
+
+ if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+ return;
+
+ if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+ return;
+
+ /* Get units */
+ msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+ power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+ /* Get power defaults for this SKU */
+ msr = msr_read(MSR_PKG_POWER_SKU);
+ tdp = msr.lo & 0x7fff;
+ min_power = (msr.lo >> 16) & 0x7fff;
+ max_power = msr.hi & 0x7fff;
+ max_time = (msr.hi >> 16) & 0x7f;
+
+ debug("CPU TDP: %u Watts\n", tdp / power_unit);
+
+ if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+ power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+ if (min_power > 0 && tdp < min_power)
+ tdp = min_power;
+
+ if (max_power > 0 && tdp > max_power)
+ tdp = max_power;
+
+ power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+ /* Set long term power limit to TDP */
+ limit.lo = 0;
+ limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+ limit.lo |= PKG_POWER_LIMIT_EN;
+ limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+ PKG_POWER_LIMIT_TIME_SHIFT;
+
+ /* Set short term power limit to 1.25 * TDP */
+ limit.hi = 0;
+ limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+ limit.hi |= PKG_POWER_LIMIT_EN;
+ /* Power limit 2 time is only programmable on SNB EP/EX */
+
+ msr_write(MSR_PKG_POWER_LIMIT, limit);
+
+ /* Use nominal TDP values for CPUs with configurable TDP */
+ if (cpu_config_tdp_levels()) {
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ limit.hi = 0;
+ limit.lo = msr.lo & 0xff;
+ msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
+ }
+}
+
+static void configure_c_states(void)
+{
+ struct cpuid_result result;
+ msr_t msr;
+
+ msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
+ msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
+ msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
+ msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
+ msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
+ msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
+ msr.lo |= 7; /* No package C-state limit */
+ msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
+
+ msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
+ msr.lo &= ~0x7ffff;
+ msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
+ msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
+ msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
+
+ msr = msr_read(MSR_MISC_PWR_MGMT);
+ msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
+ msr_write(MSR_MISC_PWR_MGMT, msr);
+
+ msr = msr_read(MSR_POWER_CTL);
+ msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
+ msr.lo |= (1 << 1); /* C1E Enable */
+ msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
+ msr_write(MSR_POWER_CTL, msr);
+
+ /* C3 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+ msr_write(MSR_PKGC3_IRTL, msr);
+
+ /* C6 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+ msr_write(MSR_PKGC6_IRTL, msr);
+
+ /* C7 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+ msr_write(MSR_PKGC7_IRTL, msr);
+
+ /* Primary Plane Current Limit */
+ msr = msr_read(MSR_PP0_CURRENT_CONFIG);
+ msr.lo &= ~0x1fff;
+ msr.lo |= PP0_CURRENT_LIMIT;
+ msr_write(MSR_PP0_CURRENT_CONFIG, msr);
+
+ /* Secondary Plane Current Limit */
+ msr = msr_read(MSR_PP1_CURRENT_CONFIG);
+ msr.lo &= ~0x1fff;
+ result = cpuid(1);
+ if (result.eax >= 0x30600)
+ msr.lo |= PP1_CURRENT_LIMIT_IVB;
+ else
+ msr.lo |= PP1_CURRENT_LIMIT_SNB;
+ msr_write(MSR_PP1_CURRENT_CONFIG, msr);
+}
+
+static int configure_thermal_target(void)
+{
+ int tcc_offset;
+ msr_t msr;
+ int node;
+
+ /* Find pointer to CPU configuration */
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_INTEL_MODEL_206AX);
+ if (node < 0)
+ return -ENOENT;
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0);
+
+ /* Set TCC activaiton offset if supported */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ if ((msr.lo & (1 << 30)) && tcc_offset) {
+ msr = msr_read(MSR_TEMPERATURE_TARGET);
+ msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+ msr.lo |= (tcc_offset & 0xf) << 24;
+ msr_write(MSR_TEMPERATURE_TARGET, msr);
+ }
+
+ return 0;
+}
+
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ msr = msr_read(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr_write(IA32_MISC_ENABLE, msr);
+
+ /* Disable Thermal interrupts */
+ msr.lo = 0;
+ msr.hi = 0;
+ msr_write(IA32_THERM_INTERRUPT, msr);
+
+ /* Enable package critical interrupt only */
+ msr.lo = 1 << 4;
+ msr.hi = 0;
+ msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_PIC_MSG_CONTROL);
+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
+ msr_write(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+ struct cpuid_result cpuid_regs;
+ msr_t msr;
+
+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+ cpuid_regs = cpuid(1);
+ if (cpuid_regs.ecx & (1 << 18)) {
+ msr = msr_read(IA32_PLATFORM_DCA_CAP);
+ msr.lo |= 1;
+ msr_write(IA32_PLATFORM_DCA_CAP, msr);
+ }
+}
+
+static void set_max_ratio(void)
+{
+ msr_t msr, perf_ctl;
+
+ perf_ctl.hi = 0;
+
+ /* Check for configurable TDP option */
+ if (cpu_config_tdp_levels()) {
+ /* Set to nominal TDP ratio */
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else {
+ /* Platform Info bits 15:8 give max ratio */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ perf_ctl.lo = msr.lo & 0xff00;
+ }
+ msr_write(IA32_PERF_CTL, perf_ctl);
+
+ debug("model_x06ax: frequency set to %d\n",
+ ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+ msr_t msr;
+
+ /* Energy Policy is bits 3:0 */
+ msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
+ msr.lo &= ~0xf;
+ msr.lo |= policy & 0xf;
+ msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+ debug("model_x06ax: energy policy set to %u\n", policy);
+}
+
+static void configure_mca(void)
+{
+ msr_t msr;
+ int i;
+
+ msr.lo = 0;
+ msr.hi = 0;
+ /* This should only be done on a cold boot */
+ for (i = 0; i < 7; i++)
+ msr_write(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static int intel_cores_init(struct x86_cpu_priv *cpu)
+{
+ struct cpuid_result result;
+ unsigned threads_per_package, threads_per_core, i;
+
+ /* Logical processors (threads) per core */
+ result = cpuid_ext(0xb, 0);
+ threads_per_core = result.ebx & 0xffff;
+
+ /* Logical processors (threads) per package */
+ result = cpuid_ext(0xb, 1);
+ threads_per_package = result.ebx & 0xffff;
+
+ debug("CPU: %u has %u cores, %u threads per core\n",
+ cpu->apic_id, threads_per_package / threads_per_core,
+ threads_per_core);
+
+ for (i = 1; i < threads_per_package; ++i) {
+ struct x86_cpu_priv *new_cpu;
+
+ new_cpu = calloc(1, sizeof(*new_cpu));
+ if (!new_cpu)
+ return -ENOMEM;
+
+ new_cpu->apic_id = cpu->apic_id + i;
+
+ /* Update APIC ID if no hyperthreading */
+ if (threads_per_core == 1)
+ new_cpu->apic_id <<= 1;
+
+ debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id);
+
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+ /* Start the new cpu */
+ if (!start_cpu(new_cpu)) {
+ /* Record the error in cpu? */
+ printk(BIOS_ERR, "CPU %u would not start!\n",
+ new_cpu->apic_id);
+ new_cpu->start_err = 1;
+ }
+#endif
+ }
+
+ return 0;
+}
+
+int model_206ax_init(struct x86_cpu_priv *cpu)
+{
+ int ret;
+
+ /* Clear out pending MCEs */
+ configure_mca();
+
+#if CONFIG_USBDEBUG
+ /* Is this caution really needed? */
+ if (!ehci_debug_addr)
+ ehci_debug_addr = get_ehci_debug();
+ set_ehci_debug(0);
+#endif
+
+ /* Setup MTRRs based on physical address size */
+#if 0 /* TODO: Implement this */
+ struct cpuid_result cpuid_regs;
+
+ cpuid_regs = cpuid(0x80000008);
+ x86_setup_fixed_mtrrs();
+ x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
+ x86_mtrr_check();
+#endif
+
+#if CONFIG_USBDEBUG
+ set_ehci_debug(ehci_debug_addr);
+#endif
+
+ /* Enable the local cpu apics */
+ enable_lapic_tpr();
+ lapic_setup();
+
+ /* Enable virtualization if enabled in CMOS */
+ enable_vmx();
+
+ /* Configure C States */
+ configure_c_states();
+
+ /* Configure Enhanced SpeedStep and Thermal Sensors */
+ configure_misc();
+
+ /* Thermal throttle activation offset */
+ ret = configure_thermal_target();
+ if (ret)
+ return ret;
+
+ /* Enable Direct Cache Access */
+ configure_dca_cap();
+
+ /* Set energy policy */
+ set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+ /* Set Max Ratio */
+ set_max_ratio();
+
+ /* Enable Turbo */
+ turbo_enable();
+
+ /* Start up extra cores */
+ intel_cores_init(cpu);
+
+ return 0;
+}
--- /dev/null
+/*
+ * From Coreboot northbridge/intel/sandybridge/northbridge.c
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/msr.h>
+#include <asm/acpi.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/model_206ax.h>
+#include <asm/arch/sandybridge.h>
+
+static int bridge_revision_id = -1;
+
+int bridge_silicon_revision(void)
+{
+ if (bridge_revision_id < 0) {
+ struct cpuid_result result;
+ uint8_t stepping, bridge_id;
+ pci_dev_t dev;
+
+ result = cpuid(1);
+ stepping = result.eax & 0xf;
+ dev = PCI_BDF(0, 0, 0);
+ bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
+ bridge_revision_id = bridge_id | stepping;
+ }
+
+ return bridge_revision_id;
+}
+
+/*
+ * Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
+ */
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_size_k = 384;
+
+static int get_pcie_bar(u32 *base, u32 *len)
+{
+ pci_dev_t dev = PCI_BDF(0, 0, 0);
+ u32 pciexbar_reg;
+
+ *base = 0;
+ *len = 0;
+
+ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+ if (!(pciexbar_reg & (1 << 0)))
+ return 0;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: /* 256MB */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28));
+ *len = 256 * 1024 * 1024;
+ return 1;
+ case 1: /* 128M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27));
+ *len = 128 * 1024 * 1024;
+ return 1;
+ case 2: /* 64M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27) | (1 << 26));
+ *len = 64 * 1024 * 1024;
+ return 1;
+ }
+
+ return 0;
+}
+
+static void add_fixed_resources(pci_dev_t dev, int index)
+{
+ u32 pcie_config_base, pcie_config_size;
+
+ if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+ debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
+ pcie_config_base, pcie_config_size);
+ }
+}
+
+static void northbridge_dmi_init(pci_dev_t dev)
+{
+ /* Clear error status bits */
+ writel(0xffffffff, DMIBAR_REG(0x1c4));
+ writel(0xffffffff, DMIBAR_REG(0x1d0));
+
+ /* Steps prior to DMI ASPM */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
+ 1 << 21);
+ }
+
+ setbits_le32(DMIBAR_REG(0x238), 1 << 29);
+
+ if (bridge_silicon_revision() >= SNB_STEP_D0) {
+ setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
+ } else if (bridge_silicon_revision() >= SNB_STEP_D1) {
+ clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
+ setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
+ }
+
+ /* Enable ASPM on SNB link, should happen before PCH link */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB)
+ setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
+
+ setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
+}
+
+void northbridge_init(pci_dev_t dev)
+{
+ u32 bridge_type;
+
+ add_fixed_resources(dev, 6);
+ northbridge_dmi_init(dev);
+
+ bridge_type = readl(MCHBAR_REG(0x5f10));
+ bridge_type &= ~0xff;
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ /* Enable Power Aware Interrupt Routing - fixed priority */
+ clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
+
+ /* 30h for IvyBridge */
+ bridge_type |= 0x30;
+ } else {
+ /* 20h for Sandybridge */
+ bridge_type |= 0x20;
+ }
+ writel(bridge_type, MCHBAR_REG(0x5f10));
+
+ /*
+ * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
+ * that BIOS has initialized memory and power management
+ */
+ setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1);
+ debug("Set BIOS_RESET_CPL\n");
+
+ /* Configure turbo power limits 1ms after reset complete bit */
+ mdelay(1);
+ set_power_limits(28);
+
+ /*
+ * CPUs with configurable TDP also need power limits set
+ * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
+ */
+ if (cpu_config_tdp_levels()) {
+ msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
+
+ writel(msr.lo, MCHBAR_REG(0x59A0));
+ writel(msr.hi, MCHBAR_REG(0x59A4));
+ }
+
+ /* Set here before graphics PM init */
+ writel(0x00100001, MCHBAR_REG(0x5500));
+}
+
+void northbridge_enable(pci_dev_t dev)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+ switch (pci_read_config32(dev, SKPAD)) {
+ case 0xcafebabe:
+ debug("Normal boot.\n");
+ apci_set_slp_type(0);
+ break;
+ case 0xcafed00d:
+ debug("S3 Resume.\n");
+ apci_set_slp_type(3);
+ break;
+ default:
+ debug("Unknown boot method, assuming normal.\n");
+ apci_set_slp_type(0);
+ break;
+ }
+#endif
+}
--- /dev/null
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+static int pch_revision_id = -1;
+static int pch_type = -1;
+
+int pch_silicon_revision(void)
+{
+ pci_dev_t dev;
+
+ dev = PCH_LPC_DEV;
+
+ if (pch_revision_id < 0)
+ pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
+ return pch_revision_id;
+}
+
+int pch_silicon_type(void)
+{
+ pci_dev_t dev;
+
+ dev = PCH_LPC_DEV;
+
+ if (pch_type < 0)
+ pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
+ return pch_type;
+}
+
+int pch_silicon_supported(int type, int rev)
+{
+ int cur_type = pch_silicon_type();
+ int cur_rev = pch_silicon_revision();
+
+ switch (type) {
+ case PCH_TYPE_CPT:
+ /* CougarPoint minimum revision */
+ if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
+ return 1;
+ /* PantherPoint any revision */
+ if (cur_type == PCH_TYPE_PPT)
+ return 1;
+ break;
+
+ case PCH_TYPE_PPT:
+ /* PantherPoint minimum revision */
+ if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
+ return 1;
+ break;
+ }
+
+ return 0;
+}
+
+#define IOBP_RETRY 1000
+static inline int iobp_poll(void)
+{
+ unsigned try = IOBP_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = readl(RCB_REG(IOBPS));
+ if ((data & 1) == 0)
+ return 1;
+ udelay(10);
+ }
+
+ printf("IOBP timeout\n");
+ return 0;
+}
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+ u32 data;
+
+ /* Set the address */
+ writel(address, RCB_REG(IOBPIRI));
+
+ /* READ OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ writel(IOBPS_RW_BX, RCB_REG(IOBPS));
+ else
+ writel(IOBPS_READ_AX, RCB_REG(IOBPS));
+ if (!iobp_poll())
+ return;
+
+ /* Read IOBP data */
+ data = readl(RCB_REG(IOBPD));
+ if (!iobp_poll())
+ return;
+
+ /* Check for successful transaction */
+ if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
+ printf("IOBP read 0x%08x failed\n", address);
+ return;
+ }
+
+ /* Update the data */
+ data &= andvalue;
+ data |= orvalue;
+
+ /* WRITE OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ writel(IOBPS_RW_BX, RCB_REG(IOBPS));
+ else
+ writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
+ if (!iobp_poll())
+ return;
+
+ /* Write IOBP data */
+ writel(data, RCB_REG(IOBPD));
+ if (!iobp_poll())
+ return;
+}
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
+#include <asm/arch/bd82x6x.h>
+#include <asm/arch/pch.h>
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
hose->region_count = 3;
}
+
+int board_pci_pre_scan(struct pci_controller *hose)
+{
+ pci_dev_t dev;
+ u16 reg16;
+
+ bd82x6x_init();
+
+ reg16 = 0xff;
+ dev = PCH_DEV;
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+ pci_write_bar32(hose, dev, 0, 0xf0000000);
+
+ return 0;
+}
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+ int ret;
+
+ ret = bd82x6x_init_pci_devices();
+ if (ret) {
+ printf("bd82x6x_init_pci_devices() failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/bd82x6x.h>
+
+static inline u32 sir_read(pci_dev_t dev, int idx)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ return pci_read_config32(dev, SATA_SIRD);
+}
+
+static inline void sir_write(pci_dev_t dev, int idx, u32 value)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ pci_write_config32(dev, SATA_SIRD, value);
+}
+
+static void common_sata_init(pci_dev_t dev, unsigned int port_map)
+{
+ u32 reg32;
+ u16 reg16;
+
+ /* Set IDE I/O Configuration */
+ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ pci_write_config32(dev, IDE_CONFIG, reg32);
+
+ /* Port enable */
+ reg16 = pci_read_config16(dev, 0x92);
+ reg16 &= ~0x3f;
+ reg16 |= port_map;
+ pci_write_config16(dev, 0x92, reg16);
+
+ /* SATA Initialization register */
+ port_map &= 0xff;
+ pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
+}
+
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
+{
+ unsigned int port_map, speed_support, port_tx;
+ struct pci_controller *hose = pci_bus_to_hose(0);
+ const char *mode;
+ u32 reg32;
+ u16 reg16;
+
+ debug("SATA: Initializing...\n");
+
+ /* SATA configuration */
+ port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+ speed_support = fdtdec_get_int(blob, node,
+ "sata_interface_speed_support", 0);
+
+ /* Enable BARs */
+ pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+ mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+ if (!mode || !strcmp(mode, "ahci")) {
+ u32 abar;
+
+ debug("SATA: Controller in AHCI mode\n");
+
+ /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
+ pci_write_config8(dev, INTR_LN, 0x0a);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+
+ common_sata_init(dev, 0x8000 | port_map);
+
+ /* Initialize AHCI memory-mapped space */
+ abar = pci_read_bar32(hose, dev, 5);
+ debug("ABAR: %08X\n", abar);
+ /* CAP (HBA Capabilities) : enable power management */
+ reg32 = readl(abar + 0x00);
+ reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
+ reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
+ /* Set ISS, if available */
+ if (speed_support) {
+ reg32 &= ~0x00f00000;
+ reg32 |= (speed_support & 0x03) << 20;
+ }
+ writel(reg32, abar + 0x00);
+ /* PI (Ports implemented) */
+ writel(port_map, abar + 0x0c);
+ (void) readl(abar + 0x0c); /* Read back 1 */
+ (void) readl(abar + 0x0c); /* Read back 2 */
+ /* CAP2 (HBA Capabilities Extended)*/
+ reg32 = readl(abar + 0x24);
+ reg32 &= ~0x00000002;
+ writel(reg32, abar + 0x24);
+ /* VSP (Vendor Specific Register */
+ reg32 = readl(abar + 0xa0);
+ reg32 &= ~0x00000005;
+ writel(reg32, abar + 0xa0);
+ } else if (!strcmp(mode, "combined")) {
+ debug("SATA: Controller in combined mode\n");
+
+ /* No AHCI: clear AHCI base */
+ pci_write_bar32(hose, dev, 5, 0x00000000);
+ /* And without AHCI BAR no memory decoding */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ pci_write_config8(dev, 0x09, 0x80);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+ common_sata_init(dev, port_map);
+ } else {
+ debug("SATA: Controller in plain-ide mode\n");
+
+ /* No AHCI: clear AHCI base */
+ pci_write_bar32(hose, dev, 5, 0x00000000);
+
+ /* And without AHCI BAR no memory decoding */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /*
+ * Native mode capable on both primary and secondary (0xa)
+ * OR'ed with enabled (0x50) = 0xf
+ */
+ pci_write_config8(dev, 0x09, 0x8f);
+
+ /* Set Interrupt Line */
+ /* Interrupt Pin is set by D31IP.PIP */
+ pci_write_config8(dev, INTR_LN, 0xff);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_SITRE | IDE_ISP_3_CLOCKS |
+ IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+ common_sata_init(dev, port_map);
+ }
+
+ /* Set Gen3 Transmitter settings if needed */
+ port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
+ if (port_tx)
+ pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
+
+ port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
+ if (port_tx)
+ pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
+
+ /* Additional Programming Requirements */
+ sir_write(dev, 0x04, 0x00001600);
+ sir_write(dev, 0x28, 0xa0000033);
+ reg32 = sir_read(dev, 0x54);
+ reg32 &= 0xff000000;
+ reg32 |= 0x5555aa;
+ sir_write(dev, 0x54, reg32);
+ sir_write(dev, 0x64, 0xcccc8484);
+ reg32 = sir_read(dev, 0x68);
+ reg32 &= 0xffff0000;
+ reg32 |= 0xcccc;
+ sir_write(dev, 0x68, reg32);
+ reg32 = sir_read(dev, 0x78);
+ reg32 &= 0x0000ffff;
+ reg32 |= 0x88880000;
+ sir_write(dev, 0x78, reg32);
+ sir_write(dev, 0x84, 0x001c7000);
+ sir_write(dev, 0x88, 0x88338822);
+ sir_write(dev, 0xa0, 0x001c7000);
+ sir_write(dev, 0xc4, 0x0c0c0c0c);
+ sir_write(dev, 0xc8, 0x0c0c0c0c);
+ sir_write(dev, 0xd4, 0x10000000);
+
+ pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
+ pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
+}
+
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
+{
+ unsigned port_map;
+ const char *mode;
+ u16 map = 0;
+
+ /*
+ * Set SATA controller mode early so the resource allocator can
+ * properly assign IO/Memory resources for the controller.
+ */
+ mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+ if (mode && !strcmp(mode, "ahci"))
+ map = 0x0060;
+ port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+
+ map |= (port_map ^ 0x3f) << 8;
+ pci_write_config16(dev, 0x90, map);
+}
--- /dev/null
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_ehci_init(pci_dev_t dev)
+{
+ u32 reg32;
+
+ /* Disable Wake on Disconnect in RMH */
+ reg32 = readl(RCB_REG(0x35b0));
+ reg32 |= 0x22;
+ writel(reg32, RCB_REG(0x35b0));
+
+ debug("EHCI: Setting up controller.. ");
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER;
+ /* reg32 |= PCI_COMMAND_SERR; */
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ debug("done.\n");
+}
--- /dev/null
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_xhci_init(pci_dev_t dev)
+{
+ u32 reg32;
+
+ debug("XHCI: Setting up controller.. ");
+
+ /* lock overcurrent map */
+ reg32 = pci_read_config32(dev, 0x44);
+ reg32 |= 1;
+ pci_write_config32(dev, 0x44, reg32);
+
+ /* Enable clock gating */
+ reg32 = pci_read_config32(dev, 0x40);
+ reg32 &= ~((1 << 20) | (1 << 21));
+ reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
+ reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
+ reg32 |= (1 << 31); /* lock */
+ pci_write_config32(dev, 0x40, reg32);
+
+ debug("done.\n");
+}
--- /dev/null
+/*
+ * From coreboot file of same name
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/msr.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/post.h>
+
+void lapic_setup(void)
+{
+#if NEED_LAPIC == 1
+ /* Only Pentium Pro and later have those MSR stuff */
+ debug("Setting up local apic: ");
+
+ /* Enable the local apic */
+ enable_lapic();
+
+ /*
+ * Set Task Priority to 'accept all'.
+ */
+ lapic_write_around(LAPIC_TASKPRI,
+ lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
+
+ /* Put the local apic in virtual wire mode */
+ lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
+ ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
+ lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_EXTINT));
+ lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_NMI));
+
+ debug("apic_id: 0x%02lx, ", lapicid());
+#else /* !NEED_LLAPIC */
+ /* Only Pentium Pro and later have those MSR stuff */
+ debug("Disabling local apic: ");
+ disable_lapic();
+#endif /* !NEED_LAPIC */
+ debug("done.\n");
+ post_code(POST_LAPIC);
+}
return 0;
}
+__weak int board_pci_pre_scan(struct pci_controller *hose)
+{
+ return 0;
+}
+
+__weak int board_pci_post_scan(struct pci_controller *hose)
+{
+ return 0;
+}
+
void pci_init_board(void)
{
struct pci_controller *hose = &x86_hose;
pci_setup_type1(hose);
pci_register_hose(hose);
+ board_pci_pre_scan(hose);
hose->last_busno = pci_hose_scan(hose);
+ board_pci_post_scan(hose);
}
static struct pci_controller *get_hose(void)
--- /dev/null
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 The Chromium Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
+#include <asm/turbo.h>
+
+#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+static inline int get_global_turbo_state(void)
+{
+ return TURBO_UNKNOWN;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+}
+#else
+static int g_turbo_state = TURBO_UNKNOWN;
+
+static inline int get_global_turbo_state(void)
+{
+ return g_turbo_state;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+ g_turbo_state = state;
+}
+#endif
+
+static const char *const turbo_state_desc[] = {
+ [TURBO_UNKNOWN] = "unknown",
+ [TURBO_UNAVAILABLE] = "unavailable",
+ [TURBO_DISABLED] = "available but hidden",
+ [TURBO_ENABLED] = "available and visible"
+};
+
+/*
+ * Determine the current state of Turbo and cache it for later.
+ * Turbo is a package level config so it does not need to be
+ * enabled on every core.
+ */
+int turbo_get_state(void)
+{
+ struct cpuid_result cpuid_regs;
+ int turbo_en, turbo_cap;
+ msr_t msr;
+ int turbo_state = get_global_turbo_state();
+
+ /* Return cached state if available */
+ if (turbo_state != TURBO_UNKNOWN)
+ return turbo_state;
+
+ cpuid_regs = cpuid(CPUID_LEAF_PM);
+ turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
+
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
+
+ if (!turbo_cap && turbo_en) {
+ /* Unavailable */
+ turbo_state = TURBO_UNAVAILABLE;
+ } else if (!turbo_cap && !turbo_en) {
+ /* Available but disabled */
+ turbo_state = TURBO_DISABLED;
+ } else if (turbo_cap && turbo_en) {
+ /* Available */
+ turbo_state = TURBO_ENABLED;
+ }
+
+ set_global_turbo_state(turbo_state);
+ debug("Turbo is %s\n", turbo_state_desc[turbo_state]);
+ return turbo_state;
+}
+
+void turbo_enable(void)
+{
+ msr_t msr;
+
+ /* Only possible if turbo is available but hidden */
+ if (turbo_get_state() == TURBO_DISABLED) {
+ /* Clear Turbo Disable bit in Misc Enables */
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ msr.hi &= ~H_MISC_DISABLE_TURBO;
+ msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+ /* Update cached turbo state */
+ set_global_turbo_state(TURBO_ENABLED);
+ debug("Turbo has been enabled\n");
+ }
+}
. = ALIGN(4);
__rel_dyn_start = .;
- .rel.dyn : { *(.rel.dyn) }
+ .rel.dyn : {
+ *(.rel*)
+ }
__rel_dyn_end = .;
. = ALIGN(4);
_end = .;
/DISCARD/ : { *(.gnu*) }
#ifdef CONFIG_X86_RESET_VECTOR
-
/*
* The following expressions place the 16-bit Real-Mode code and
* Reset Vector at the end of the Flash ROM
*/
- . = START_16;
- .start16 : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); }
+ . = START_16 - RESET_SEG_START;
+ .start16 : AT (START_16) {
+ KEEP(*(.start16));
+ }
- . = RESET_VEC_LOC;
- .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
+ . = RESET_VEC_LOC - RESET_SEG_START;
+ .resetvec : AT (RESET_VEC_LOC) {
+ KEEP(*(.resetvec));
+ }
#endif
+
}
};
};
- lpc {
- compatible = "intel,lpc";
- #address-cells = <1>;
- #size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
- cros-ec@200 {
- compatible = "google,cros-ec";
- reg = <0x204 1 0x200 1 0x880 0x80>;
+ pci {
+ sata {
+ compatible = "intel,pantherpoint-ahci";
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+ };
+
+ gma {
+ compatible = "intel,gma";
+ intel,dp_hotplug = <0 0 0x06>;
+ intel,panel-port-select = <1>;
+ intel,panel-power-cycle-delay = <6>;
+ intel,panel-power-up-delay = <2000>;
+ intel,panel-power-down-delay = <500>;
+ intel,panel-power-backlight-on-delay = <2000>;
+ intel,panel-power-backlight-off-delay = <2000>;
+ intel,cpu-backlight = <0x00000200>;
+ intel,pch-backlight = <0x04000000>;
+ };
- /* This describes the flash memory within the EC */
+ lpc {
+ compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
- flash@8000000 {
- reg = <0x08000000 0x20000>;
- erase-value = <0xff>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+ 0x80 0x80 0x80 0x80>;
+ intel,gpi-routing = <0 0 0 0 0 0 0 2
+ 1 0 0 0 0 0 0 0>;
+ /* Enable EC SMI source */
+ intel,alt-gp-smi-enable = <0x0100>;
+
+ cros-ec@200 {
+ compatible = "google,cros-ec";
+ reg = <0x204 1 0x200 1 0x880 0x80>;
+
+ /* Describes the flash memory within the EC */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0xff>;
+ };
};
};
};
--- /dev/null
+/*
+ * From coreboot
+ *
+ * Copyright (C) 2004 SUSE LINUX AG
+ * Copyright (C) 2004 Nick Barker
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan@coresystems.de>)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ACPI_H
+#define __ASM_ACPI_H
+
+#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
+#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */
+#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */
+#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */
+
+/* 0 = S0, 1 = S1 ...*/
+int acpi_get_slp_type(void);
+void apci_set_slp_type(int type);
+
+#endif
#define _COREBOOT_SYSINFO_H
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <libfdt.h>
#include <asm/arch/tables.h>
#ifndef _COREBOOT_TABLES_H
#define _COREBOOT_TABLES_H
-#include <compiler.h>
+#include <linux/compiler.h>
struct cbuint64 {
u32 lo;
--- /dev/null
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_BD82X6X_H
+#define _ASM_ARCH_BD82X6X_H
+
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
+void bd82x6x_pci_init(pci_dev_t dev);
+void bd82x6x_usb_ehci_init(pci_dev_t dev);
+void bd82x6x_usb_xhci_init(pci_dev_t dev);
+int bd82x6x_init_pci_devices(void);
+int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
+ const void *blob, int node);
+int bd82x6x_init(void);
+
+struct x86_cpu_priv;
+int model_206ax_init(struct x86_cpu_priv *cpu);
+
+#endif
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+int cpu_config_tdp_levels(void);
+
#endif
#include <pci.h>
+/* PCH types */
+#define PCH_TYPE_CPT 0x1c /* CougarPoint */
+#define PCH_TYPE_PPT 0x1e /* IvyBridge */
+
+/* PCH stepping values for LPC device */
+#define PCH_STEP_A0 0
+#define PCH_STEP_A1 1
+#define PCH_STEP_B0 2
+#define PCH_STEP_B1 3
+#define PCH_STEP_B2 4
+#define PCH_STEP_B3 5
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
#define SMBUS_IO_BASE 0x0400
+int pch_silicon_revision(void);
+int pch_silicon_type(void);
+int pch_silicon_supported(int type, int rev);
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS 0x06
+#define SMLT 0x1b
+#define SECSTS 0x1e
+#define INTR 0x3c
+#define BCTRL 0x3e
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
+
#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xa0
+#define GEN_PMCON_2 0xa2
+#define GEN_PMCON_3 0xa4
+#define ETR3 0xac
+#define ETR3_CWORWRE (1 << 18)
+#define ETR3_CF9GR (1 << 20)
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD (1 << 2)
+#define RTC_POWER_FAILED (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
+#define PMBASE 0x40
+#define ACPI_CNTL 0x44
+#define BIOS_CNTL 0xDC
+#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT 0xb8
+
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x68
+#define PIRQF_ROUT 0x69
+#define PIRQG_ROUT 0x6A
+#define PIRQH_ROUT 0x6B
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
+#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
+#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
+
+#define INTR_LN 0x3c
+#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
+#define IDE_DECODE_ENABLE (1 << 15)
+#define IDE_SITRE (1 << 14)
+#define IDE_ISP_5_CLOCKS (0 << 12)
+#define IDE_ISP_4_CLOCKS (1 << 12)
+#define IDE_ISP_3_CLOCKS (2 << 12)
+#define IDE_RCT_4_CLOCKS (0 << 8)
+#define IDE_RCT_3_CLOCKS (1 << 8)
+#define IDE_RCT_2_CLOCKS (2 << 8)
+#define IDE_RCT_1_CLOCKS (3 << 8)
+#define IDE_DTE1 (1 << 7)
+#define IDE_PPE1 (1 << 6)
+#define IDE_IE1 (1 << 5)
+#define IDE_TIME1 (1 << 4)
+#define IDE_DTE0 (1 << 3)
+#define IDE_PPE0 (1 << 2)
+#define IDE_IE0 (1 << 1)
+#define IDE_TIME0 (1 << 0)
+#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
+
+#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
+#define IDE_SSDE1 (1 << 3)
+#define IDE_SSDE0 (1 << 2)
+#define IDE_PSDE1 (1 << 1)
+#define IDE_PSDE0 (1 << 0)
+
+#define IDE_SDMA_TIM 0x4a
+
+#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
+#define SIG_MODE_SEC_NORMAL (0 << 18)
+#define SIG_MODE_SEC_TRISTATE (1 << 18)
+#define SIG_MODE_SEC_DRIVELOW (2 << 18)
+#define SIG_MODE_PRI_NORMAL (0 << 16)
+#define SIG_MODE_PRI_TRISTATE (1 << 16)
+#define SIG_MODE_PRI_DRIVELOW (2 << 16)
+#define FAST_SCB1 (1 << 15)
+#define FAST_SCB0 (1 << 14)
+#define FAST_PCB1 (1 << 13)
+#define FAST_PCB0 (1 << 12)
+#define SCB1 (1 << 3)
+#define SCB0 (1 << 2)
+#define PCB1 (1 << 1)
+#define PCB0 (1 << 0)
+
+#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
+#define SATA_SP 0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR 0xea000151
+#define SATA_IOBP_SP1G3IR 0xea000051
+
/* PCI Configuration Space (D31:F3): SMBus */
#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
#define SMB_BASE 0x20
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
+int lpc_init(struct pci_controller *hose, pci_dev_t dev);
+void lpc_enable(pci_dev_t dev);
+
/**
* lpc_early_init() - set up LPC serial ports and other early things
*
/*
* MCHBAR
*/
-#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg))
+#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg))
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
#define BIOS_RESET_CPL 0x5da8 /* 8bit */
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
+
+int bridge_silicon_revision(void);
+
+void northbridge_enable(pci_dev_t dev);
+void northbridge_init(pci_dev_t dev);
+
void report_platform_info(void);
void sandybridge_early_init(int chipset_type);
#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
#define ICW4_PM 0x01 /* Microprocessor Mode */
+int i8259_init(void);
+
#endif
extern char exception_stack[];
+/**
+ * configure_irq_trigger() - Configure IRQ triggering
+ *
+ * Switch the given interrupt to be level / edge triggered
+ *
+ * @param int_num legacy interrupt number (3-7, 9-15)
+ * @param is_level_triggered true for level triggered interrupt, false for
+ * edge triggered interrupt
+ */
+void configure_irq_trigger(int int_num, bool is_level_triggered);
+
#endif
#ifndef _ASM_IO_H
#define _ASM_IO_H
-#include <compiler.h>
+#include <linux/compiler.h>
/*
* This file contains the definitions for the x86 IO instructions
--- /dev/null
+/*
+ * From coreboot file of the same name
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_IOAPIC_H
+#define __ASM_IOAPIC_H
+
+#define IO_APIC_ADDR 0xfec00000
+#define IO_APIC_INDEX IO_APIC_ADDR
+#define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
+#define IO_APIC_INTERRUPTS 24
+
+#define ALL (0xff << 24)
+#define NONE 0
+#define DISABLED (1 << 16)
+#define ENABLED (0 << 16)
+#define TRIGGER_EDGE (0 << 15)
+#define TRIGGER_LEVEL (1 << 15)
+#define POLARITY_HIGH (0 << 13)
+#define POLARITY_LOW (1 << 13)
+#define PHYSICAL_DEST (0 << 11)
+#define LOGICAL_DEST (1 << 11)
+#define ExtINT (7 << 8)
+#define NMI (4 << 8)
+#define SMI (2 << 8)
+#define INT (1 << 8)
+
+u32 io_apic_read(u32 ioapic_base, u32 reg);
+void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
+void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
+void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
+void clear_ioapic(u32 ioapic_base);
+
+#endif
#include <asm/msr.h>
#include <asm/processor.h>
+/* See if I need to initialize the local apic */
+#if CONFIG_SMP || CONFIG_IOAPIC
+# define NEED_LAPIC 1
+#else
+# define NEED_LAPIC 0
+#endif
+
static inline __attribute__((always_inline))
unsigned long lapic_read(unsigned long reg)
{
msr = msr_read(LAPIC_BASE_MSR);
msr.hi &= 0xffffff00;
- msr.lo &= 0x000007ff;
- msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
+ msr.lo |= LAPIC_BASE_MSR_ENABLE;
+ msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
+ msr.lo |= LAPIC_DEFAULT_BASE;
msr_write(LAPIC_BASE_MSR, msr);
}
return lapic_read(LAPIC_ID) >> 24;
}
+#if !CONFIG_AP_IN_SIPI_WAIT
+/* If we need to go back to sipi wait, we use the long non-inlined version of
+ * this function in lapic_cpu_init.c
+ */
+static inline __attribute__((always_inline)) void stop_this_cpu(void)
+{
+ /* Called by an AP when it is ready to halt and wait for a new task */
+ for (;;)
+ cpu_hlt();
+}
+#else
+void stop_this_cpu(void);
+#endif
+
+#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+ sizeof(*(ptr))))
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
+
+/*
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note 2: xchg has side effect, so that attribute volatile is necessary,
+ * but generally the primitive is invalid, *ptr is output argument. --ANK
+ */
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+ int size)
+{
+ switch (size) {
+ case 1:
+ __asm__ __volatile__("xchgb %b0,%1"
+ : "=q" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 2:
+ __asm__ __volatile__("xchgw %w0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 4:
+ __asm__ __volatile__("xchgl %0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ }
+
+ return x;
+}
+
+static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
+{
+ (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
+}
+
+
+#ifdef X86_GOOD_APIC
+# define FORCE_READ_AROUND_WRITE 0
+# define lapic_read_around(x) lapic_read(x)
+# define lapic_write_around(x, y) lapic_write((x), (y))
+#else
+# define FORCE_READ_AROUND_WRITE 1
+# define lapic_read_around(x) lapic_read(x)
+# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
+#endif
+
+static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
+{
+ int timeout;
+ unsigned long status;
+ int result;
+ lapic_wait_icr_idle();
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
+ lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+ timeout = 0;
+ do {
+ status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
+ } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
+
+ result = -1;
+ if (status == LAPIC_ICR_RR_VALID) {
+ *pvalue = lapic_read(LAPIC_RRR);
+ result = 0;
+ }
+ return result;
+}
+
+
+void lapic_setup(void);
+
+#if CONFIG_SMP
+struct device;
+int start_cpu(struct device *cpu);
+#endif /* CONFIG_SMP */
+
+int boot_cpu(void);
+
+/**
+ * struct x86_cpu_priv - Information about a single CPU
+ *
+ * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
+ * just a number representing the CPU core
+ *
+ * TODO: Move this to driver model once lifecycle is understood
+ */
+struct x86_cpu_priv {
+ int apic_id;
+ int start_err;
+};
+
#endif
#define MSR_AMD_PERF_STATUS 0xc0010063
#define MSR_AMD_PERF_CTL 0xc0010062
+#define MSR_PMG_CST_CONFIG_CTL 0x000000e2
+#define MSR_PMG_IO_CAPTURE_ADR 0x000000e4
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
struct msr *msrs_alloc(void);
void msrs_free(struct msr *msrs);
-#ifdef CONFIG_SMP
-int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
-void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
-int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
-int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
-
-#endif /* CONFIG_SMP */
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_X86_MSR_H */
*/
int pci_early_init_hose(struct pci_controller **hosep);
+int board_pci_pre_scan(struct pci_controller *hose);
+int board_pci_post_scan(struct pci_controller *hose);
+
/*
* Simple PCI access routines - these work from either the early PCI hose
* or the 'real' one, created after U-Boot has memory available
#define POST_PRE_MRC 0x2e
#define POST_MRC 0x2f
#define POST_DRAM 0x2f
+#define POST_LAPIC 0x30
#define POST_RAM_FAILURE 0xea
#ifndef __ASM_PROCESSOR_H_
#define __ASM_PROCESSOR_H_ 1
-#define X86_GDT_ENTRY_SIZE 8
-
-#ifndef __ASSEMBLY__
-
-enum {
- X86_GDT_ENTRY_NULL = 0,
- X86_GDT_ENTRY_UNUSED,
- X86_GDT_ENTRY_32BIT_CS,
- X86_GDT_ENTRY_32BIT_DS,
- X86_GDT_ENTRY_32BIT_FS,
- X86_GDT_ENTRY_16BIT_CS,
- X86_GDT_ENTRY_16BIT_DS,
- X86_GDT_NUM_ENTRIES
-};
-#else
-/* NOTE: If the above enum is modified, this define must be checked */
-#define X86_GDT_ENTRY_32BIT_DS 3
-#define X86_GDT_NUM_ENTRIES 7
-#endif
+#define X86_GDT_ENTRY_SIZE 8
+
+#define X86_GDT_ENTRY_NULL 0
+#define X86_GDT_ENTRY_UNUSED 1
+#define X86_GDT_ENTRY_32BIT_CS 2
+#define X86_GDT_ENTRY_32BIT_DS 3
+#define X86_GDT_ENTRY_32BIT_FS 4
+#define X86_GDT_ENTRY_16BIT_CS 5
+#define X86_GDT_ENTRY_16BIT_DS 6
+#define X86_GDT_ENTRY_16BIT_FLAT_CS 7
+#define X86_GDT_ENTRY_16BIT_FLAT_DS 8
+#define X86_GDT_NUM_ENTRIES 9
#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
--- /dev/null
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * 2012 secunet Security Networks AG
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_SPEEDSTEP_H
+#define _ASM_SPEEDSTEP_H
+
+/* Magic value used to locate speedstep configuration in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+/* MWAIT coordination I/O base address. This must match
+ * the \_PR_.CPU0 PM base address.
+ */
+#define PMB0_BASE 0x510
+
+/* PMB1: I/O port that triggers SMI once cores are in the same state.
+ * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
+ */
+#define PMB1_BASE 0x800
+
+struct sst_state {
+ uint8_t dynfsb:1; /* whether this is SLFM */
+ uint8_t nonint:1; /* add .5 to ratio */
+ uint8_t ratio:6;
+ uint8_t vid;
+ uint8_t is_turbo;
+ uint8_t is_slfm;
+ uint32_t power;
+};
+#define SPEEDSTEP_RATIO_SHIFT 8
+#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
+#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
+#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_VID_MASK 0x3f
+#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \
+ 0, /* dynfsb won't be read. */ \
+ ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \
+ (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \
+ >> SPEEDSTEP_RATIO_SHIFT), \
+ (val & mask) & SPEEDSTEP_VID_MASK, \
+ 0, /* not turbo by default */ \
+ 0, /* not slfm by default */ \
+ 0 /* power is hardcoded in software. */ \
+ })
+#define SPEEDSTEP_ENCODE_STATE(state) ( \
+ ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \
+ ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \
+ ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
+ ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
+#define SPEEDSTEP_DOUBLE_RATIO(state) ( \
+ ((uint8_t)(state).ratio * 2) + (state).nonint)
+
+struct sst_params {
+ struct sst_state slfm;
+ struct sst_state min;
+ struct sst_state max;
+ struct sst_state turbo;
+};
+
+/* Looking at core2's spec, the highest normal bus ratio for an eist enabled
+ processor is 14, the lowest is always 6. This makes 5 states with the
+ minimal step width of 2. With turbo mode and super LFM we have at most 7. */
+#define SPEEDSTEP_MAX_NORMAL_STATES 5
+#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2)
+struct sst_table {
+ /* Table of p-states for EMTTM and ACPI by decreasing performance. */
+ struct sst_state states[SPEEDSTEP_MAX_STATES];
+ int num_states;
+};
+
+void speedstep_gen_pstates(struct sst_table *);
+
+#define SPEEDSTEP_MAX_POWER_YONAH 31000
+#define SPEEDSTEP_MIN_POWER_YONAH 13100
+#define SPEEDSTEP_MAX_POWER_MEROM 35000
+#define SPEEDSTEP_MIN_POWER_MEROM 25000
+#define SPEEDSTEP_SLFM_POWER_MEROM 12000
+#define SPEEDSTEP_MAX_POWER_PENRYN 35000
+#define SPEEDSTEP_MIN_POWER_PENRYN 15000
+#define SPEEDSTEP_SLFM_POWER_PENRYN 12000
+
+#endif
--- /dev/null
+/*
+ * From coreboot file of the same name
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_TURBO_H
+#define _ASM_TURBO_H
+
+#define CPUID_LEAF_PM 6
+#define PM_CAP_TURBO_MODE (1 << 1)
+
+#define MSR_IA32_MISC_ENABLES 0x1a0
+#define H_MISC_DISABLE_TURBO (1 << 6)
+
+enum {
+ TURBO_UNKNOWN,
+ TURBO_UNAVAILABLE,
+ TURBO_DISABLED,
+ TURBO_ENABLED,
+};
+
+/* Return current turbo state */
+int turbo_get_state(void);
+
+/* Enable turbo */
+void turbo_enable(void);
+
+#endif
/* cpu/.../cpu.c */
int arch_cpu_init(void);
-int x86_cpu_init_r(void);
-int cpu_init_r(void);
int x86_cpu_init_f(void);
int cpu_init_f(void);
void init_gd(gd_t *id, u64 *gdt_addr);
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += bios.o
+obj-y += bios_asm.o
+obj-y += bios_interrupts.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cmd_boot.o
obj-y += gcc.o
--- /dev/null
+/*
+ * From Coreboot file device/oprom/realmode/x86.c
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <bios_emul.h>
+#include <vbe.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/i8259.h>
+#include <asm/io.h>
+#include <asm/post.h>
+#include "bios.h"
+
+/* Interrupt handlers for each interrupt the ROM can call */
+static int (*int_handler[256])(void);
+
+/* to have a common register file for interrupt handlers */
+X86EMU_sysEnv _X86EMU_env;
+
+asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+ u32 esi, u32 edi);
+
+asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx,
+ u32 edx, u32 esi, u32 edi);
+
+static void setup_realmode_code(void)
+{
+ memcpy((void *)REALMODE_BASE, &asm_realmode_code,
+ asm_realmode_code_size);
+
+ /* Ensure the global pointers are relocated properly. */
+ realmode_call = PTR_TO_REAL_MODE(asm_realmode_call);
+ realmode_interrupt = PTR_TO_REAL_MODE(__realmode_interrupt);
+
+ debug("Real mode stub @%x: %d bytes\n", REALMODE_BASE,
+ asm_realmode_code_size);
+}
+
+static void setup_rombios(void)
+{
+ const char date[] = "06/11/99";
+ memcpy((void *)0xffff5, &date, 8);
+
+ const char ident[] = "PCI_ISA";
+ memcpy((void *)0xfffd9, &ident, 7);
+
+ /* system model: IBM-AT */
+ writeb(0xfc, 0xffffe);
+}
+
+static int int_exception_handler(void)
+{
+ /* compatibility shim */
+ struct eregs reg_info = {
+ .eax = M.x86.R_EAX,
+ .ecx = M.x86.R_ECX,
+ .edx = M.x86.R_EDX,
+ .ebx = M.x86.R_EBX,
+ .esp = M.x86.R_ESP,
+ .ebp = M.x86.R_EBP,
+ .esi = M.x86.R_ESI,
+ .edi = M.x86.R_EDI,
+ .vector = M.x86.intno,
+ .error_code = 0,
+ .eip = M.x86.R_EIP,
+ .cs = M.x86.R_CS,
+ .eflags = M.x86.R_EFLG
+ };
+ struct eregs *regs = ®_info;
+
+ debug("Oops, exception %d while executing option rom\n", regs->vector);
+ cpu_hlt();
+
+ return 0;
+}
+
+static int int_unknown_handler(void)
+{
+ debug("Unsupported software interrupt #0x%x eax 0x%x\n",
+ M.x86.intno, M.x86.R_EAX);
+
+ return -1;
+}
+
+/* setup interrupt handlers for mainboard */
+void bios_set_interrupt_handler(int intnum, int (*int_func)(void))
+{
+ int_handler[intnum] = int_func;
+}
+
+static void setup_interrupt_handlers(void)
+{
+ int i;
+
+ /*
+ * The first 16 int_handler functions are not BIOS services,
+ * but the CPU-generated exceptions ("hardware interrupts")
+ */
+ for (i = 0; i < 0x10; i++)
+ int_handler[i] = &int_exception_handler;
+
+ /* Mark all other int_handler calls as unknown first */
+ for (i = 0x10; i < 0x100; i++) {
+ /* Skip if bios_set_interrupt_handler() isn't called first */
+ if (int_handler[i])
+ continue;
+
+ /*
+ * Now set the default functions that are actually needed
+ * to initialize the option roms. The board may override
+ * these with bios_set_interrupt_handler()
+ */
+ switch (i) {
+ case 0x10:
+ int_handler[0x10] = &int10_handler;
+ break;
+ case 0x12:
+ int_handler[0x12] = &int12_handler;
+ break;
+ case 0x16:
+ int_handler[0x16] = &int16_handler;
+ break;
+ case 0x1a:
+ int_handler[0x1a] = &int1a_handler;
+ break;
+ default:
+ int_handler[i] = &int_unknown_handler;
+ break;
+ }
+ }
+}
+
+static void write_idt_stub(void *target, u8 intnum)
+{
+ unsigned char *codeptr;
+
+ codeptr = (unsigned char *)target;
+ memcpy(codeptr, &__idt_handler, __idt_handler_size);
+ codeptr[3] = intnum; /* modify int# in the code stub. */
+}
+
+static void setup_realmode_idt(void)
+{
+ struct realmode_idt *idts = NULL;
+ int i;
+
+ /*
+ * Copy IDT stub code for each interrupt. This might seem wasteful
+ * but it is really simple
+ */
+ for (i = 0; i < 256; i++) {
+ idts[i].cs = 0;
+ idts[i].offset = 0x1000 + (i * __idt_handler_size);
+ write_idt_stub((void *)((u32)idts[i].offset), i);
+ }
+
+ /*
+ * Many option ROMs use the hard coded interrupt entry points in the
+ * system bios. So install them at the known locations.
+ */
+
+ /* int42 is the relocated int10 */
+ write_idt_stub((void *)0xff065, 0x42);
+ /* BIOS Int 11 Handler F000:F84D */
+ write_idt_stub((void *)0xff84d, 0x11);
+ /* BIOS Int 12 Handler F000:F841 */
+ write_idt_stub((void *)0xff841, 0x12);
+ /* BIOS Int 13 Handler F000:EC59 */
+ write_idt_stub((void *)0xfec59, 0x13);
+ /* BIOS Int 14 Handler F000:E739 */
+ write_idt_stub((void *)0xfe739, 0x14);
+ /* BIOS Int 15 Handler F000:F859 */
+ write_idt_stub((void *)0xff859, 0x15);
+ /* BIOS Int 16 Handler F000:E82E */
+ write_idt_stub((void *)0xfe82e, 0x16);
+ /* BIOS Int 17 Handler F000:EFD2 */
+ write_idt_stub((void *)0xfefd2, 0x17);
+ /* ROM BIOS Int 1A Handler F000:FE6E */
+ write_idt_stub((void *)0xffe6e, 0x1a);
+}
+
+static u8 vbe_get_mode_info(struct vbe_mode_info *mi)
+{
+ u16 buffer_seg;
+ u16 buffer_adr;
+ char *buffer;
+
+ debug("VBE: Getting information about VESA mode %04x\n",
+ mi->video_mode);
+ buffer = PTR_TO_REAL_MODE(asm_realmode_buffer);
+ buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00;
+ buffer_adr = ((unsigned long)buffer) & 0xffff;
+
+ realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode,
+ 0x0000, buffer_seg, buffer_adr);
+ memcpy(mi->mode_info_block, buffer, sizeof(struct vbe_mode_info));
+ mi->valid = true;
+
+ return 0;
+}
+
+static u8 vbe_set_mode(struct vbe_mode_info *mi)
+{
+ debug("VBE: Setting VESA mode %#04x\n", mi->video_mode);
+ /* request linear framebuffer mode */
+ mi->video_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ mi->video_mode &= ~(1 << 15);
+ realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode,
+ 0x0000, 0x0000, 0x0000, 0x0000);
+
+ return 0;
+}
+
+static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info)
+{
+ unsigned char *framebuffer;
+
+ mode_info->video_mode = (1 << 14) | vesa_mode;
+ vbe_get_mode_info(mode_info);
+
+ framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr;
+ debug("VBE: resolution: %dx%d@%d\n",
+ le16_to_cpu(mode_info->vesa.x_resolution),
+ le16_to_cpu(mode_info->vesa.y_resolution),
+ mode_info->vesa.bits_per_pixel);
+ debug("VBE: framebuffer: %p\n", framebuffer);
+ if (!framebuffer) {
+ debug("VBE: Mode does not support linear framebuffer\n");
+ return;
+ }
+
+ vbe_set_mode(mode_info);
+}
+
+void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ u32 num_dev;
+
+ num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 |
+ PCI_FUNC(pcidev);
+
+ /* Needed to avoid exceptions in some ROMs */
+ interrupt_init();
+
+ /* Set up some legacy information in the F segment */
+ setup_rombios();
+
+ /* Set up C interrupt handlers */
+ setup_interrupt_handlers();
+
+ /* Set up real-mode IDT */
+ setup_realmode_idt();
+
+ /* Make sure the code is placed. */
+ setup_realmode_code();
+
+ disable_caches();
+ debug("Calling Option ROM at %lx, pci device %#x...", addr, num_dev);
+
+ /* Option ROM entry point is at OPROM start + 3 */
+ realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0,
+ 0x0);
+ debug("done\n");
+
+ if (vesa_mode != -1)
+ vbe_set_graphics(vesa_mode, mode_info);
+}
+
+asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses,
+ u32 edi, u32 esi, u32 ebp, u32 esp,
+ u32 ebx, u32 edx, u32 ecx, u32 eax,
+ u32 cs_ip, u16 stackflags)
+{
+ u32 ip;
+ u32 cs;
+ u32 flags;
+ int ret = 0;
+
+ ip = cs_ip & 0xffff;
+ cs = cs_ip >> 16;
+ flags = stackflags;
+
+#ifdef CONFIG_REALMODE_DEBUG
+ debug("oprom: INT# 0x%x\n", intnumber);
+ debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n",
+ eax, ebx, ecx, edx);
+ debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n",
+ ebp, esp, edi, esi);
+ debug("oprom: ip: %04x cs: %04x flags: %08x\n",
+ ip, cs, flags);
+ debug("oprom: stackflags = %04x\n", stackflags);
+#endif
+
+ /*
+ * Fetch arguments from the stack and put them to a place
+ * suitable for the interrupt handlers
+ */
+ M.x86.R_EAX = eax;
+ M.x86.R_ECX = ecx;
+ M.x86.R_EDX = edx;
+ M.x86.R_EBX = ebx;
+ M.x86.R_ESP = esp;
+ M.x86.R_EBP = ebp;
+ M.x86.R_ESI = esi;
+ M.x86.R_EDI = edi;
+ M.x86.intno = intnumber;
+ M.x86.R_EIP = ip;
+ M.x86.R_CS = cs;
+ M.x86.R_EFLG = flags;
+
+ /* Call the interrupt handler for this interrupt number */
+ ret = int_handler[intnumber]();
+
+ /*
+ * This code is quite strange...
+ *
+ * Put registers back on the stack. The assembler code will pop them
+ * later. We force (volatile!) changing the values of the parameters
+ * of this function. We know that they stay alive on the stack after
+ * we leave this function.
+ */
+ *(volatile u32 *)&eax = M.x86.R_EAX;
+ *(volatile u32 *)&ecx = M.x86.R_ECX;
+ *(volatile u32 *)&edx = M.x86.R_EDX;
+ *(volatile u32 *)&ebx = M.x86.R_EBX;
+ *(volatile u32 *)&esi = M.x86.R_ESI;
+ *(volatile u32 *)&edi = M.x86.R_EDI;
+ flags = M.x86.R_EFLG;
+
+ /* Pass success or error back to our caller via the CARRY flag */
+ if (ret) {
+ flags &= ~1; /* no error: clear carry */
+ } else {
+ debug("int%02x call returned error\n", intnumber);
+ flags |= 1; /* error: set carry */
+ }
+ *(volatile u16 *)&stackflags = flags;
+
+ return ret;
+}
--- /dev/null
+/*
+ * From Coreboot file device/oprom/realmode/x86.h
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _X86_LIB_BIOS_H
+#define _X86_LIB_BIOS_H
+
+#define REALMODE_BASE 0x600
+
+#ifdef __ASSEMBLY__
+
+#define PTR_TO_REAL_MODE(x) (x - asm_realmode_code + REALMODE_BASE)
+
+#else
+
+/* Convert a symbol address to our real mode area */
+#define PTR_TO_REAL_MODE(sym)\
+ (void *)(REALMODE_BASE + ((char *)&(sym) - (char *)&asm_realmode_code))
+
+/*
+ * The following symbols cannot be used directly. They need to be fixed up
+ * to point to the correct address location after the code has been copied
+ * to REALMODE_BASE. Absolute symbols are not used because those symbols are
+ * relocated by U-Boot.
+ */
+extern unsigned char asm_realmode_call, __realmode_interrupt;
+extern unsigned char asm_realmode_buffer;
+
+#define DOWNTO8(A) \
+ union { \
+ struct { \
+ union { \
+ struct { \
+ uint8_t A##l; \
+ uint8_t A##h; \
+ } __packed; \
+ uint16_t A##x; \
+ } __packed; \
+ uint16_t h##A##x; \
+ } __packed; \
+ uint32_t e##A##x; \
+ } __packed;
+
+#define DOWNTO16(A) \
+ union { \
+ struct { \
+ uint16_t A; \
+ uint16_t h##A; \
+ } __packed; \
+ uint32_t e##A; \
+ } __packed;
+
+struct eregs {
+ DOWNTO8(a);
+ DOWNTO8(c);
+ DOWNTO8(d);
+ DOWNTO8(b);
+ DOWNTO16(sp);
+ DOWNTO16(bp);
+ DOWNTO16(si);
+ DOWNTO16(di);
+ uint32_t vector;
+ uint32_t error_code;
+ uint32_t eip;
+ uint32_t cs;
+ uint32_t eflags;
+};
+
+struct realmode_idt {
+ u16 offset, cs;
+};
+
+void x86_exception(struct eregs *info);
+
+/* From x86_asm.S */
+extern unsigned char __idt_handler;
+extern unsigned int __idt_handler_size;
+extern unsigned char asm_realmode_code;
+extern unsigned int asm_realmode_code_size;
+
+asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+ u32 esi, u32 edi);
+
+asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx,
+ u32 edx, u32 esi, u32 edi);
+
+int int10_handler(void);
+int int12_handler(void);
+int int16_handler(void);
+int int1a_handler(void);
+#endif /*__ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * From coreboot x86_asm.S, cleaned up substantially
+ *
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm/processor.h>
+#include <asm/processor-flags.h>
+#include "bios.h"
+
+#define SEG(segment) $segment * X86_GDT_ENTRY_SIZE
+
+/*
+ * This is the interrupt handler stub code. It gets copied to the IDT and
+ * to some fixed addresses in the F segment. Before the code can used,
+ * it gets patched up by the C function copying it: byte 3 (the $0 in
+ * movb $0, %al) is overwritten with the interrupt numbers.
+ */
+
+ .code16
+ .globl __idt_handler
+__idt_handler:
+ pushal
+ movb $0, %al /* This instruction gets modified */
+ ljmp $0, $__interrupt_handler_16bit
+ .globl __idt_handler_size
+__idt_handler_size:
+ .long . - __idt_handler
+
+.macro setup_registers
+ /* initial register values */
+ movl 44(%ebp), %eax
+ movl %eax, __registers + 0 /* eax */
+ movl 48(%ebp), %eax
+ movl %eax, __registers + 4 /* ebx */
+ movl 52(%ebp), %eax
+ movl %eax, __registers + 8 /* ecx */
+ movl 56(%ebp), %eax
+ movl %eax, __registers + 12 /* edx */
+ movl 60(%ebp), %eax
+ movl %eax, __registers + 16 /* esi */
+ movl 64(%ebp), %eax
+ movl %eax, __registers + 20 /* edi */
+.endm
+
+.macro enter_real_mode
+ /* Activate the right segment descriptor real mode. */
+ ljmp SEG(X86_GDT_ENTRY_16BIT_CS), $PTR_TO_REAL_MODE(1f)
+1:
+.code16
+ /*
+ * Load the segment registers with properly configured segment
+ * descriptors. They will retain these configurations (limits,
+ * writability, etc.) once protected mode is turned off.
+ */
+ mov SEG(X86_GDT_ENTRY_16BIT_DS), %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov %ax, %ss
+
+ /* Turn off protection */
+ movl %cr0, %eax
+ andl $~X86_CR0_PE, %eax
+ movl %eax, %cr0
+
+ /* Now really going into real mode */
+ ljmp $0, $PTR_TO_REAL_MODE(1f)
+1:
+ /*
+ * Set up a stack: Put the stack at the end of page zero. That way
+ * we can easily share it between real and protected, since the
+ * 16-bit ESP at segment 0 will work for any case.
+ */
+ mov $0x0, %ax
+ mov %ax, %ss
+
+ /* Load 16 bit IDT */
+ xor %ax, %ax
+ mov %ax, %ds
+ lidt __realmode_idt
+
+.endm
+
+.macro prepare_for_irom
+ movl $0x1000, %eax
+ movl %eax, %esp
+
+ /* Initialise registers for option rom lcall */
+ movl __registers + 0, %eax
+ movl __registers + 4, %ebx
+ movl __registers + 8, %ecx
+ movl __registers + 12, %edx
+ movl __registers + 16, %esi
+ movl __registers + 20, %edi
+
+ /* Set all segments to 0x0000, ds to 0x0040 */
+ push %ax
+ xor %ax, %ax
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov SEG(X86_GDT_ENTRY_16BIT_FLAT_DS), %ax
+ mov %ax, %ds
+ pop %ax
+
+.endm
+
+.macro enter_protected_mode
+ /* Go back to protected mode */
+ movl %cr0, %eax
+ orl $X86_CR0_PE, %eax
+ movl %eax, %cr0
+
+ /* Now that we are in protected mode jump to a 32 bit code segment */
+ data32 ljmp SEG(X86_GDT_ENTRY_32BIT_CS), $PTR_TO_REAL_MODE(1f)
+1:
+ .code32
+ mov SEG(X86_GDT_ENTRY_32BIT_DS), %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %gs
+ mov %ax, %ss
+ mov SEG(X86_GDT_ENTRY_32BIT_FS), %ax
+ mov %ax, %fs
+
+ /* restore proper idt */
+ lidt idt_ptr
+.endm
+
+/*
+ * In order to be independent of U-Boot's position in RAM we relocate a part
+ * of the code to the first megabyte of RAM, so the CPU can use it in
+ * real-mode. This code lives at asm_realmode_code.
+ */
+ .globl asm_realmode_code
+asm_realmode_code:
+
+/* Realmode IDT pointer structure. */
+__realmode_idt = PTR_TO_REAL_MODE(.)
+ .word 1023 /* 16 bit limit */
+ .long 0 /* 24 bit base */
+ .word 0
+
+/* Preserve old stack */
+__stack = PTR_TO_REAL_MODE(.)
+ .long 0
+
+/* Register store for realmode_call and realmode_interrupt */
+__registers = PTR_TO_REAL_MODE(.)
+ .long 0 /* 0 - EAX */
+ .long 0 /* 4 - EBX */
+ .long 0 /* 8 - ECX */
+ .long 0 /* 12 - EDX */
+ .long 0 /* 16 - ESI */
+ .long 0 /* 20 - EDI */
+
+/* 256 byte buffer, used by int10 */
+ .globl asm_realmode_buffer
+asm_realmode_buffer:
+ .skip 256
+
+ .code32
+ .globl asm_realmode_call
+asm_realmode_call:
+ /* save all registers to the stack */
+ pusha
+ pushf
+ movl %esp, __stack
+ movl %esp, %ebp
+
+ /*
+ * This function is called with regparm=0 and we have to skip the
+ * 36 bytes from pushf+pusha. Hence start at 40.
+ * Set up our call instruction.
+ */
+ movl 40(%ebp), %eax
+ mov %ax, __lcall_instr + 1
+ andl $0xffff0000, %eax
+ shrl $4, %eax
+ mov %ax, __lcall_instr + 3
+
+ wbinvd
+
+ setup_registers
+ enter_real_mode
+ prepare_for_irom
+
+__lcall_instr = PTR_TO_REAL_MODE(.)
+ .byte 0x9a
+ .word 0x0000, 0x0000
+
+ enter_protected_mode
+
+ /* restore stack pointer, eflags and register values and exit */
+ movl __stack, %esp
+ popf
+ popa
+ ret
+
+ .globl __realmode_interrupt
+__realmode_interrupt:
+ /* save all registers to the stack and store the stack pointer */
+ pusha
+ pushf
+ movl %esp, __stack
+ movl %esp, %ebp
+
+ /*
+ * This function is called with regparm=0 and we have to skip the
+ * 36 bytes from pushf+pusha. Hence start at 40.
+ * Prepare interrupt calling code.
+ */
+ movl 40(%ebp), %eax
+ movb %al, __intXX_instr + 1 /* intno */
+
+ setup_registers
+ enter_real_mode
+ prepare_for_irom
+
+__intXX_instr = PTR_TO_REAL_MODE(.)
+ .byte 0xcd, 0x00 /* This becomes intXX */
+
+ enter_protected_mode
+
+ /* restore stack pointer, eflags and register values and exit */
+ movl __stack, %esp
+ popf
+ popa
+ ret
+
+/*
+ * This is the 16-bit interrupt entry point called by the IDT stub code.
+ *
+ * Before this code code is called, %eax is pushed to the stack, and the
+ * interrupt number is loaded into %al. On return this function cleans up
+ * for its caller.
+ */
+ .code16
+__interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
+ push %ds
+ push %es
+ push %fs
+ push %gs
+
+ /* Clear DF to not break ABI assumptions */
+ cld
+
+ /*
+ * Clean up the interrupt number. We could do this in the stub, but
+ * it would cost two more bytes per stub entry.
+ */
+ andl $0xff, %eax
+ pushl %eax /* ... and make it the first parameter */
+
+ enter_protected_mode
+
+ /* Call the C interrupt handler */
+ movl $interrupt_handler, %eax
+ call *%eax
+
+ enter_real_mode
+
+ /*
+ * Restore all registers, including those manipulated by the C
+ * handler
+ */
+ popl %eax
+ pop %gs
+ pop %fs
+ pop %es
+ pop %ds
+ popal
+ iret
+
+ .globl asm_realmode_code_size
+asm_realmode_code_size:
+ .long . - asm_realmode_code
--- /dev/null
+/*
+ * From Coreboot
+ *
+ * Copyright (C) 2001 Ronald G. Minnich
+ * Copyright (C) 2005 Nick.Barker9@btinternet.com
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/pci.h>
+#include "bios_emul.h"
+
+/* errors go in AH. Just set these up so that word assigns will work */
+enum {
+ PCIBIOS_SUCCESSFUL = 0x0000,
+ PCIBIOS_UNSUPPORTED = 0x8100,
+ PCIBIOS_BADVENDOR = 0x8300,
+ PCIBIOS_NODEV = 0x8600,
+ PCIBIOS_BADREG = 0x8700
+};
+
+int int10_handler(void)
+{
+ static u8 cursor_row, cursor_col;
+ int res = 0;
+
+ switch ((M.x86.R_EAX & 0xff00) >> 8) {
+ case 0x01: /* Set cursor shape */
+ res = 1;
+ break;
+ case 0x02: /* Set cursor position */
+ if (cursor_row != ((M.x86.R_EDX >> 8) & 0xff) ||
+ cursor_col >= (M.x86.R_EDX & 0xff)) {
+ debug("\n");
+ }
+ cursor_row = (M.x86.R_EDX >> 8) & 0xff;
+ cursor_col = M.x86.R_EDX & 0xff;
+ res = 1;
+ break;
+ case 0x03: /* Get cursor position */
+ M.x86.R_EAX &= 0x00ff;
+ M.x86.R_ECX = 0x0607;
+ M.x86.R_EDX = (cursor_row << 8) | cursor_col;
+ res = 1;
+ break;
+ case 0x06: /* Scroll up */
+ debug("\n");
+ res = 1;
+ break;
+ case 0x08: /* Get Character and Mode at Cursor Position */
+ M.x86.R_EAX = 0x0f00 | 'A'; /* White on black 'A' */
+ res = 1;
+ break;
+ case 0x09: /* Write Character and attribute */
+ case 0x0e: /* Write Character */
+ debug("%c", M.x86.R_EAX & 0xff);
+ res = 1;
+ break;
+ case 0x0f: /* Get video mode */
+ M.x86.R_EAX = 0x5002; /*80 x 25 */
+ M.x86.R_EBX &= 0x00ff;
+ res = 1;
+ break;
+ default:
+ printf("Unknown INT10 function %04x\n", M.x86.R_EAX & 0xffff);
+ break;
+ }
+ return res;
+}
+
+int int12_handler(void)
+{
+ M.x86.R_EAX = 64 * 1024;
+ return 1;
+}
+
+int int16_handler(void)
+{
+ int res = 0;
+
+ switch ((M.x86.R_EAX & 0xff00) >> 8) {
+ case 0x00: /* Check for Keystroke */
+ M.x86.R_EAX = 0x6120; /* Space Bar, Space */
+ res = 1;
+ break;
+ case 0x01: /* Check for Keystroke */
+ M.x86.R_EFLG |= 1 << 6; /* Zero Flag set (no key available) */
+ res = 1;
+ break;
+ default:
+ printf("Unknown INT16 function %04x\n", M.x86.R_EAX & 0xffff);
+
+break;
+ }
+ return res;
+}
+
+#define PCI_CONFIG_SPACE_TYPE1 (1 << 0)
+#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4)
+
+int int1a_handler(void)
+{
+ unsigned short func = (unsigned short)M.x86.R_EAX;
+ int retval = 1;
+ unsigned short devid, vendorid, devfn;
+ /* Use short to get rid of gabage in upper half of 32-bit register */
+ short devindex;
+ unsigned char bus;
+ pci_dev_t dev;
+ u32 dword;
+ u16 word;
+ u8 byte, reg;
+
+ switch (func) {
+ case 0xb101: /* PCIBIOS Check */
+ M.x86.R_EDX = 0x20494350; /* ' ICP' */
+ M.x86.R_EAX &= 0xffff0000; /* Clear AH / AL */
+ M.x86.R_EAX |= PCI_CONFIG_SPACE_TYPE1 |
+ PCI_SPECIAL_CYCLE_TYPE1;
+ /*
+ * last bus in the system. Hard code to 255 for now.
+ * dev_enumerate() does not seem to tell us (publically)
+ */
+ M.x86.R_ECX = 0xff;
+ M.x86.R_EDI = 0x00000000; /* protected mode entry */
+ retval = 1;
+ break;
+ case 0xb102: /* Find Device */
+ devid = M.x86.R_ECX;
+ vendorid = M.x86.R_EDX;
+ devindex = M.x86.R_ESI;
+ dev = pci_find_device(vendorid, devid, devindex);
+ if (dev != -1) {
+ unsigned short busdevfn;
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
+ /*
+ * busnum is an unsigned char;
+ * devfn is an int, so we mask it off.
+ */
+ busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 |
+ PCI_FUNC(dev);
+ debug("0x%x: return 0x%x\n", func, busdevfn);
+ M.x86.R_EBX = busdevfn;
+ retval = 1;
+ } else {
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_NODEV;
+ retval = 0;
+ }
+ break;
+ case 0xb10a: /* Read Config Dword */
+ case 0xb109: /* Read Config Word */
+ case 0xb108: /* Read Config Byte */
+ case 0xb10d: /* Write Config Dword */
+ case 0xb10c: /* Write Config Word */
+ case 0xb10b: /* Write Config Byte */
+ devfn = M.x86.R_EBX & 0xff;
+ bus = M.x86.R_EBX >> 8;
+ reg = M.x86.R_EDI;
+ dev = PCI_BDF(bus, devfn >> 3, devfn & 7);
+ if (!dev) {
+ debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func,
+ bus, devfn);
+ /* Or are we supposed to return PCIBIOS_NODEV? */
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_BADREG;
+ retval = 0;
+ return retval;
+ }
+ switch (func) {
+ case 0xb108: /* Read Config Byte */
+ byte = pci_read_config8(dev, reg);
+ M.x86.R_ECX = byte;
+ break;
+ case 0xb109: /* Read Config Word */
+ word = pci_read_config16(dev, reg);
+ M.x86.R_ECX = word;
+ break;
+ case 0xb10a: /* Read Config Dword */
+ dword = pci_read_config32(dev, reg);
+ M.x86.R_ECX = dword;
+ break;
+ case 0xb10b: /* Write Config Byte */
+ byte = M.x86.R_ECX;
+ pci_write_config8(dev, reg, byte);
+ break;
+ case 0xb10c: /* Write Config Word */
+ word = M.x86.R_ECX;
+ pci_write_config16(dev, reg, word);
+ break;
+ case 0xb10d: /* Write Config Dword */
+ dword = M.x86.R_ECX;
+ pci_write_config32(dev, reg, dword);
+ break;
+ }
+
+#ifdef CONFIG_REALMODE_DEBUG
+ debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
+ bus, devfn, reg, M.x86.R_ECX);
+#endif
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
+ retval = 1;
+ break;
+ default:
+ printf("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_UNSUPPORTED;
+ retval = 0;
+ break;
+ }
+
+ return retval;
+}
#error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined"
#endif
-int interrupt_init(void)
+int i8259_init(void)
{
u8 i;
- disable_interrupts();
-
/* Mask all interrupts */
outb(0xff, MASTER_PIC + IMR);
outb(0xff, SLAVE_PIC + IMR);
*/
unmask_irq(2);
- enable_interrupts();
+ /* Interrupt 9 should be level triggered (SCI). The OS might do this */
+ configure_irq_trigger(9, true);
return 0;
}
outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
}
+
+#define ELCR1 0x4d0
+#define ELCR2 0x4d1
+
+void configure_irq_trigger(int int_num, bool is_level_triggered)
+{
+ u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
+
+ debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
+ if (is_level_triggered)
+ int_bits |= (1 << int_num);
+ else
+ int_bits &= ~(1 << int_num);
+
+ /* Write new values */
+ debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
+ outb((u8)(int_bits & 0xff), ELCR1);
+ outb((u8)(int_bits >> 8), ELCR2);
+
+#ifdef PARANOID_IRQ_TRIGGERS
+ /*
+ * Try reading back the new values. This seems like an error but is
+ * not
+ */
+ if (inb(ELCR1) != (int_bits & 0xff)) {
+ printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
+ __func__, (int_bits & 0xff), inb(ELCR1));
+ }
+
+ if (inb(ELCR2) != (int_bits >> 8)) {
+ printf("%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
+ __func__, (int_bits>>8), inb(ELCR2));
+ }
+#endif
+}
/* The size of the region of u-boot that runs out of RAM. */
uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+ if (re_src == re_end)
+ panic("No relocation data");
+
do {
/* Get the location from the relocation entry */
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* From glibc-2.14, sysdeps/i386/memset.c */
-#include <compiler.h>
-#include <asm/string.h>
#include <linux/types.h>
+#include <linux/compiler.h>
+#include <asm/string.h>
typedef uint32_t op_t;
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
#ifdef CONFIG_CMD_NET
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
*/
#include <common.h>
+#include <cros_ec.h>
#include <asm/gpio.h>
int arch_early_init_r(void)
{
- return 0;
-}
+ if (cros_ec_board_init())
+ return -1;
-int board_early_init_r(void)
-{
return 0;
}
+++ /dev/null
-if TARGET_HERMES
-
-config SYS_BOARD
- default "hermes"
-
-config SYS_CONFIG_NAME
- default "hermes"
-
-endif
+++ /dev/null
-HERMES BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/hermes/
-F: include/configs/hermes.h
-F: configs/hermes_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hermes.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- (memctl->memc_br0 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size;
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- uchar value;
- vu_char *caddr = (vu_char *)addr;
- ulong base = (ulong)addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- caddr[0x0AAA] = 0xAA;
- caddr[0x0555] = 0x55;
- caddr[0x0AAA] = 0x90;
-
- value = caddr[0];
- switch (value) {
- case (AMD_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = caddr[2]; /* device ID */
-
- switch (value) {
- case (AMD_ID_LV400T & 0xFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV400B & 0xFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV800T & 0xFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800B & 0xFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV160T & 0xFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160B & 0xFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV320B & 0xFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection: D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[4] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (vu_char *)info->start[0];
-
- *caddr = 0xF0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
- addr[0x0AAA] = 0x80;
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char*)(info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_char*)(info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- int rc;
-
- while (cnt > 0) {
- if ((rc = write_byte(info, addr++, *src++)) != 0) {
- return (rc);
- }
- --cnt;
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte (flash_info_t *info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
- addr[0x0AAA] = 0xA0;
-
- *((vu_char *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <mpc8xx.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-# define SHOW_BOOT_PROGRESS(arg) bootstage_mark(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static ulong board_init (void);
-static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
- uchar * msg);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
- 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ID string (HERMES...)
- *
- * Return code for board revision and network speed
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board: ");
-
- if (l < 0 || strncmp(buf, "HERMES", 6)) {
- puts ("### No HW ID - assuming HERMES-PRO");
- } else {
- for (i = 0; i < l; i++) {
- if (buf[i] == ' ')
- break;
- putc (buf[i]);
- }
- }
-
- gd->board_type = board_init ();
-
- printf (" Rev. %ld.x\n", (gd->board_type >> 16));
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size, size8, size9;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh
- */
- memctl->memc_mptpr = 0x0400;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 1 to the SDRAM banks at preliminary address
- */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- /* HERMES-PRO boards have only one bank SDRAM */
-
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mamr = 0xD0802114;
- memctl->memc_mcr = 0x80002105;
- udelay (1);
- memctl->memc_mamr = 0xD0802118;
- memctl->memc_mcr = 0x80002130;
- udelay (1);
- memctl->memc_mamr = 0xD0802114;
- memctl->memc_mcr = 0x80002106;
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- udelay (10000);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define PB_LED_3 0x00020000 /* Status LED's */
-#define PB_LED_2 0x00010000
-#define PB_LED_1 0x00008000
-#define PB_LED_0 0x00004000
-
-#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
-
-#define PC_REP_SPD1 0x00000800
-#define PC_REP_SPD0 0x00000400
-
-#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */
-
-#define PB_MAI_4 0x00000010 /* Configuration */
-#define PB_MAI_3 0x00000008
-#define PB_MAI_2 0x00000004
-#define PB_MAI_1 0x00000002
-#define PB_MAI_0 0x00000001
-
-#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
-
-
-#define PC_REP_MGRPRS 0x0200
-#define PC_REP_SPD 0x0040 /* Select 100 Mbps */
-#define PC_REP_RES 0x0004
-#define PC_BIT14 0x0002 /* ??? */
-#define PC_BIT15 0x0001 /* ??? ENDSL ?? */
-
-/* ------------------------------------------------------------------------- */
-
-static ulong board_init (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- ulong reg, revision, speed = 100;
- int ethspeed;
- char *s;
-
- if ((s = getenv ("ethspeed")) != NULL) {
- if (strcmp (s, "100") == 0) {
- ethspeed = 100;
- } else if (strcmp (s, "10") == 0) {
- ethspeed = 10;
- } else {
- ethspeed = 0;
- }
- } else {
- ethspeed = 0;
- }
-
- /* Configure Port B Output Pins => 0x0003cc3F */
- reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 |
- PB_MAI_ALL;
- immr->im_cpm.cp_pbpar &= ~reg;
- immr->im_cpm.cp_pbodr &= ~reg;
- immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */
- immr->im_cpm.cp_pbdir |= reg;
-
- /* Check hardware revision */
- if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
- /*
- * Revision 3.x hardware
- */
- revision = 3;
-
- immr->im_ioport.iop_pcdat = 0x0240;
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */
- immr->im_ioport.iop_pcdat |= PC_REP_RES;
- } else {
- immr->im_ioport.iop_pcdat = 0x0002;
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */
-
- if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
- /*
- * Revision 2.x hardware: PC9 connected to PB21
- */
- revision = 2;
-
- if (ethspeed == 0) {
- /* both 10 and 100 Mbps allowed:
- * select 10 Mbps and autonegotiation
- */
- puts (" [10+100]");
- immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
- speed = 10;
- } else if (ethspeed == 10) {
- /* we are asked for 10 Mbps,
- * so select 10 Mbps
- */
- puts (" [10]");
- immr->im_cpm.cp_pbdat = 0; /* ??? */
- speed = 10;
- } else {
- /* anything else:
- * select 100 Mbps
- */
- puts (" [100]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
- /* SPD1:SPD0 = 1:1 - 100 Mbps */
- speed = 100;
- }
- immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
-
- /* must be run from RAM */
- /* start_lxt980 (speed); */
- /*************************/
- } else {
- /*
- * Revision 1.x hardware
- */
- revision = 1;
-
- immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */
-
- if (ethspeed == 0) {
- /* both 10 and 100 Mbps allowed:
- * select 100 Mbps and autonegotiation
- */
- puts (" [10+100]");
- immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
- immr->im_ioport.iop_pcdat |= PC_REP_SPD;
- } else if (ethspeed == 10) {
- /* we are asked for 10 Mbps,
- * so select 10 Mbps
- */
- puts (" [10]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */
- } else {
- /* anything else:
- * select 100 Mbps
- */
- puts (" [100]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
- /* SPD1:SPD0 = 1:1 - 100 Mbps */
- immr->im_ioport.iop_pcdat |= PC_REP_SPD;
- }
-
- immr->im_ioport.iop_pcdat |= PC_REP_RES;
- }
- }
- SHOW_BOOT_PROGRESS(BOOTSTAGE_ID_CHECK_MAGIC);
-
- return ((revision << 16) | (speed & 0xFFFF));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define SCC_SM 1 /* Index => SCC2 */
-#define PROFF PROFF_SCC2
-
-#define SMI_MSGLEN 8 /* Length of SMI Messages */
-
-#define PHYGPCR_ADDR 0x109 /* Port Enable */
-#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */
-#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */
-#define RPRESET_ADDR 0x144 /* Repeater Reset */
-
-#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */
-#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */
-#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */
-#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */
-#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Must run from RAM:
- * uses parameter RAM area which is used for stack while running from ROM
- */
-void hermes_start_lxt980 (int speed)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
- volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
- volatile cbd_t *bd;
- volatile hdlc_pram_t *hp;
- uchar smimsg[SMI_MSGLEN];
- ushort phypcrval;
- uint bd_off;
- int pnr;
-
- printf ("LXT9880: %3d Mbps\n", speed);
-
- immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */
- immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */
- immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */
- immr->im_ioport.iop_padir |= 0x4000;
-
- /* get temporary BD; no need for permanent alloc */
- bd_off = dpram_base_align (8);
-
- bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);
-
- bd->cbd_bufaddr = 0;
- bd->cbd_datlen = 0;
- bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;
-
- /* init. baudrate generator BRG4 */
- cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */
-
- cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */
- cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */
-
- /* init SCC_SM register */
- sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */
- sp->scc_todr = 0x0000;
- sp->scc_dsr = 0x7e7e;
-
- /* init. SCC_SM parameter area */
- hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];
-
- hp->tbase = bd_off; /* offset from beginning of DPRAM */
-
- hp->rfcr = 0x18;
- hp->tfcr = 0x18;
- hp->mrblr = 10;
-
- hp->c_mask = 0x0000f0b8;
- hp->c_pres = 0x0000ffff;
-
- hp->disfc = 0;
- hp->crcec = 0;
- hp->abtsc = 0;
- hp->nmarc = 0;
- hp->retrc = 0;
-
- hp->mflr = 10;
-
- hp->rfthr = 1;
-
- hp->hmask = 0;
- hp->haddr1 = 0;
- hp->haddr2 = 0;
- hp->haddr3 = 0;
- hp->haddr4 = 0;
-
- cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */
- while (cp->cp_cpcr & CPM_CR_FLG);
-
- /* clear all outstanding SCC events */
- sp->scc_scce = ~0;
-
- /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
- sp->scc_gsmrh = 0;
- sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
- SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;
-
-#if 0
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
- smimsg[3] = RPRESET_ADDR >> 4;
- smimsg[4] = 0x01;
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-#endif
-
- smimsg[0] = 0x7f; /* BROADCAST */
- smimsg[1] = 0x34; /* ASSIGN HUB ID */
- smimsg[2] = 0x00;
- smimsg[3] = 0x00;
- smimsg[4] = 0x00; /* HUB ID = 0 */
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- smimsg[0] = 0x7f; /* BROADCAST */
- smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */
- smimsg[2] = 0x00; /* ADDRESS = 0 */
- smimsg[3] = 0x00;
- smimsg[4] = 0x00; /* DATA = 0 */
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- if (speed == 100) {
- phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */
- } else {
- phypcrval = 0; /* 10 MBIT, disable autoneg. */
- }
-
- /* send MSGs */
- for (pnr = 0; pnr < 8; pnr++) {
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
- smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
- smimsg[4] = (unsigned char) (phypcrval & 0xff);
- smimsg[5] = (unsigned char) (phypcrval >> 8);
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
- }
-
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
- smimsg[3] = PHYGPCR_ADDR >> 4;
- smimsg[4] = 0xff; /* enable port 1-8 */
- smimsg[5] = 0x01; /* enable MII1 (0x01) */
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
- smimsg[3] = LEDPCR_ADDR >> 4;
- smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */
- smimsg[5] = 0xaa;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- /*
- * Disable Transmitter (so that we can free the BD, too)
- */
- sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
- uchar * msg)
-{
-#ifdef DEBUG
- unsigned hub, chip, cmd, length, addr;
-
- hub = msg[0] & 0x1F;
- chip = msg[0] >> 5;
- cmd = msg[1] & 0x1F;
- length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
- addr = (msg[2] >> 4) | (msg[3] << 4);
-
- printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
- "%02x %02x %02x %02x\n",
- hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
-#endif /* DEBUG */
-
- bd->cbd_bufaddr = (uint) msg;
- bd->cbd_datlen = SMI_MSGLEN;
- bd->cbd_sc |= BD_SC_READY;
-
- /* wait for msg transmitted */
- while ((sp->scc_scce & 0x0002) == 0);
- /* clear all events */
- sp->scc_scce = ~0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void show_boot_progress (int status)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* let things compatible */
- if (status < -BOOTSTAGE_ID_POST_FAIL_R)
- status = -1;
- status ^= 0x0F;
- status = (status & 0x0F) << 14;
- immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- board/hermes/built-in.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/lib/time.o (.text)
- arch/powerpc/lib/ticks.o (.text)
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
void set_fdt(void)
{
switch (gd->bd->bi_arch_number) {
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#ifdef CONFIG_SMC911X
/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
static const u32 gpmc_lan92xx_config[] = {
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
#ifdef CONFIG_CMD_NET
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
#endif
#if defined(CONFIG_CMD_NET)
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
--- /dev/null
+if TARGET_RPI
+
+config SYS_BOARD
+ default "rpi"
+
+config SYS_VENDOR
+ default "raspberrypi"
+
+config SYS_SOC
+ default "bcm2835"
+
+config SYS_CONFIG_NAME
+ default "rpi"
+
+endif
--- /dev/null
+RPI BOARD
+M: Stephen Warren <swarren@wwwdotorg.org>
+S: Maintained
+F: board/raspberrypi/rpi/
+F: include/configs/rpi.h
+F: configs/rpi_defconfig
--- /dev/null
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+obj-y := rpi.o
--- /dev/null
+/*
+ * (C) Copyright 2012-2013 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <asm/gpio.h>
+#include <asm/arch/mbox.h>
+#include <asm/arch/sdhci.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct bcm2835_gpio_platdata gpio_platdata = {
+ .base = BCM2835_GPIO_BASE,
+};
+
+U_BOOT_DEVICE(bcm2835_gpios) = {
+ .name = "gpio_bcm2835",
+ .platdata = &gpio_platdata,
+};
+
+struct msg_get_arm_mem {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
+ u32 end_tag;
+};
+
+struct msg_get_board_rev {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_board_rev get_board_rev;
+ u32 end_tag;
+};
+
+struct msg_get_mac_address {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_mac_address get_mac_address;
+ u32 end_tag;
+};
+
+struct msg_set_power_state {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_set_power_state set_power_state;
+ u32 end_tag;
+};
+
+struct msg_get_clock_rate {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
+ u32 end_tag;
+};
+
+/* See comments in mbox.h for data source */
+static const struct {
+ const char *name;
+ const char *fdtfile;
+} models[] = {
+ [BCM2835_BOARD_REV_B_I2C0_2] = {
+ "Model B (no P5)",
+ "bcm2835-rpi-b-i2c0.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C0_3] = {
+ "Model B (no P5)",
+ "bcm2835-rpi-b-i2c0.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_4] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_5] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_6] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_A_7] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_A_8] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_A_9] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_d] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_e] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_f] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_PLUS] = {
+ "Model B+",
+ "bcm2835-rpi-b-plus.dtb",
+ },
+ [BCM2835_BOARD_REV_CM] = {
+ "Compute Module",
+ "bcm2835-rpi-cm.dtb",
+ },
+};
+
+u32 rpi_board_rev = 0;
+
+int dram_init(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query ARM memory size\n");
+ return -1;
+ }
+
+ gd->ram_size = msg->get_arm_mem.body.resp.mem_size;
+
+ return 0;
+}
+
+static void set_fdtfile(void)
+{
+ const char *fdtfile;
+
+ if (getenv("fdtfile"))
+ return;
+
+ fdtfile = models[rpi_board_rev].fdtfile;
+ if (!fdtfile)
+ fdtfile = "bcm2835-rpi-other.dtb";
+
+ setenv("fdtfile", fdtfile);
+}
+
+static void set_usbethaddr(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
+ int ret;
+
+ if (getenv("usbethaddr"))
+ return;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query MAC address\n");
+ /* Ignore error; not critical */
+ return;
+ }
+
+ eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac);
+
+ return;
+}
+
+int misc_init_r(void)
+{
+ set_fdtfile();
+ set_usbethaddr();
+ return 0;
+}
+
+static int power_on_module(u32 module)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg_pwr);
+ BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state,
+ SET_POWER_STATE);
+ msg_pwr->set_power_state.body.req.device_id = module;
+ msg_pwr->set_power_state.body.req.state =
+ BCM2835_MBOX_SET_POWER_STATE_REQ_ON |
+ BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
+ &msg_pwr->hdr);
+ if (ret) {
+ printf("bcm2835: Could not set module %u power state\n",
+ module);
+ return -1;
+ }
+
+ return 0;
+}
+
+static void get_board_rev(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16);
+ int ret;
+ const char *name;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query board revision\n");
+ /* Ignore error; not critical */
+ return;
+ }
+
+ rpi_board_rev = msg->get_board_rev.body.resp.rev;
+ if (rpi_board_rev >= ARRAY_SIZE(models))
+ rpi_board_rev = 0;
+
+ name = models[rpi_board_rev].name;
+ if (!name)
+ name = "Unknown model";
+ printf("RPI model: %s\n", name);
+}
+
+int board_init(void)
+{
+ get_board_rev();
+
+ gd->bd->bi_boot_params = 0x100;
+
+ return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
+ int ret;
+
+ power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
+
+ BCM2835_MBOX_INIT_HDR(msg_clk);
+ BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE);
+ msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query eMMC clock rate\n");
+ return -1;
+ }
+
+ return bcm2835_sdhci_init(BCM2835_SDHCI_BASE,
+ msg_clk->get_clock_rate.body.resp.rate_hz);
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /*
+ * For now, we simply always add the simplefb DT node. Later, we
+ * should be more intelligent, and e.g. only do this if no enabled DT
+ * node exists for the "real" graphics driver.
+ */
+ lcd_dt_simplefb_add_node(blob);
+
+ return 0;
+}
+++ /dev/null
-if TARGET_RPI_B
-
-config SYS_BOARD
- default "rpi_b"
-
-config SYS_VENDOR
- default "raspberrypi"
-
-config SYS_SOC
- default "bcm2835"
-
-config SYS_CONFIG_NAME
- default "rpi_b"
-
-endif
+++ /dev/null
-RPI_B BOARD
-M: Stephen Warren <swarren@wwwdotorg.org>
-S: Maintained
-F: board/raspberrypi/rpi_b/
-F: include/configs/rpi_b.h
-F: configs/rpi_b_defconfig
+++ /dev/null
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-obj-y := rpi_b.o
+++ /dev/null
-/*
- * (C) Copyright 2012-2013 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <config.h>
-#include <dm.h>
-#include <fdt_support.h>
-#include <lcd.h>
-#include <mmc.h>
-#include <asm/gpio.h>
-#include <asm/arch/mbox.h>
-#include <asm/arch/sdhci.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct bcm2835_gpio_platdata gpio_platdata = {
- .base = BCM2835_GPIO_BASE,
-};
-
-U_BOOT_DEVICE(bcm2835_gpios) = {
- .name = "gpio_bcm2835",
- .platdata = &gpio_platdata,
-};
-
-struct msg_get_arm_mem {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
- u32 end_tag;
-};
-
-struct msg_get_mac_address {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_mac_address get_mac_address;
- u32 end_tag;
-};
-
-struct msg_set_power_state {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_set_power_state set_power_state;
- u32 end_tag;
-};
-
-struct msg_get_clock_rate {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
- u32 end_tag;
-};
-
-int dram_init(void)
-{
- ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16);
- int ret;
-
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret) {
- printf("bcm2835: Could not query ARM memory size\n");
- return -1;
- }
-
- gd->ram_size = msg->get_arm_mem.body.resp.mem_size;
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
- int ret;
-
- if (getenv("usbethaddr"))
- return 0;
-
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret) {
- printf("bcm2835: Could not query MAC address\n");
- /* Ignore error; not critical */
- return 0;
- }
-
- eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac);
-
- return 0;
-}
-
-static int power_on_module(u32 module)
-{
- ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
- int ret;
-
- BCM2835_MBOX_INIT_HDR(msg_pwr);
- BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state,
- SET_POWER_STATE);
- msg_pwr->set_power_state.body.req.device_id = module;
- msg_pwr->set_power_state.body.req.state =
- BCM2835_MBOX_SET_POWER_STATE_REQ_ON |
- BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT;
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
- &msg_pwr->hdr);
- if (ret) {
- printf("bcm2835: Could not set module %u power state\n",
- module);
- return -1;
- }
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = 0x100;
-
- return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
-}
-
-int board_mmc_init(bd_t *bis)
-{
- ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
- int ret;
-
- power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
-
- BCM2835_MBOX_INIT_HDR(msg_clk);
- BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE);
- msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr);
- if (ret) {
- printf("bcm2835: Could not query eMMC clock rate\n");
- return -1;
- }
-
- return bcm2835_sdhci_init(BCM2835_SDHCI_BASE,
- msg_clk->get_clock_rate.body.resp.rate_hz);
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /*
- * For now, we simply always add the simplefb DT node. Later, we
- * should be more intelligent, and e.g. only do this if no enabled DT
- * node exists for the "real" graphics driver.
- */
- lcd_dt_simplefb_add_node(blob);
-
- return 0;
-}
return &dpll_ddr;
}
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- omap_nand_switch_ecc(1, 8);
-
- return 0;
-}
-#endif
-
#ifndef CONFIG_SPL_BUILD
#if defined(BOARD_DFU_BUTTON_GPIO)
/*
int i, nxt = 0;
int c;
unsigned char end = 0xff;
+ unsigned char tmp;
for (i = 0; fact_get_char(i) != end; i = nxt) {
nxt = i + 1;
int pos;
int endpos;
int z;
+ int level = 0;
c = strncmp((char *)&eeprom_buf[i + 1], (char *)record,
strlen((char *)record));
/* search for "<" */
c = -1;
for (z = pos; fact_get_char(z) != end; z++) {
- if ((fact_get_char(z) == '<') ||
- (fact_get_char(z) == '>')) {
- endpos = z;
- nxt = endpos;
- c = 0;
- break;
+ if (fact_get_char(z) == '<') {
+ if (level == 0) {
+ endpos = z;
+ nxt = endpos;
+ c = 0;
+ break;
+ } else {
+ level--;
+ }
}
+ if (fact_get_char(z) == '>')
+ level++;
}
+ } else {
+ continue;
}
if (c == 0) {
/* end found -> call get_factory_val */
+ tmp = eeprom_buf[endpos];
eeprom_buf[endpos] = end;
ret = get_factory_val(&eeprom_buf[pos],
- size - pos, name, buf, len);
+ endpos - pos, name, buf, len);
/* fix buffer */
- eeprom_buf[endpos] = '<';
+ eeprom_buf[endpos] = tmp;
debug("%s: %s.%s = %s\n",
__func__, record, name, buf);
return ret;
printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
factory_dat.usb_product_id);
#endif
- if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
- (uchar *)"id", buf,
- MAX_STRING_LENGTH)) {
- if (strncmp((const char *)buf, "PXM50", 5) == 0)
- factory_dat.pxm50 = 1;
- else
- factory_dat.pxm50 = 0;
- }
- debug("PXM50: %d\n", factory_dat.pxm50);
#if defined(CONFIG_VIDEO)
if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
(uchar *)"name", factory_dat.disp_name,
NULL, 16);
debug("version number: %d\n", factory_dat.version);
}
+ /* Get ASN from factory set if available */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"id", factory_dat.asn,
+ MAX_STRING_LENGTH)) {
+ debug("factoryset asn: %s\n", factory_dat.asn);
+ } else {
+ factory_dat.asn[0] = 0;
+ }
+ /* Get COMP/ver from factory set if available */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP",
+ (uchar *)"ver",
+ factory_dat.comp_version,
+ MAX_STRING_LENGTH)) {
+ debug("factoryset COMP/ver: %s\n", factory_dat.comp_version);
+ } else {
+ strcpy((char *)factory_dat.comp_version, "1.0");
+ }
return 0;
#endif
unsigned char serial[MAX_STRING_LENGTH];
int version;
+ uchar asn[MAX_STRING_LENGTH];
+ uchar comp_version[MAX_STRING_LENGTH];
};
int factoryset_read_eeprom(int i2c_addr);
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ omap_nand_switch_ecc(1, 8);
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
return 0;
}
#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+
+ omap_nand_switch_ecc(1, 8);
+
+#ifdef CONFIG_FACTORYSET
+ if (factory_dat.asn[0] != 0) {
+ char tmp[2 * MAX_STRING_LENGTH + 2];
+
+ if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
+ factory_dat.pxm50 = 1;
+ else
+ factory_dat.pxm50 = 0;
+ sprintf(tmp, "%s_%s", factory_dat.asn,
+ factory_dat.comp_version);
+ ret = setenv("boardid", tmp);
+ if (ret)
+ printf("error setting board id\n");
+ } else {
+ factory_dat.pxm50 = 1;
+ ret = setenv("boardid", "PXM50_1.0");
+ if (ret)
+ printf("error setting board id\n");
+ }
+ debug("PXM50: %d\n", factory_dat.pxm50);
+#endif
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
return 0;
}
#endif /* ifdef CONFIG_VIDEO */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char tmp[2 * MAX_STRING_LENGTH + 2];
+
+ omap_nand_switch_ecc(1, 8);
+
+ if (factory_dat.asn[0] != 0)
+ sprintf(tmp, "%s_%s", factory_dat.asn,
+ factory_dat.comp_version);
+ else
+ sprintf(tmp, "QMX7.E38_4.0");
+
+ ret = setenv("boardid", tmp);
+ if (ret)
+ printf("error setting board id\n");
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
--- /dev/null
+if TARGET_BEAGLE_X15
+
+config SYS_BOARD
+ default "beagle_x15"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "beagle_x15"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2014
+# Texas Instruments, <www.ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <palmas.h>
+#include <sata.h>
+#include <usb.h>
+#include <asm/omap_common.h>
+#include <asm/emif.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
+#include <asm/arch/gpio.h>
+#include <environment.h>
+
+#include "mux_data.h"
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#include <cpsw.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: BeagleBoard x15\n"
+};
+
+static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
+ .dmm_lisa_map_3 = 0x80740300,
+ .is_ma_present = 0x1
+};
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+ *dmm_lisa_regs = &beagle_x15_lisa_regs;
+}
+
+static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xceef266b,
+ .sdram_tim2 = 0x328f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050001,
+ .zq_config = 0x0007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
+ .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x00800080,
+ 0x00360036,
+ 0x00340034,
+ 0x00360036,
+ 0x00350035,
+ 0x00350035,
+
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+
+ 0x00430043,
+ 0x003e003e,
+ 0x004a004a,
+ 0x00470047,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40010080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040
+};
+
+static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xceef266b,
+ .sdram_tim2 = 0x328f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050001,
+ .zq_config = 0x0007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
+ .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x00800080,
+ 0x00370037,
+ 0x00390039,
+ 0x00360036,
+ 0x00370037,
+ 0x00350035,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x00540054,
+ 0x00540054,
+ 0x004e004e,
+ 0x004c004c,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40010080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040
+};
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
+ break;
+ case 2:
+ *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+ break;
+ }
+}
+
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
+ break;
+ case 2:
+ *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
+ break;
+ }
+}
+
+struct vcores_data beagle_x15_volts = {
+ .mpu.value = VDD_MPU_DRA752,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+
+ .eve.value = VDD_EVE_DRA752,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+
+ .gpu.value = VDD_GPU_DRA752,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS45,
+ .gpu.pmic = &tps659038,
+
+ .core.value = VDD_CORE_DRA752,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS6,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA752,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS45,
+ .iva.pmic = &tps659038,
+};
+
+void hw_data_init(void)
+{
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra7xx_dplls;
+ *omap_vcores = &beagle_x15_volts;
+ *ctrl = &dra7xx_ctrl;
+}
+
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ init_sata(0);
+ /*
+ * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
+ * This is the POWERHOLD-in-Low behavior.
+ */
+ palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+ return 0;
+}
+
+static void do_set_mux32(u32 base,
+ struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+ for (i = 0; i < size; i++, pad++)
+ writel(pad->val, base + pad->offset);
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+/* Delay value to add to calibrated value */
+#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
+#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
+#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
+#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 1,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 2,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ uint32_t ctrl_val;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+ ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+ ctrl_val |= 0x22;
+ writel(ctrl_val, (*ctrl)->control_core_control_io1);
+
+ ret = cpsw_register(&cpsw_data);
+ if (ret < 0)
+ printf("Error %d registering CPSW switch\n", ret);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+int board_usb_init(int index, enum usb_init_type init)
+{
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+ OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MUX_DATA_BEAGLE_X15_H_
+#define _MUX_DATA_BEAGLE_X15_H_
+
+#include <asm/arch/mux_dra7xx.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+ {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
+ {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
+ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
+ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
+ {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
+ {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
+ {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
+ {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
+ {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
+ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
+ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
+ {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
+ {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
+ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
+ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
+ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
+ {RGMII0_TXC, (M0) },
+ {RGMII0_TXCTL, (M0) },
+ {RGMII0_TXD3, (M0) },
+ {RGMII0_TXD2, (M0) },
+ {RGMII0_TXD1, (M0) },
+ {RGMII0_TXD0, (M0) },
+ {RGMII0_RXC, (IEN | M0) },
+ {RGMII0_RXCTL, (IEN | M0) },
+ {RGMII0_RXD3, (IEN | M0) },
+ {RGMII0_RXD2, (IEN | M0) },
+ {RGMII0_RXD1, (IEN | M0) },
+ {RGMII0_RXD0, (IEN | M0) },
+ {USB1_DRVVBUS, (M0 | FSC) },
+ {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
+};
+#endif /* _MUX_DATA_BEAGLE_X15_H_ */
return 0;
}
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- return 0;
-}
-
static void do_set_mux32(u32 base,
struct pad_conf_entry const *array, int size)
{
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
- {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
- {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
{GPMC_A18, (M1)}, /* QSPI1_SCLK */
{GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
#include <asm/arch/mmc_host_def.h>
#include <asm/gpio.h>
#include <i2c.h>
+#include <twl4030.h>
#include <asm/mach-types.h>
#include <linux/mtd/nand.h>
#include "evm.h"
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
/*
* Routine: board_eth_init
{
ulong flash_size = 0;
bd_t *bd = gd->bd;
- int ok;
puts("Flash: ");
- if (board_flash_wp_on()) {
+ if (board_flash_wp_on())
printf("Uninitialized - Write Protect On\n");
- /* Since WP is on, we can't find real size. Set to 0 */
- ok = 1;
- } else {
+ else
flash_size = flash_init();
- ok = flash_size > 0;
- }
- if (!ok) {
- puts("*** failed ***\n");
-#ifdef CONFIG_PPC
- /* Why does PPC do this? */
- hang();
-#endif
- return -1;
- }
+
print_size(flash_size, "");
#ifdef CONFIG_SYS_FLASH_CHECKSUM
/*
return 0;
}
-#ifdef CONFIG_HERMES
-static int initr_hermes(void)
-{
- if ((gd->board_type >> 16) == 2)
- gd->bd->bi_ethspeed = gd->board_type & 0xFFFF;
- else
- gd->bd->bi_ethspeed = 0xFFFF;
- return 0;
-}
-
-static int initr_hermes_start(void)
-{
- if (gd->bd->bi_ethspeed != 0xFFFF)
- hermes_start_lxt980((int) gd->bd->bi_ethspeed);
- return 0;
-}
-#endif
-
#ifdef CONFIG_SC3
/* TODO: with new initcalls, move this into the driver */
extern void sc3_read_eeprom(void);
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC) || defined(CONFIG_X86)
+#if defined(CONFIG_PPC)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
#ifdef CONFIG_SC3
initr_sc3_read_eeprom,
#endif
-#ifdef CONFIG_HERMES
- initr_hermes,
-#endif
#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
mac_read_from_eeprom,
#endif
#endif
#ifdef CONFIG_MISC_INIT_R
misc_init_r, /* miscellaneous platform-dependent init */
-#endif
-#ifdef CONFIG_HERMES
- initr_hermes_start,
#endif
INIT_FUNC_WATCHDOG_RESET
#ifdef CONFIG_CMD_KGDB
initr_kgdb,
-#endif
-#ifdef CONFIG_X86
- board_early_init_r,
#endif
interrupt_init,
-#if defined(CONFIG_ARM) || defined(CONFIG_x86)
+#if defined(CONFIG_ARM)
initr_enable_interrupts,
#endif
#ifdef CONFIG_X86
print_eth(5);
#endif
-#ifdef CONFIG_HERMES
- print_mhz("ethspeed", bd->bi_ethspeed);
-#endif
printf("IP addr = %s\n", getenv("ipaddr"));
printf("baudrate = %6u bps\n", gd->baudrate);
print_num("relocaddr", gd->relocaddr);
err:
puts("ERROR\n");
- return ret;
+ return CMD_RET_FAILURE;
}
U_BOOT_CMD(
#include <dataflash.h>
#endif
#include <hash.h>
+#include <inttypes.h>
#include <watchdog.h>
#include <asm/io.h>
#include <linux/compiler.h>
if (word1 != word2) {
ulong offset = buf1 - base;
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
- printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
+ printf("%s at 0x%p (%#0*"PRIx64") != %s at 0x%p (%#0*"
+ PRIx64 ")\n",
type, (void *)(addr1 + offset), size, word1,
type, (void *)(addr2 + offset), size, word2);
#else
printf(" %08x", *((u32 *)ptr));
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
else if (size == 8)
- printf(" %016llx", *((u64 *)ptr));
+ printf(" %016" PRIx64, *((u64 *)ptr));
#endif
else if (size == 2)
printf(" %04x", *((u16 *)ptr));
*/
switch (file) {
case stdin:
- gd->jt[XF_getc] = dev->getc;
- gd->jt[XF_tstc] = dev->tstc;
+ gd->jt[XF_getc] = getc;
+ gd->jt[XF_tstc] = tstc;
break;
case stdout:
- gd->jt[XF_putc] = dev->putc;
- gd->jt[XF_puts] = dev->puts;
+ gd->jt[XF_putc] = putc;
+ gd->jt[XF_puts] = puts;
gd->jt[XF_printf] = printf;
break;
}
*/
#include <common.h>
+#include <inttypes.h>
#include <stdio_dev.h>
#include <linux/ctype.h>
#include <linux/types.h>
int n)
{
int i;
- int address_len = fdt_address_cells(fdt, 0);
- int size_len = fdt_size_cells(fdt, 0);
+ int address_cells = fdt_address_cells(fdt, 0);
+ int size_cells = fdt_size_cells(fdt, 0);
char *p = buf;
for (i = 0; i < n; i++) {
- if (address_len == 2)
+ if (address_cells == 2)
*(fdt64_t *)p = cpu_to_fdt64(address[i]);
else
*(fdt32_t *)p = cpu_to_fdt32(address[i]);
- p += address_len;
+ p += 4 * address_cells;
- if (size_len == 2)
+ if (size_cells == 2)
*(fdt64_t *)p = cpu_to_fdt64(size[i]);
else
*(fdt32_t *)p = cpu_to_fdt32(size[i]);
- p += size_len;
+ p += 4 * size_cells;
}
return p - (char *)buf;
fdt_delprop(blob, off, alias);
}
-#define PRu64 "%llx"
-
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR ((u64)-1)
s = of_read_number(range + na + pna, ns);
da = of_read_number(addr, na);
- debug("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n",
- cp, s, da);
+ debug("OF: default map, cp=%" PRIu64 ", s=%" PRIu64
+ ", da=%" PRIu64 "\n", cp, s, da);
if (da < cp || da >= (cp + s))
return OF_BAD_ADDR;
finish:
of_dump_addr("OF: parent translation for:", addr, pna);
- debug("OF: with offset: "PRu64"\n", offset);
+ debug("OF: with offset: %" PRIu64 "\n", offset);
/* Translate it into parent bus space */
return pbus->translate(addr, offset, pna);
dt_addr = fdt_translate_address(fdt, node, reg);
if (addr != dt_addr) {
- printf("Warning: U-Boot configured device %s at address %llx,\n"
- " but the device tree has it address %llx.\n",
- alias, addr, dt_addr);
+ printf("Warning: U-Boot configured device %s at address %"
+ PRIx64 ",\n but the device tree has it address %"
+ PRIx64 ".\n", alias, addr, dt_addr);
return 0;
}
int fdt_noffset;
#endif
const char *select = NULL;
+ int ok_no_fdt = 0;
*of_flat_tree = NULL;
*of_size = 0;
fdt_addr);
fdt_hdr = image_get_fdt(fdt_addr);
if (!fdt_hdr)
- goto error;
+ goto no_fdt;
/*
* move image data to the load address,
break;
default:
puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
printf(" Booting using the fdt blob at %#08lx\n", fdt_addr);
}
} else {
debug("## No Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
} else {
debug("## No Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
*of_flat_tree = fdt_blob;
return 0;
+no_fdt:
+ ok_no_fdt = 1;
error:
*of_flat_tree = NULL;
*of_size = 0;
+ if (!select && ok_no_fdt) {
+ debug("Continuing to boot without FDT\n");
+ return 0;
+ }
return 1;
}
lcd_ctrl_init(lcdbase);
/*
- * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi_b) ignores
+ * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi) ignores
* the 'lcdbase' argument and uses custom lcd base address
* by setting up gd->fb_base. Check for this condition and fixup
* 'lcd_base' address.
DECLARE_GLOBAL_DATA_PTR;
-static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector)
+static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
{
unsigned long err;
u32 image_size_sectors;
return (err == 0);
}
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
+{
+ disk_partition_t info;
+
+ if (get_partition_info(&mmc->block_dev, partition, &info)) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("spl: partition error\n");
+#endif
+ return -1;
+ }
+
+ return mmc_load_image_raw_sector(mmc, info.start);
+}
+#endif
+
#ifdef CONFIG_SPL_OS_BOOT
static int mmc_load_image_raw_os(struct mmc *mmc)
{
return -1;
}
- return mmc_load_image_raw(mmc, CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
+ return mmc_load_image_raw_sector(mmc,
+ CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
}
#endif
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
#endif
- err = mmc_load_image_raw(mmc,
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+ err = mmc_load_image_raw_partition(mmc,
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
+#else
+ err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+#endif
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
- } else if (boot_mode == MMCSD_MODE_FS) {
+ }
+ if (err || boot_mode == MMCSD_MODE_FS) {
debug("boot mode - FS\n");
#ifdef CONFIG_SPL_FAT_SUPPORT
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION))
#endif
err = spl_load_image_fat(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
if(err)
#endif /* CONFIG_SPL_FAT_SUPPORT */
#ifdef CONFIG_SPL_EXT_SUPPORT
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION))
#endif
err = spl_load_image_ext(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
#endif /* CONFIG_SPL_EXT_SUPPORT */
}
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
#endif
- err = mmc_load_image_raw(mmc,
+ err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
#endif
} else {
#include <linux/ctype.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
-#include <compiler.h>
#include <errno.h>
#include <usb.h>
#ifdef CONFIG_4xx
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
++S:CONFIG_ARM=y
++S:CONFIG_OMAP54XX=y
++S:CONFIG_TARGET_BEAGLE_X15=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_HERMES=y
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_LD4=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_PRO4=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_SLD8=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_RPI_B=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_RPI=y
#include <common.h>
#include <command.h>
#include <ide.h>
+#include <inttypes.h>
#include <malloc.h>
#include <part_efi.h>
#include <linux/ctype.h>
/* Check that the my_lba entry points to the LBA that contains the GPT */
if (le64_to_cpu(pgpt_head->my_lba) != lba) {
- printf("GPT: my_lba incorrect: %llX != %llX\n",
- le64_to_cpu(pgpt_head->my_lba),
- lba);
+ printf("GPT: my_lba incorrect: %llX != %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->my_lba),
+ lba);
return 0;
}
/* Check the first_usable_lba and last_usable_lba are within the disk. */
lastlba = (u64)dev_desc->lba;
if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) {
- printf("GPT: first_usable_lba incorrect: %llX > %llX\n",
- le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
+ printf("GPT: first_usable_lba incorrect: %llX > %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
return 0;
}
if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) {
- printf("GPT: last_usable_lba incorrect: %llX > %llX\n",
- le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
+ printf("GPT: last_usable_lba incorrect: %llX > %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
return 0;
}
- debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %llX\n",
- le64_to_cpu(pgpt_head->first_usable_lba),
- le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
+ debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %"
+ PRIX64 "\n", le64_to_cpu(pgpt_head->first_usable_lba),
+ le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
/* Read and allocate Partition Table Entries */
*pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
To compile U-Boot with clang on linux without IAS use e.g.:
export TRIPLET=arm-linux-gnueabi && export CROSS_COMPILE="$TRIPLET-"
-make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_b_defconfig
+make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_defconfig
make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" all V=1 -j8
FreeBSD 11 (Current):
# The following commands compile U-Boot using the clang xdev toolchain.
# NOTE: CROSS_COMPILE and target differ on purpose!
export CROSS_COMPILE=arm-gnueabi-freebsd-
-gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_b_defconfig
+gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_defconfig
gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8
Given that u-boot will default to gcc, above commands can be
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-PRS200 powerpc mpc5200 - -
-MCC200 powerpc mpc5200 - -
+hermes powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+PRS200 powerpc mpc5200 ecfdcee 2014-11-12
+MCC200 powerpc mpc5200 ecfdcee 2014-11-12
TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
--- /dev/null
+Intel Pantherpoint SATA Device Binding
+======================================
+
+The device tree node which describes the operation of the Intel Pantherpoint
+SATA device is as follows:
+
+Required properties :
+- compatible = "intel,pantherpoint-ahci"
+- intel,sata-mode : string, one of:
+ "ahci" : Use AHCI mode (default)
+ "combined" : Use combined IDE + legacy mode
+ "plain-ide" : Use plain IDE mode
+- intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
+ bit 1=enable second port, etc.
+- intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
+- intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
+
+Example
+-------
+
+sata {
+ compatible = "intel,pantherpoint-ahci";
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+};
Required properties :
- compatible = "intel,lpc"
-- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
- pairs can be provided - the first of each pair is the base address and
+- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the
+ ALT_GP_SMI_EN register
+- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four
+ cell pairs can be provided - the first of each pair is the base address and
the second is the size. These are written into the GENx_DEC registers of
the LPC device
+- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid
+ values are:
+ 0 No effect (default)
+ 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ 2 SCI (if corresponding GPIO_EN bit is also set)
+- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
+ one cell for each.
+ 0x00 - 0000 = Reserved
+ 0x01 - 0001 = Reserved
+ 0x02 - 0010 = Reserved
+ 0x03 - 0011 = IRQ3
+ 0x04 - 0100 = IRQ4
+ 0x05 - 0101 = IRQ5
+ 0x06 - 0110 = IRQ6
+ 0x07 - 0111 = IRQ7
+ 0x08 - 1000 = Reserved
+ 0x09 - 1001 = IRQ9
+ 0x0A - 1010 = IRQ10
+ 0x0B - 1011 = IRQ11
+ 0x0C - 1100 = IRQ12
+ 0x0D - 1101 = Reserved
+ 0x0E - 1110 = IRQ14
+ 0x0F - 1111 = IRQ15
+ PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ 0x80 - The PIRQ is not routed.
Example
compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+
+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+ 0x80 0x80 0x80 0x80>;
+ /*
+ * GPI routing
+ * 0 No effect (default)
+ * 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is
+ * also set)
+ * 2 SCI (if corresponding GPIO_EN bit is also set)
+ */
+ intel,gpi-routing = <0 0 0 0 0 0 0 2
+ 1 0 0 0 0 0 0 0>;
+ /* Enable EC SMI source */
+ intel,alt-gp-smi-enable = <0x0100>;
};
--- /dev/null
+Intel GMA Bindings
+==================
+
+This is the Intel Graphics Media Accelerator. This binding supports selection
+of display parameters only.
+
+
+Required properties:
+ - compatible : "intel,gma";
+
+Optional properties:
+ - intel,dp-hotplug : values for digital port hotplug, one cell per value for
+ ports B, C and D
+ - intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D
+ - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
+
+ The following delays are in units of 0.1ms:
+ - intel,panel-power-up-delay : T1+T2 time sequence
+ - intel,panel-power-down-delay : T3 time sequence
+ - intel,panel-power-backlight-on-delay : T5 time sequence
+ - intel,panel-power-backlight-off-delay : Tx time sequence
+
+ - intel,cpu-backlight : Value for CPU Backlight PWM
+ - intel,pch-backlight : Value for PCH Backlight PWM
+
+Example
+-------
+
+gma {
+ compatible = "intel,gma";
+ intel,dp_hotplug = <0 0 0x06>;
+ intel,panel-port-select = <1>;
+ intel,panel-power-cycle-delay = <6>;
+ intel,panel-power-up-delay = <2000>;
+ intel,panel-power-down-delay = <500>;
+ intel,panel-power-backlight-on-delay = <2000>;
+ intel,panel-power-backlight-off-delay = <2000>;
+ intel,cpu-backlight = <0x00000200>;
+ intel,pch-backlight = <0x04000000>;
+};
alias abiessmann Andreas Bießmann <andreas.devel@googlemail.com>
alias afleming Andy Fleming <afleming@gmail.com>
alias ag Anatolij Gustschin <agust@denx.de>
+alias alisonwang Alison Wang <alison.wang@freescale.com>
+alias angelo_ts Angelo Dureghello <angelo@sysam.it>
+alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
alias galak Kumar Gala <galak@kernel.crashing.org>
alias gruss Graeme Russ <graeme.russ@gmail.com>
alias hs Heiko Schocher <hs@denx.de>
alias bfin uboot, vapier, sonic
alias blackfin bfin
-alias m68k uboot, jasonjin
+alias m68k uboot, alisonwang, angelo_ts
alias coldfire m68k
alias microblaze uboot, monstr
alias mb microblaze
-alias mips uboot, Shinya Kuribayashi <skuribay@pobox.com>
+alias mips uboot, danielschwierzeck
alias nds32 uboot, macpaul
alias nand uboot, scottwood
alias net uboot, jhersh
alias spi uboot, jagan
+alias ubi uboot, hs
alias usb uboot, marex
alias video uboot, ag
alias patman uboot, sjg
$(X86DIR)/debug.o
ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \
- -D__PPC__ -D__BIG_ENDIAN__
+ $(if $(CONFIG_PPC),-D__PPC__ -D__BIG_ENDIAN__)
* BIOS in u-boot.
****************************************************************************/
#include <common.h>
-#include "biosemui.h"
+#include <bios_emul.h>
+#include <errno.h>
#include <malloc.h>
+#include <vbe.h>
+#include "biosemui.h"
/* Length of the BIOS image */
#define MAX_BIOSLEN (128 * 1024L)
static u32 saveBaseAddress18;
static u32 saveBaseAddress20;
+static void atibios_set_vesa_mode(RMREGS *regs, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ debug("VBE: Setting VESA mode %#04x\n", vesa_mode);
+ /* request linear framebuffer mode */
+ vesa_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ vesa_mode &= ~(1 << 15);
+ regs->e.eax = VESA_SET_MODE;
+ regs->e.ebx = vesa_mode;
+ BE_int86(0x10, regs, regs);
+
+ int offset = 0x2000;
+ void *buffer = (void *)(M.mem_base + offset);
+
+ u16 buffer_seg = (((unsigned long)offset) >> 4) & 0xff00;
+ u16 buffer_adr = ((unsigned long)offset) & 0xffff;
+ regs->e.eax = VESA_GET_MODE_INFO;
+ regs->e.ebx = 0;
+ regs->e.ecx = vesa_mode;
+ regs->e.edx = 0;
+ regs->e.esi = buffer_seg;
+ regs->e.edi = buffer_adr;
+ BE_int86(0x10, regs, regs);
+ memcpy(mode_info->mode_info_block, buffer,
+ sizeof(struct vbe_mode_info));
+ mode_info->valid = true;
+
+ vesa_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ vesa_mode &= ~(1 << 15);
+ regs->e.eax = VESA_SET_MODE;
+ regs->e.ebx = vesa_mode;
+ BE_int86(0x10, regs, regs);
+}
+
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus to boot
-VGAInfo - BIOS emulator VGA info structure
+vga_info - BIOS emulator VGA info structure
REMARKS:
This function executes the BIOS POST code on the controller. We assume that
at this stage the controller has its I/O and memory space enabled and
that all other controllers are in a disabled state.
****************************************************************************/
-static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
+static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
+ int vesa_mode, struct vbe_mode_info *mode_info)
{
RMREGS regs;
RMSREGS sregs;
((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
/*Setup the X86 emulator for the VGA BIOS*/
- BE_setVGA(VGAInfo);
+ BE_setVGA(vga_info);
/*Execute the BIOS POST code*/
BE_callRealMode(0xC000, 0x0003, ®s, &sregs);
/*Cleanup and exit*/
- BE_getVGA(VGAInfo);
+ BE_getVGA(vga_info);
+
+ if (vesa_mode != -1)
+ atibios_set_vesa_mode(®s, vesa_mode, mode_info);
}
/****************************************************************************
Loads and POST's the display controllers BIOS, directly from the BIOS
image we can extract over the PCI bus.
****************************************************************************/
-static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
+static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int vesa_mode,
+ struct vbe_mode_info *mode_info)
{
- u32 BIOSImageLen;
- uchar *mappedBIOS;
- uchar *copyOfBIOS;
-
- /*Allocate memory to store copy of BIOS from display controller*/
- if ((mappedBIOS = PCI_mapBIOSImage(pcidev)) == NULL) {
- printf("videoboot: Video ROM failed to map!\n");
- return false;
- }
+ u32 bios_image_len;
+ uchar *mapped_bios;
+ uchar *copy_of_bios;
+
+ if (bios_rom) {
+ copy_of_bios = bios_rom;
+ bios_image_len = bios_len;
+ } else {
+ /*
+ * Allocate memory to store copy of BIOS from display
+ * controller
+ */
+ mapped_bios = PCI_mapBIOSImage(pcidev);
+ if (mapped_bios == NULL) {
+ printf("videoboot: Video ROM failed to map!\n");
+ return false;
+ }
- BIOSImageLen = mappedBIOS[2] * 512;
+ bios_image_len = mapped_bios[2] * 512;
- if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) {
- printf("videoboot: Out of memory!\n");
- return false;
+ copy_of_bios = malloc(bios_image_len);
+ if (copy_of_bios == NULL) {
+ printf("videoboot: Out of memory!\n");
+ return false;
+ }
+ memcpy(copy_of_bios, mapped_bios, bios_image_len);
+ PCI_unmapBIOSImage(pcidev, mapped_bios);
}
- memcpy(copyOfBIOS, mappedBIOS, BIOSImageLen);
- PCI_unmapBIOSImage(pcidev, mappedBIOS);
-
- /*Save information in VGAInfo structure*/
- VGAInfo->function = PCI_FUNC(pcidev);
- VGAInfo->device = PCI_DEV(pcidev);
- VGAInfo->bus = PCI_BUS(pcidev);
- VGAInfo->pcidev = pcidev;
- VGAInfo->BIOSImage = copyOfBIOS;
- VGAInfo->BIOSImageLen = BIOSImageLen;
+ /*Save information in vga_info structure*/
+ vga_info->function = PCI_FUNC(pcidev);
+ vga_info->device = PCI_DEV(pcidev);
+ vga_info->bus = PCI_BUS(pcidev);
+ vga_info->pcidev = pcidev;
+ vga_info->BIOSImage = copy_of_bios;
+ vga_info->BIOSImageLen = bios_image_len;
/*Now execute the BIOS POST for the device*/
- if (copyOfBIOS[0] != 0x55 || copyOfBIOS[1] != 0xAA) {
+ if (copy_of_bios[0] != 0x55 || copy_of_bios[1] != 0xAA) {
printf("videoboot: Video ROM image is invalid!\n");
return false;
}
- PCI_doBIOSPOST(pcidev, VGAInfo);
+ PCI_doBIOSPOST(pcidev, vga_info, vesa_mode, mode_info);
/*Reset the size of the BIOS image to the final size*/
- VGAInfo->BIOSImageLen = copyOfBIOS[2] * 512;
+ vga_info->BIOSImageLen = copy_of_bios[2] * 512;
return true;
}
-/****************************************************************************
-PARAMETERS:
-pcidev - PCI device info for the video card on the bus to boot
-pVGAInfo - Place to return VGA info structure is requested
-cleanUp - true to clean up on exit, false to leave emulator active
-
-REMARKS:
-Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
-and the X86 BIOS emulator module.
-****************************************************************************/
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp)
+int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop)
{
BE_VGAInfo *VGAInfo;
/*Initialise the x86 BIOS emulator*/
if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
printf("videoboot: Out of memory!\n");
- return false;
+ return -ENOMEM;
}
memset(VGAInfo, 0, sizeof(*VGAInfo));
BE_init(0, 65536, VGAInfo, 0);
+ *vga_infop = VGAInfo;
- /*Post all the display controller BIOS'es*/
- if (!PCI_postController(pcidev, VGAInfo))
- return false;
+ return 0;
+}
- /*Cleanup and exit the emulator if requested. If the BIOS emulator
- is needed after booting the card, we will not call BE_exit and
- leave it enabled for further use (ie: VESA driver etc).
+void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void))
+{
+ X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func);
+}
+
+int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ /*Post all the display controller BIOS'es*/
+ if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info,
+ vesa_mode, mode_info))
+ return -EINVAL;
+
+ /*
+ * Cleanup and exit the emulator if requested. If the BIOS emulator
+ * is needed after booting the card, we will not call BE_exit and
+ * leave it enabled for further use (ie: VESA driver etc).
*/
- if (cleanUp) {
+ if (clean_up) {
BE_exit();
- if (VGAInfo->BIOSImage)
- free(VGAInfo->BIOSImage);
- free(VGAInfo);
- VGAInfo = NULL;
+ if (vga_info->BIOSImage)
+ free(vga_info->BIOSImage);
+ free(vga_info);
+ vga_info = NULL;
}
- /*Return VGA info pointer if the caller requested it*/
+
+ return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+pcidev - PCI device info for the video card on the bus to boot
+pVGAInfo - Place to return VGA info structure is requested
+cleanUp - true to clean up on exit, false to leave emulator active
+
+REMARKS:
+Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
+and the X86 BIOS emulator module.
+****************************************************************************/
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up)
+{
+ BE_VGAInfo *VGAInfo;
+ int ret;
+
+ ret = biosemu_setup(pcidev, &VGAInfo);
+ if (ret)
+ return false;
+ ret = biosemu_run(pcidev, NULL, 0, VGAInfo, clean_up, -1, NULL);
+ if (ret)
+ return false;
+
+ /* Return VGA info pointer if the caller requested it*/
if (pVGAInfo)
*pVGAInfo = VGAInfo;
+
return true;
}
/*------------------------- Global Variables ------------------------------*/
-#ifndef __i386__
+#ifndef CONFIG_X86EMU_RAW_IO
static char *BE_biosDate = "08/14/99";
static u8 BE_model = 0xFC;
static u8 BE_submodel = 0x00;
#endif
+#undef DEBUG_IO_ACCESS
+
+#ifdef DEBUG_IO_ACCESS
+#define debug_io(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define debug_io(x, b...)
+#endif
+
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
return (u8*)(_BE_env.biosmem_base + addr - 0xC0000);
} else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) {
- DB(printf("BE_memaddr: address %#lx may be invalid!\n", addr);)
- return M.mem_base;
+ DB(printf("BE_memaddr: address %#lx may be invalid!\n",
+ (ulong)addr);)
+ return (u8 *)M.mem_base;
} else if (addr >= 0xA0000 && addr <= 0xBFFFF) {
return (u8*)(_BE_env.busmem_base + addr - 0xA0000);
}
-#ifdef __i386__
+#ifdef CONFIG_X86EMU_RAW_IO
else if (addr >= 0xD0000 && addr <= 0xFFFFF) {
/* We map the real System BIOS directly on real PC's */
- DB(printf("BE_memaddr: System BIOS address %#lx\n", addr);)
- return _BE_env.busmem_base + addr - 0xA0000;
+ DB(printf("BE_memaddr: System BIOS address %#lx\n",
+ (ulong)addr);)
+ return (u8 *)_BE_env.busmem_base + addr - 0xA0000;
}
#else
else if (addr >= 0xFFFF5 && addr < 0xFFFFE) {
/* Return a faked BIOS date string for non-x86 machines */
- DB(printf("BE_memaddr - Returning BIOS date\n");)
+ debug_io("BE_memaddr - Returning BIOS date\n");
return (u8 *)(BE_biosDate + addr - 0xFFFF5);
} else if (addr == 0xFFFFE) {
/* Return system model identifier for non-x86 machines */
- DB(printf("BE_memaddr - Returning model\n");)
+ debug_io("BE_memaddr - Returning model\n");
return &BE_model;
} else if (addr == 0xFFFFF) {
/* Return system submodel identifier for non-x86 machines */
- DB(printf("BE_memaddr - Returning submodel\n");)
+ debug_io("BE_memaddr - Returning submodel\n");
return &BE_submodel;
}
#endif
else if (addr > M.mem_size - 1) {
HALT_SYS();
- return M.mem_base;
+ return (u8 *)M.mem_base;
}
- return M.mem_base + addr;
+ return (u8 *)(M.mem_base + addr);
}
/****************************************************************************
}
}
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
/* For Non-Intel machines we may need to emulate some I/O port accesses that
* the BIOS may try to access, such as the PCI config registers.
{
u8 val = 0xff;
+ debug_io("vga_inb.%04X -> ", (u16) port);
switch (port) {
case 0x3C0:
/* 3C0 has funky characteristics because it can act as either
{
u8 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_VGA_PORT(port)){
/*seems reading port 0x3c3 return the high 16 bit of io port*/
if(port == 0x3c3)
val = LOG_inpb(port);
} else
#endif
+ {
+ debug_io("inb.%04X -> ", (u16) port);
val = LOG_inpb(port);
+ debug_io("%02X\n", val);
+ }
+
return val;
}
{
u16 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_WORD);
else if (port < 0x100) {
val = LOG_inpw(port);
} else
#endif
+ {
+ debug_io("inw.%04X -> ", (u16) port);
val = LOG_inpw(port);
+ debug_io("%04X\n", val);
+ }
+
return val;
}
{
u32 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_DWORD);
else if (port < 0x100) {
val = LOG_inpd(port);
} else
#endif
+ {
+ debug_io("inl.%04X -> ", (u16) port);
val = LOG_inpd(port);
+ debug_io("%08X\n", val);
+ }
+
return val;
}
****************************************************************************/
void X86API BE_outb(X86EMU_pioAddr port, u8 val)
{
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_VGA_PORT(port))
VGA_outpb(port, val);
else if (IS_TIMER_PORT(port))
LOG_outpb(port, val);
} else
#endif
+ {
+ debug_io("outb.%04X <- %02X", (u16) port, val);
LOG_outpb(port, val);
+ debug_io("\n");
+ }
}
/****************************************************************************
****************************************************************************/
void X86API BE_outw(X86EMU_pioAddr port, u16 val)
{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_VGA_PORT(port)) {
- VGA_outpb(port, val);
- VGA_outpb(port + 1, val >> 8);
- } else if (IS_PCI_PORT(port))
- PCI_outp(port, val, REG_WRITE_WORD);
- else if (port < 0x100) {
- DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16) port,
- val);)
- LOG_outpw(port, val);
- } else
+#if !defined(CONFIG_X86EMU_RAW_IO)
+ if (IS_VGA_PORT(port)) {
+ VGA_outpb(port, val);
+ VGA_outpb(port + 1, val >> 8);
+ } else if (IS_PCI_PORT(port)) {
+ PCI_outp(port, val, REG_WRITE_WORD);
+ } else if (port < 0x100) {
+ DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16)port,
+ val);)
+ LOG_outpw(port, val);
+ } else
#endif
- LOG_outpw(port, val);
+ {
+ debug_io("outw.%04X <- %04X", (u16) port, val);
+ LOG_outpw(port, val);
+ debug_io("\n");
+ }
}
/****************************************************************************
****************************************************************************/
void X86API BE_outl(X86EMU_pioAddr port, u32 val)
{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_PCI_PORT(port))
+#if !defined(CONFIG_X86EMU_RAW_IO)
+ if (IS_PCI_PORT(port)) {
PCI_outp(port, val, REG_WRITE_DWORD);
- else if (port < 0x100) {
+ } else if (port < 0x100) {
DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);)
LOG_outpd(port, val);
} else
#endif
+ {
+ debug_io("outl.%04X <- %08X", (u16) port, val);
LOG_outpd(port, val);
+ debug_io("\n");
+ }
}
PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8) ~ 0x02);
return;
}
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
else {
printf("int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",
M.x86.R_AL);
}
#endif
}
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
else {
printf("int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",
M.x86.R_AH, M.x86.R_AL, M.x86.R_BL);
#include <asm/io.h>
/*---------------------- Macros and type definitions ----------------------*/
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define DB(x) x
#else
#define DB(x) do{}while(0);
#ifndef __BIOSEMU_H
#define __BIOSEMU_H
+#include <bios_emul.h>
+
#ifdef __KERNEL__
#include "x86emu.h"
#else
#pragma pack(1)
-#ifndef __KERNEL__
-/****************************************************************************
-REMARKS:
-Data structure used to describe the details specific to a particular VGA
-controller. This information is used to allow the VGA controller to be
-swapped on the fly within the BIOS emulator.
-
-HEADER:
-biosemu.h
-
-MEMBERS:
-pciInfo - PCI device information block for the controller
-BIOSImage - Pointer to a read/write copy of the BIOS image
-BIOSImageLen - Length of the BIOS image
-LowMem - Copy of key low memory areas
-****************************************************************************/
-typedef struct {
- PCIDeviceInfo *pciInfo;
- void *BIOSImage;
- ulong BIOSImageLen;
- uchar LowMem[1536];
-} BE_VGAInfo;
-#else
-/****************************************************************************
-REMARKS:
-Data structure used to describe the details for the BIOS emulator system
-environment as used by the X86 emulator library.
-
-HEADER:
-biosemu.h
-
-MEMBERS:
-vgaInfo - VGA BIOS information structure
-biosmem_base - Base of the BIOS image
-biosmem_limit - Limit of the BIOS image
-busmem_base - Base of the VGA bus memory
-****************************************************************************/
-typedef struct {
- int function;
- int device;
- int bus;
- u32 VendorID;
- u32 DeviceID;
- pci_dev_t pcidev;
- void *BIOSImage;
- u32 BIOSImageLen;
- u8 LowMem[1536];
-} BE_VGAInfo;
-
-#endif /* __KERNEL__ */
-
#define CRT_C 24 /* 24 CRT Controller Registers */
#define ATT_C 21 /* 21 Attribute Controller Registers */
#define GRA_C 9 /* 9 Graphics Controller Registers */
/*---------------------- Macros and type definitions ----------------------*/
-#if defined (CONFIG_ARM)
+#if defined(CONFIG_ARM)
#define GAS_LINE_COMMENT "@"
-#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_X86)
#define GAS_LINE_COMMENT "#"
#elif defined (CONFIG_SH)
#define GAS_LINE_COMMENT "!"
void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs);
void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs);
void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]);
+ void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func);
void X86EMU_prepareForInt(int num);
/* decode.c */
void X86EMU_exec(void);
void X86EMU_halt_sys(void);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define HALT_SYS() \
printf("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \
X86EMU_halt_sys()
#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */
#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F)
# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F)
# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F)
# define CHECK_DATA_ACCESS()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F)
# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F)
# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F)
# define DEBUG_DECODE_NOPRINT() 0
#endif
-#ifdef DEBUG
+# define ERR_PRINTF(x) printf(x)
+# define ERR_PRINTF2(x, y) printf(x, y)
+
+#ifdef CONFIG_X86EMU_DEBUG103
+
# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \
x86emu_decode_printf(x)
# define SAVE_IP_CS(x,y)
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define TRACE_REGS() \
if (DEBUG_DISASSEMBLE()) { \
x86emu_just_disassemble(); \
# define TRACE_REGS()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step()
#else
# define SINGLE_STEP()
TRACE_REGS(); \
SINGLE_STEP()
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define START_OF_INSTR()
# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr();
# define END_OF_INSTR_NO_TRACE() x86emu_end_instr();
# define END_OF_INSTR_NO_TRACE()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define CALL_TRACE(u,v,w,x,s) \
if (DEBUG_TRACECALLREGS()) \
x86emu_dump_regs(); \
# define RETURN_TRACE(n,u,v)
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define DB(x) x
#else
#define DB(x)
u8 intno;
volatile int intr; /* mask of pending interrupts */
int debug;
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
int check;
u16 saved_ip;
u16 saved_cs;
/*----------------------------- Implementation ----------------------------*/
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static void print_encoded_bytes(u16 s, u16 o);
static void print_decoded_instruction(void);
u32 start = off & 0xfffffff0;
u32 end = (off + 16) & 0xfffffff0;
u32 i;
- u32 current;
- current = start;
while (end <= off + amt) {
printk("%04x:%04x ", seg, start);
for (i = start; i < off; i++)
void x86emu_single_step(void)
{
char s[1024];
- int ps[10];
+ int ps[10];
int ntok;
int cmd;
int done;
static int breakpoint;
static int noDecode = 1;
- char *p;
-
if (DEBUG_BREAK()) {
if (M.x86.saved_ip != breakpoint) {
return;
offset = M.x86.saved_ip;
while (!done) {
printk("-");
+ ps[1] = 0; /* Avoid dodgy compiler warnings */
+ ps[2] = 0;
cmd = x86emu_parse_line(s, ps, &ntok);
switch (cmd) {
case 'u':
u8 fetch_data_byte(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
u16 fetch_data_word(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
u32 fetch_data_long(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
uint offset,
u8 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
uint offset,
u16 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
uint offset,
u32 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
uint offset,
u8 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
uint offset,
u16 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
uint offset,
u32 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
/* constant arrays to do several instructions in just one function */
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static char *x86emu_GenOpName[8] = {
"ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"};
#endif
sar_long,
};
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static char *opF6_names[8] =
{ "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" };
{
START_OF_INSTR();
if (M.x86.R_SP != 0) {
- DECODE_PRINTF("ILLEGAL X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL X86 OPCODE\n");
TRACE_REGS();
DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n",
M.x86.R_CS, M.x86.R_IP-1,op1));
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
DECODE_PRINTF("POP\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
HALT_SYS();
}
if (mod < 3) {
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
HALT_SYS();
}
if (mod < 3) {
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
HALT_SYS();
}
if (mod < 3) {
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
DECODE_PRINTF("AAM\n");
a = fetch_byte_imm(); /* this is a stupid encoding. */
if (a != 10) {
- DECODE_PRINTF("ERROR DECODING AAM\n");
+ ERR_PRINTF("ERROR DECODING AAM\n");
TRACE_REGS();
HALT_SYS();
}
test_byte(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
test_byte(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
test_long(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
HALT_SYS();
break;
case 2:
test_word(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
HALT_SYS();
break;
case 2:
test_long(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
test_word(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
/* Yet another special case instruction. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
case 5:
case 6:
case 7:
- DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod);
+ ERR_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x\n", mod);
HALT_SYS();
break;
}
/* Yet another special case instruction. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
DECODE_PRINTF("PUSH\t");
break;
case 7:
- DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
+ ERR_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
HALT_SYS();
break;
}
M.x86.R_IP = *destreg;
break;
case 3: /* jmp far ptr ... */
- DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+ ERR_PRINTF("OPERATION UNDEFINED 0XFF\n");
TRACE_AND_STEP();
HALT_SYS();
break;
M.x86.R_IP = (u16) (*destreg);
break;
case 5: /* jmp far ptr ... */
- DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+ ERR_PRINTF("OPERATION UNDEFINED 0XFF\n");
TRACE_AND_STEP();
HALT_SYS();
break;
u8 op2)
{
START_OF_INSTR();
- DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
TRACE_REGS();
printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
M.x86.R_CS, M.x86.R_IP-2,op2);
DECODE_PRINTF("BTC\t");
break;
default:
- DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
TRACE_REGS();
printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl);
sys_outl = funcs->outl;
}
+void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func)
+{
+ _X86EMU_intrTab[intnum] = func;
+}
+
/****************************************************************************
PARAMETERS:
funcs - New interrupt vector table to make active
#define DRV_NAME "pata-bfin"
#define DRV_VERSION "0.9"
-#define __iomem
#define ATA_REG_CTRL 0x0E
#define ATA_REG_ALTSTATUS ATA_REG_CTRL
return 0;
}
-static int i2c_mux_disconnet_all(void)
+static int i2c_mux_disconnect_all(void)
{
struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
int i;
- uint8_t buf;
+ uint8_t buf = 0;
if (I2C_ADAP->init_done == 0)
return 0;
ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1);
if (ret != 0) {
- printf("i2c: mux diconnect error\n");
+ printf("i2c: mux disconnect error\n");
return ret;
}
} while (i > 0);
}
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
- i2c_mux_disconnet_all();
+ i2c_mux_disconnect_all();
#endif
gd->cur_i2c_bus = bus;
}
#endif
+/* board-specific MMC power initializations. */
+__weak void board_mmc_power_init(void)
+{
+}
+
int mmc_start_init(struct mmc *mmc)
{
int err;
if (mmc->has_init)
return 0;
+ board_mmc_power_init();
+
/* made sure it's not NULL earlier */
err = mmc->cfg->ops->init(mmc);
pbias_lite = readl(&t2_base->pbias_lite);
pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
writel(pbias_lite, &t2_base->pbias_lite);
-#endif
-#if defined(CONFIG_TWL4030_POWER)
- twl4030_power_mmc_init();
- mdelay(100); /* ramp-up delay from Linux code */
-#endif
-#if defined(CONFIG_OMAP34XX)
+
writel(pbias_lite | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
- defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT)
+ defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
+ defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
-#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
+#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
{
- int i;
-
sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
if (!clk)
return;
- if (clk == CLKDEV_EMMC_DATA) {
+
+ if (clk == CLKDEV_EMMC_DATA)
sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
- } else {
- for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++)
- ;
- sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl);
- }
+ else
+ sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
+ clk) - 1) - 1) << 16,
+ &host->regs->ce_clk_ctrl);
sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
}
.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
MMC_MODE_8BIT | MMC_MODE_HC,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .f_min = CLKDEV_MMC_INIT,
- .f_max = CLKDEV_EMMC_DATA,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
host->clk = CONFIG_SH_MMCIF_CLK;
+ sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
+ sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
+
mmc = mmc_create(&sh_mmcif_cfg, host);
if (mmc == NULL) {
free(host);
#define SOFT_RST_OFF (0 << 31)
#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
-#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */
+#ifdef CONFIG_RMOBILE
+#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9))
+#define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1))
+#else
+#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8))
+#define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA
+#endif
#define MMC_BUS_WIDTH_1 0
#define MMC_BUS_WIDTH_4 2
writeb(cmd, this->IO_ADDR_W);
}
-#ifdef CONFIG_SPL_BUILD
/* Check wait pin as dev ready indicator */
-static int omap_spl_dev_ready(struct mtd_info *mtd)
+static int omap_dev_ready(struct mtd_info *mtd)
{
return gpmc_cfg->status & (1 << 8);
}
-#endif
-
/*
* gen_true_ecc - This function will generate true ECC value, which
nand->read_buf = nand_read_buf16;
else
nand->read_buf = nand_read_buf;
- nand->dev_ready = omap_spl_dev_ready;
#endif
+
+ nand->dev_ready = omap_dev_ready;
+
return 0;
}
#
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
-obj-$(CONFIG_PCI) += pci.o pci_auto.o
+obj-$(CONFIG_PCI) += pci.o pci_auto.o pci_rom.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
return phys_addr;
}
-/*
- *
- */
+void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
+ u32 addr_and_ctrl)
+{
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
+}
+
+u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
+{
+ u32 addr;
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ pci_hose_read_config_dword(hose, dev, bar, &addr);
+ if (addr & PCI_BASE_ADDRESS_SPACE_IO)
+ return addr & PCI_BASE_ADDRESS_IO_MASK;
+ else
+ return addr & PCI_BASE_ADDRESS_MEM_MASK;
+}
int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
--- /dev/null
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
+ *
+ * Modifications are:
+ * Copyright (C) 2003-2004 Linux Networx
+ * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
+ * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
+ * Copyright (C) 2005-2006 Tyan
+ * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
+ * Copyright (C) 2005-2009 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
+ *
+ * PCI Bus Services, see include/linux/pci.h for further explanation.
+ *
+ * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
+ * David Mosberger-Tang
+ *
+ * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <errno.h>
+#include <malloc.h>
+#include <pci.h>
+#include <pci_rom.h>
+#include <vbe.h>
+#include <video_fb.h>
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+#include <asm/acpi.h>
+#endif
+
+__weak bool board_should_run_oprom(pci_dev_t dev)
+{
+ return true;
+}
+
+static bool should_load_oprom(pci_dev_t dev)
+{
+#ifdef CONFIG_HAVE_ACPI_RESUME
+ if (acpi_get_slp_type() == 3)
+ return false;
+#endif
+ if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
+ return 1;
+ if (board_should_run_oprom(dev))
+ return 1;
+
+ return 0;
+}
+
+__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
+{
+ return vendev;
+}
+
+static int pci_rom_probe(pci_dev_t dev, uint class,
+ struct pci_rom_header **hdrp)
+{
+ struct pci_rom_header *rom_header;
+ struct pci_rom_data *rom_data;
+ u16 vendor, device;
+ u32 vendev;
+ u32 mapped_vendev;
+ u32 rom_address;
+
+ pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
+ pci_read_config_word(dev, PCI_DEVICE_ID, &device);
+ vendev = vendor << 16 | device;
+ mapped_vendev = board_map_oprom_vendev(vendev);
+ if (vendev != mapped_vendev)
+ debug("Device ID mapped to %#08x\n", mapped_vendev);
+
+#ifdef CONFIG_X86_OPTION_ROM_ADDR
+ rom_address = CONFIG_X86_OPTION_ROM_ADDR;
+#else
+ pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
+ pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
+ if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
+ debug("%s: rom_address=%x\n", __func__, rom_address);
+ return -ENOENT;
+ }
+
+ /* Enable expansion ROM address decoding. */
+ pci_write_config_dword(dev, PCI_ROM_ADDRESS,
+ rom_address | PCI_ROM_ADDRESS_ENABLE);
+#endif
+ debug("Option ROM address %x\n", rom_address);
+ rom_header = (struct pci_rom_header *)rom_address;
+
+ debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
+ le32_to_cpu(rom_header->signature),
+ rom_header->size * 512, le32_to_cpu(rom_header->data));
+
+ if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
+ printf("Incorrect expansion ROM header signature %04x\n",
+ le32_to_cpu(rom_header->signature));
+ return -EINVAL;
+ }
+
+ rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
+
+ debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
+ rom_data->vendor, rom_data->device);
+
+ /* If the device id is mapped, a mismatch is expected */
+ if ((vendor != rom_data->vendor || device != rom_data->device) &&
+ (vendev == mapped_vendev)) {
+ printf("ID mismatch: vendor ID %04x, device ID %04x\n",
+ rom_data->vendor, rom_data->device);
+ return -EPERM;
+ }
+
+ debug("PCI ROM image, Class Code %04x%02x, Code Type %02x\n",
+ rom_data->class_hi, rom_data->class_lo, rom_data->type);
+
+ if (class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
+ debug("Class Code mismatch ROM %08x, dev %08x\n",
+ (rom_data->class_hi << 8) | rom_data->class_lo,
+ class);
+ }
+ *hdrp = rom_header;
+
+ return 0;
+}
+
+int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header,
+ struct pci_rom_header **ram_headerp)
+{
+ struct pci_rom_data *rom_data;
+ unsigned int rom_size;
+ unsigned int image_size = 0;
+ void *target;
+
+ do {
+ /* Get next image, until we see an x86 version */
+ rom_header = (struct pci_rom_header *)((void *)rom_header +
+ image_size);
+
+ rom_data = (struct pci_rom_data *)((void *)rom_header +
+ le32_to_cpu(rom_header->data));
+
+ image_size = le32_to_cpu(rom_data->ilen) * 512;
+ } while ((rom_data->type != 0) && (rom_data->indicator != 0));
+
+ if (rom_data->type != 0)
+ return -EACCES;
+
+ rom_size = rom_header->size * 512;
+
+ target = (void *)PCI_VGA_RAM_IMAGE_START;
+ if (target != rom_header) {
+ debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
+ rom_header, target, rom_size);
+ memcpy(target, rom_header, rom_size);
+ if (memcmp(target, rom_header, rom_size)) {
+ printf("VGA ROM copy failed\n");
+ return -EFAULT;
+ }
+ }
+ *ram_headerp = target;
+
+ return 0;
+}
+
+static struct vbe_mode_info mode_info;
+
+int vbe_get_video_info(struct graphic_device *gdev)
+{
+#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE
+ struct vesa_mode_info *vesa = &mode_info.vesa;
+
+ gdev->winSizeX = vesa->x_resolution;
+ gdev->winSizeY = vesa->y_resolution;
+
+ gdev->plnSizeX = vesa->x_resolution;
+ gdev->plnSizeY = vesa->y_resolution;
+
+ gdev->gdfBytesPP = vesa->bits_per_pixel / 8;
+
+ switch (vesa->bits_per_pixel) {
+ case 24:
+ gdev->gdfIndex = GDF_32BIT_X888RGB;
+ break;
+ case 16:
+ gdev->gdfIndex = GDF_16BIT_565RGB;
+ break;
+ default:
+ gdev->gdfIndex = GDF__8BIT_INDEX;
+ break;
+ }
+
+ gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
+ gdev->pciBase = vesa->phys_base_ptr;
+
+ gdev->frameAdrs = vesa->phys_base_ptr;
+ gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution;
+
+ gdev->vprBase = vesa->phys_base_ptr;
+ gdev->cprBase = vesa->phys_base_ptr;
+
+ return 0;
+#else
+ return -ENOSYS;
+#endif
+}
+
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
+{
+ struct pci_rom_header *rom, *ram;
+ int vesa_mode = -1;
+ uint16_t class;
+ int ret;
+
+ /* Only execute VGA ROMs */
+ pci_read_config_word(dev, PCI_CLASS_DEVICE, &class);
+ if ((class ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
+ debug("%s: Class %#x, should be %#x\n", __func__, class,
+ PCI_CLASS_DISPLAY_VGA);
+ return -ENODEV;
+ }
+
+ if (!should_load_oprom(dev))
+ return -ENXIO;
+
+ ret = pci_rom_probe(dev, class, &rom);
+ if (ret)
+ return ret;
+
+ ret = pci_rom_load(class, rom, &ram);
+ if (ret)
+ return ret;
+
+ if (!board_should_run_oprom(dev))
+ return -ENXIO;
+
+#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
+ defined(CONFIG_FRAMEBUFFER_VESA_MODE)
+ vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
+#endif
+ debug("Selected vesa mode %d\b", vesa_mode);
+ if (emulate) {
+#ifdef CONFIG_BIOSEMU
+ BE_VGAInfo *info;
+
+ ret = biosemu_setup(dev, &info);
+ if (ret)
+ return ret;
+ biosemu_set_interrupt_handler(0x15, int15_handler);
+ ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true,
+ vesa_mode, &mode_info);
+ if (ret)
+ return ret;
+#else
+ printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
+ return -ENOSYS;
+#endif
+ } else {
+#ifdef CONFIG_X86
+ bios_set_interrupt_handler(0x15, int15_handler);
+
+ bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
+ &mode_info);
+#else
+ printf("BIOS native execution is only available on x86\n");
+ return -ENOSYS;
+#endif
+ }
+ debug("Final vesa mode %d\n", mode_info.video_mode);
+
+ return 0;
+}
{
u8 val = 0;
-#if defined(CONFIG_DRA7XX)
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
/*
* Currently valid for the dra7xx_evm board:
* Set TPS659038 LDO1 to 3.0 V
#include <linux/types.h>
#include <power/pmic.h>
#include <i2c.h>
-#include <compiler.h>
+#include <linux/compiler.h>
int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
{
TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
-void twl4030_power_mmc_init(void)
+void twl4030_power_mmc_init(int dev_index)
{
- /* Set VMMC1 to 3.15 Volts */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
- TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
- TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ if (dev_index == 0) {
+ /* Set VMMC1 to 3.15 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
+ TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
- /* Set VMMC2 to 3.15 Volts */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
- TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
- TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ mdelay(100); /* ramp-up delay from Linux code */
+ } else if (dev_index == 1) {
+ /* Set VMMC2 to 3.15 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+ TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ mdelay(100); /* ramp-up delay from Linux code */
+ }
}
#define NUM_SECS_IN_DAY DAYS_TO_SECS(1)
/* Enable the RTC prescaler enable register */
-static void rtc_init(void)
+void rtc_init(void)
{
if (!(bfin_read_RTC_PREN() & 0x1))
bfin_write_RTC_PREN(0x1);
#include <common.h>
#include <command.h>
#include <rtc.h>
+#include <version.h>
#if defined(__I386__) || defined(CONFIG_MALTA)
#include <asm/io.h>
#if defined(CONFIG_CMD_DATE)
+/* Set this to 1 to clear the CMOS RAM */
+#define CLEAR_CMOS 0
+
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
#define RTC_CONFIG_B 0x0B
#define RTC_CONFIG_C 0x0C
#define RTC_CONFIG_D 0x0D
+#define RTC_REG_SIZE 0x80
+
+#define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5)
+#define RTC_CONFIG_A_RATE_1024HZ 6
+#define RTC_CONFIG_B_24H (1 << 1)
+
+#define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80
/* ------------------------------------------------------------------------- */
*/
static uchar rtc_read (uchar reg)
{
- return(in8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg));
+ return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
}
static void rtc_write (uchar reg, uchar val)
{
- out8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg, val);
+ out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val);
}
#else
static uchar rtc_read (uchar reg)
{
out8(RTC_PORT_MC146818,reg);
- return(in8(RTC_PORT_MC146818+1));
+ return in8(RTC_PORT_MC146818 + 1);
}
static void rtc_write (uchar reg, uchar val)
{
out8(RTC_PORT_MC146818,reg);
- out8(RTC_PORT_MC146818+1,val);
+ out8(RTC_PORT_MC146818+1, val);
}
#endif
+void rtc_init(void)
+{
+#if CLEAR_CMOS
+ int i;
+
+ rtc_write(RTC_SECONDS_ALARM, 0);
+ rtc_write(RTC_MINUTES_ALARM, 0);
+ rtc_write(RTC_HOURS_ALARM, 0);
+ for (i = RTC_CONFIG_A; i < RTC_REG_SIZE; i++)
+ rtc_write(i, 0);
+ printf("RTC: zeroing CMOS RAM\n");
+#endif
+
+ /* Setup the real time clock */
+ rtc_write(RTC_CONFIG_B, RTC_CONFIG_B_24H);
+ /* Setup the frequency it operates at */
+ rtc_write(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ |
+ RTC_CONFIG_A_RATE_1024HZ);
+ /* Ensure all reserved bits are 0 in register D */
+ rtc_write(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME);
+
+ /* Clear any pending interrupts */
+ rtc_read(RTC_CONFIG_C);
+}
#endif
#define _MVRTC_H_
#include <asm/arch/soc.h>
-#include <compiler.h>
+#include <linux/compiler.h>
/* RTC registers */
struct mvrtc_registers {
void NS16550_init(NS16550_t com_port, int baud_divisor)
{
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
+#if (defined(CONFIG_SPL_BUILD) && \
+ (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
/*
- * On some OMAP3 devices when UART3 is configured for boot mode before
- * SPL starts only THRE bit is set. We have to empty the transmitter
- * before initialization starts.
+ * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
+ * before SPL starts only THRE bit is set. We have to empty the
+ * transmitter before initialization starts.
*/
if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
== UART_LSR_THRE) {
/* Check for a chosen console */
node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
if (node < 0)
- node = fdtdec_get_alias_node(gd->fdt_blob, "console");
+ node = fdt_path_offset(gd->fdt_blob, "console");
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) {
gd->cur_serial_dev = dev;
return;
static int pl01x_generic_serial_init(struct pl01x_regs *regs,
enum pl01x_type type)
{
- unsigned int lcr;
-
+ switch (type) {
+ case TYPE_PL010:
+ /* disable everything */
+ writel(0, ®s->pl010_cr);
+ break;
+ case TYPE_PL011:
#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
- if (type == TYPE_PL011) {
/* Empty RX fifo if necessary */
if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
readl(®s->dr);
}
- }
#endif
+ /* disable everything */
+ writel(0, ®s->pl011_cr);
+ break;
+ default:
+ return -EINVAL;
+ }
- /* First, disable everything */
- writel(0, ®s->pl010_cr);
+ return 0;
+}
- /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
+static int set_line_control(struct pl01x_regs *regs)
+{
+ unsigned int lcr;
+ /*
+ * Internal update of baud rate register require line
+ * control register write
+ */
lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
- writel(lcr, ®s->pl011_lcrh);
-
- switch (type) {
- case TYPE_PL010:
- break;
- case TYPE_PL011: {
#ifdef CONFIG_PL011_SERIAL_RLCR
+ {
int i;
/*
writel(lcr, ®s->fr);
writel(lcr, ®s->pl011_rlcr);
- /* lcrh needs to be set again for change to be effective */
- writel(lcr, ®s->pl011_lcrh);
-#endif
- break;
- }
- default:
- return -EINVAL;
}
-
+#endif
+ writel(lcr, ®s->pl011_lcrh);
return 0;
}
writel(divider, ®s->pl011_ibrd);
writel(fraction, ®s->pl011_fbrd);
+ set_line_control(regs);
/* Finally, enable the UART */
writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
pl01x_generic_serial_init(base_regs, pl01x_type);
- pl01x_generic_setbrg(base_regs, TYPE_PL010, clock, baudrate);
+ pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
}
/*
#include <dm/device.h>
#include <dm/platform_data/serial-uniphier.h>
#include <serial.h>
+#include <fdtdec.h>
#define UART_REG(x) \
u8 x; \
}
#ifdef CONFIG_OF_CONTROL
-static const struct udevice_id uniphier_uart_of_match = {
- { .compatible = "panasonic,uniphier-uart"},
+static const struct udevice_id uniphier_uart_of_match[] = {
+ { .compatible = "panasonic,uniphier-uart" },
{},
};
static int uniphier_serial_ofdata_to_platdata(struct udevice *dev)
{
- /*
- * TODO: Masahiro Yamada (yamada.m@jp.panasonic.com)
- *
- * Implement conversion code from DTB to platform data
- * when supporting CONFIG_OF_CONTROL on UniPhir platform.
- */
+ struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+ DECLARE_GLOBAL_DATA_PTR;
+
+ plat->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 0);
+
+ return 0;
}
#endif
struct spi_slave *slave = &qslave->slave;
u32 memval = 0;
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
slave->memory_map = (void *)MMAP_START_ADDR_DRA;
#else
slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
uint status;
int timeout;
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
int val;
#endif
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
writel(MM_SWITCH, &qslave->base->memswitch);
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
val = readl(CORE_CTRL_IO);
val |= MEM_CS;
writel(val, CORE_CTRL_IO);
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
writel(~MM_SWITCH, &qslave->base->memswitch);
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
val = readl(CORE_CTRL_IO);
val &= MEM_CS_UNSELECT;
writel(val, CORE_CTRL_IO);
#include <config.h>
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <fdtdec.h>
#include <i2c.h>
#include <tpm.h>
#include <common.h>
#include <fdtdec.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <i2c.h>
#include <tpm.h>
#include <asm-generic/errno.h>
*/
#include <common.h>
+#include <linux/err.h>
#include <usb.h>
#include <asm/arch/ehci-uniphier.h>
#include "ehci.h"
+#ifdef CONFIG_OF_CONTROL
+#include <fdtdec.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FDT gd->fdt_blob
+#define COMPAT "panasonic,uniphier-ehci"
+
+static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+{
+ int offset;
+
+ for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
+ offset >= 0;
+ offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
+ if (index == 0) {
+ *base = (struct ehci_hccr *)
+ fdtdec_get_addr(FDT, offset, "reg");
+ return 0;
+ }
+ index--;
+ }
+
+ return -ENODEV; /* not found */
+}
+#else
+static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+{
+ *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base;
+ return 0;
+}
+#endif
+
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
+ int ret;
struct ehci_hccr *cr;
struct ehci_hcor *or;
uniphier_ehci_reset(index, 0);
- cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base);
+ ret = get_uniphier_ehci_base(index, &cr);
+ if (ret < 0)
+ return ret;
or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
*hccr = cr;
void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
{
omap_usb_dpll_lock(phy_regs);
-
usb3_phy_partial_powerup(phy_regs);
/*
* Give enough time for the PHY to partially power-up before
* team.
*/
mdelay(100);
- usb3_phy_power(1);
}
static void omap_enable_usb3_phy(struct omap_xhci *omap)
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+obj-$(CONFIG_VIDEO_X86) += x86_fb.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
obj-$(CONFIG_VIDEO_PARADE) += parade.o
#include <common.h>
#include <command.h>
+#include <bios_emul.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
}
#include "../bios_emulator/include/biosemu.h"
-extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
int radeon_probe(struct radeonfb_info *rinfo)
{
--- /dev/null
+/*
+ *
+ * Vesa frame buffer driver for x86
+ *
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <video_fb.h>
+#include <vbe.h>
+#include "videomodes.h"
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+
+void *video_hw_init(void)
+{
+ GraphicDevice *gdev = &ctfb;
+ int bits_per_pixel;
+
+ printf("Video: ");
+ if (vbe_get_video_info(gdev)) {
+ printf("No video mode configured\n");
+ return NULL;
+ }
+
+ bits_per_pixel = gdev->gdfBytesPP * 8;
+ sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
+ bits_per_pixel);
+ printf("%s\n", gdev->modeIdent);
+
+ return (void *)gdev;
+}
#include <ext_common.h>
#include <ext4fs.h>
#include "ext4_common.h"
+#include <div64.h>
int ext4fs_symlinknest;
struct ext_filesystem ext_fs;
if (len > filesize)
len = filesize;
- blockcnt = ((len + pos) + blocksize - 1) / blocksize;
+ blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
- for (i = pos / blocksize; i < blockcnt; i++) {
+ for (i = lldiv(pos, blocksize); i < blockcnt; i++) {
lbaint_t blknr;
- int blockoff = pos % blocksize;
+ int blockoff = pos - (blocksize * i);
int blockend = blocksize;
int skipfirst = 0;
blknr = read_allocated_block(&(node->inode), i);
/* Last block. */
if (i == blockcnt - 1) {
- blockend = (len + pos) % blocksize;
+ blockend = (len + pos) - (blocksize * i);
/* The last portion is exactly blocksize. */
if (!blockend)
}
/* First block. */
- if (i == pos / blocksize) {
+ if (i == lldiv(pos, blocksize)) {
skipfirst = blockoff;
blockend -= skipfirst;
}
#include <asm/byteorder.h>
#include <part.h>
#include <linux/ctype.h>
+#include <div64.h>
+#include <linux/math64.h>
#include "fat.c"
static void uppercase(char *str, int len)
*/
static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size)
{
- __u32 startsect, sect_num;
+ __u32 startsect, sect_num, offset;
if (clustnum > 0) {
startsect = mydata->data_begin +
startsect = mydata->rootdir_sect;
}
- sect_num = size / mydata->sect_size;
- if (size % mydata->sect_size)
+ sect_num = div_u64_rem(size, mydata->sect_size, &offset);
+
+ if (offset != 0)
sect_num++;
if (startsect + sect_num > cur_part_info.start + total_sector)
return -1;
-
return 0;
}
#include <fs.h>
#include <sandboxfs.h>
#include <asm/io.h>
+#include <div64.h>
+#include <linux/math64.h>
DECLARE_GLOBAL_DATA_PTR;
printf("%llu bytes read in %lu ms", len_read, time);
if (time > 0) {
puts(" (");
- print_size(len_read / time * 1000, "/s");
+ print_size(div_u64(len_read, time) * 1000, "/s");
puts(")");
}
puts("\n");
printf("%llu bytes written in %lu ms", len, time);
if (time > 0) {
puts(" (");
- print_size(len / time * 1000, "/s");
+ print_size(div_u64(len, time) * 1000, "/s");
puts(")");
}
puts("\n");
--- /dev/null
+/*
+ * Copyright (C) 1996-1999 SciTech Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _BIOS_EMUL_H
+#define _BIOS_EMUL_H
+
+/* Include the register header directly here */
+#include "../drivers/bios_emulator/include/x86emu/regs.h"
+#include <pci.h>
+
+/****************************************************************************
+REMARKS:
+Data structure used to describe the details for the BIOS emulator system
+environment as used by the X86 emulator library.
+
+HEADER:
+biosemu.h
+
+MEMBERS:
+vgaInfo - VGA BIOS information structure
+biosmem_base - Base of the BIOS image
+biosmem_limit - Limit of the BIOS image
+busmem_base - Base of the VGA bus memory
+****************************************************************************/
+typedef struct {
+ int function;
+ int device;
+ int bus;
+ u32 VendorID;
+ u32 DeviceID;
+ pci_dev_t pcidev;
+ void *BIOSImage;
+ u32 BIOSImageLen;
+ u8 LowMem[1536];
+} BE_VGAInfo;
+
+struct vbe_mode_info;
+
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp);
+
+/* Run a BIOS ROM natively (only supported on x86 machines) */
+void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+ struct vbe_mode_info *mode_info);
+
+/**
+ * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS
+ *
+ * This installs an interrupt handler that the BIOS will call when needed.
+ *
+ * @intnum: Interrupt number to install a handler for
+ * @int_handler_func: Function to call to handle interrupt
+ */
+void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
+
+void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
+
+int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
+
+int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+ struct vbe_mode_info *mode_info);
+
+#endif
#ifdef CONFIG_ARM
#define asmlinkage /* nothing */
#endif
+#ifdef CONFIG_X86
+#define asmlinkage __attribute__((regparm(0)))
+#endif
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
-#ifdef CONFIG_HERMES
-/* $(BOARD)/hermes.c */
-void hermes_start_lxt980 (int speed);
-#endif
-
#ifdef CONFIG_EVB64260
void evb64260_init(void);
void debug_led(int, int);
#define SICR_ENET_CLKRT ((uint)0x00002600)
#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
-/*** HERMES-PRO ******************************************************/
-
-/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
-
-#ifdef CONFIG_HERMES
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_HERMES */
-
/*** IP860 **********************************************************/
#if defined(CONFIG_IP860)
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0xfc000000
-#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
-#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated.
+ * Felipe Balbi <balbi@ti.com>
+ *
+ * Configuration settings for the TI Beagle x15 board.
+ * See ti_omap5_common.h for omap5 common settings.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BEAGLE_X15_H
+#define __CONFIG_BEAGLE_X15_H
+
+#define CONFIG_AM57XX
+
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_ENV_SIZE (64 << 10)
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+
+#define CONFIG_CMD_SAVEENV
+
+#define CONSOLEDEV "ttyO2"
+#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+
+#include <configs/ti_omap5_common.h>
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
+#define CONFIG_MII /* Required in net/eth.c */
+#define CONFIG_PHY_GIGE /* per-board part of CPSW */
+#define CONFIG_PHYLIB
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB3PHY1_HOST
+
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+#endif /* __CONFIG_BEAGLE_X5_H */
#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
#define CONFIG_SYS_X86_START16 0xfffff800
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_X86_RESET_VECTOR
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-/*
- * These common x86 features are not yet supported, but are added in
- * follow-on patches in this series. Add undefs here to avoid every patch
- * having to put things back into x86-common.h
- */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-#undef CONFIG_ICH_SPI
-#undef CONFIG_SPI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_SF
-#undef CONFIG_USB_EHCI
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_SCSI
+#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin
+#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
+#define CONFIG_VIDEO_X86
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xefff
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+
+#define CONFIG_BIOSEMU
+#define VIDEO_IO_OFFSET 0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_CROS_EC
+#define CONFIG_CROS_EC_LPC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_ARCH_EARLY_INIT_R
+
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
#include <configs/ti_omap5_common.h>
-#undef CONFIG_MISC_INIT_R
#undef CONFIG_SPL_OS_BOOT
/* Enable Generic board */
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
+#define CONFIG_HSMMC2_8BIT
/* CPSW Ethernet */
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
-#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- * +0x0004
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * +0x0000 => 0x000000C0
- */
-#define CONFIG_SYS_SIUMCR 0
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- * +0x0200 => 0x00C2
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * +0x0240 => 0x0082
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* +0x0286 => 0x00B0D0C0 */
-#define CONFIG_SYS_PLPRCR \
- ( (11 << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* +0x0282 => 0x03800000 */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* +0x0220 => 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => TIMEP=1 */
-#define CONFIG_SYS_RCCR 0x0100
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* allow for max 4 MB of Flash */
-#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
- OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-/* 8 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR1/OR1 - SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
- */
-#define HPRO2_BASE 0xE0000000
-#define HPRO2_OR_AM 0xFFFF8000
-#define HPRO2_TIMING 0x00000934
-
-#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
-#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: not used
- * BR4/OR4: not used
- * BR5/OR5: not used
- * BR6/OR6: not used
- * BR7/OR7: not used
- */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-#endif /* __CONFIG_H */
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x00908000
#define CONFIG_SPL_MAX_SIZE 0x10000
-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7"
#define CONFIG_SPL_STACK 0x0091FFB8
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#if defined(CONFIG_SPL_MMC_SUPPORT)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
#endif
#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
-#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
-#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* NAND boot config */
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* Partition tables */
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif /* __OMAP3_EVM_QUICK_MMC_H */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_BAUDRATE 115200
+#define CONFIG_MISC_INIT_R
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x10000000
-#define CONFIG_SDRAM1_BASE 0x90000000
-#define CONFIG_SDRAM1_SIZE 0x10000000
-
-#define CONFIG_SPL_TEXT_BASE 0x40000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 2
-#define CONFIG_DDR_NUM_CH1 2
-
-#define CONFIG_UNIPHIER_SMP
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x20000000
-#define CONFIG_SDRAM1_BASE 0xa0000000
-#define CONFIG_SDRAM1_SIZE 0x20000000
-
-#define CONFIG_SPL_TEXT_BASE 0x100000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/* #define CONFIG_DDR_STANDARD */
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x10000000
-#define CONFIG_SDRAM1_BASE 0x90000000
-#define CONFIG_SDRAM1_SIZE 0x10000000
-
-#define CONFIG_SPL_TEXT_BASE 0x40000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FIT
+#endif
+
#endif /* ! __CONFIG_PXM2_H */
--- /dev/null
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/* Architecture, CPU, etc.*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_BCM2835
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_DCACHE_OFF
+/*
+ * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
+ * so 2708 has historically been used rather than a dedicated 2835 ID.
+ */
+#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
+
+/* Enable driver model */
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+
+/* Memory layout */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_TEXT_BASE 0x00008000
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+/*
+ * The board really has 256M. However, the VC (VideoCore co-processor) shares
+ * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
+ * smaller amount of RAM is present in order to avoid stomping on the area
+ * the VC uses.
+ */
+#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_SDRAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x00200000
+#define CONFIG_LOADADDR 0x00200000
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Devices */
+/* GPIO */
+#define CONFIG_BCM2835_GPIO
+/* LCD */
+#define CONFIG_LCD
+#define CONFIG_LCD_DT_SIMPLEFB
+#define LCD_BPP LCD_COLOR16
+/*
+ * Prevent allocation of RAM for FB; the real FB address is queried
+ * dynamically from the VideoCore co-processor, and comes from RAM
+ * not owned by the ARM CPU.
+ */
+#define CONFIG_FB_ADDR 0
+#define CONFIG_VIDEO_BCM2835
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_BCM2835_SDHCI
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MISC_INIT_R
+#endif
+
+/* Console UART */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 3000000
+#define CONFIG_PL01x_PORTS { (void *)0x20201000 }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Environment */
+#define CONFIG_ENV_SIZE SZ_16K
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_SYS_LOAD_ADDR 0x1000000
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Shell */
+#define CONFIG_SYS_MAXARGS 8
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_COMMAND_HISTORY
+
+/* Commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* Device tree support */
+#define CONFIG_OF_BOARD_SETUP
+/* ATAGs support for bootm/bootz */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+#include <config_distro_defaults.h>
+
+/* Some things don't make sense on this HW or yet */
+#undef CONFIG_CMD_FPGA
+
+/* Environment */
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial,lcd\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it low in memory to avoid conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it low in memory to avoid conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00000000\0" \
+ "pxefile_addr_r=0x00100000\0" \
+ "kernel_addr_r=0x01000000\0" \
+ "fdt_addr_r=0x02000000\0" \
+ "ramdisk_addr_r=0x02100000\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_DEVICE_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV
+
+#define CONFIG_BOOTDELAY 2
+
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-
-/* Architecture, CPU, etc.*/
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_BCM2835
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_DCACHE_OFF
-/*
- * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
- * so 2708 has historically been used rather than a dedicated 2835 ID.
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
-
-/* Enable driver model */
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-
-/* Memory layout */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_TEXT_BASE 0x00008000
-#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/*
- * The board really has 256M. However, the VC (VideoCore co-processor) shares
- * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
- * smaller amount of RAM is present in order to avoid stomping on the area
- * the VC uses.
- */
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_SDRAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x00200000
-#define CONFIG_LOADADDR 0x00200000
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH
-
-/* Devices */
-/* GPIO */
-#define CONFIG_BCM2835_GPIO
-/* LCD */
-#define CONFIG_LCD
-#define CONFIG_LCD_DT_SIMPLEFB
-#define LCD_BPP LCD_COLOR16
-/*
- * Prevent allocation of RAM for FB; the real FB address is queried
- * dynamically from the VideoCore co-processor, and comes from RAM
- * not owned by the ARM CPU.
- */
-#define CONFIG_FB_ADDR 0
-#define CONFIG_VIDEO_BCM2835
-#define CONFIG_SYS_WHITE_ON_BLACK
-
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS
-#define CONFIG_BCM2835_SDHCI
-
-#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
-#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_MISC_INIT_R
-#endif
-
-/* Console UART */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK 3000000
-#define CONFIG_PL01x_PORTS { (void *)0x20201000 }
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 115200
-
-/* Console configuration */
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Environment */
-#define CONFIG_ENV_SIZE SZ_16K
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_SYS_LOAD_ADDR 0x1000000
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_PREBOOT \
- "if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
- "env import -t -r ${loadaddr} ${filesize}; " \
- "fi"
-
-/* Shell */
-#define CONFIG_SYS_MAXARGS 8
-#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_COMMAND_HISTORY
-
-/* Commands */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_MMC
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
-/* Device tree support */
-#define CONFIG_OF_BOARD_SETUP
-/* ATAGs support for bootm/bootz */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
-#include <config_distro_defaults.h>
-
-/* Some things don't make sense on this HW or yet */
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SAVEENV
-
-/* Environment */
-#define ENV_DEVICE_SETTINGS \
- "stdin=serial,lcd\0" \
- "stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
-
-/*
- * Memory layout for where various images get loaded by boot scripts:
- *
- * scriptaddr can be pretty much anywhere that doesn't conflict with something
- * else. Put it low in memory to avoid conflicts.
- *
- * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
- * something else. Put it low in memory to avoid conflicts.
- *
- * kernel_addr_r must be within the first 128M of RAM in order for the
- * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
- * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
- * should not overlap that area, or the kernel will have to copy itself
- * somewhere else before decompression. Similarly, the address of any other
- * data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
- * compressed load address.
- *
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- * the compressed kernel to be up to 16M too.
- *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
- * for the FDT/DTB to be up to 1M, which is hopefully plenty.
- */
-#define ENV_MEM_LAYOUT_SETTINGS \
- "scriptaddr=0x00000000\0" \
- "pxefile_addr_r=0x00100000\0" \
- "kernel_addr_r=0x01000000\0" \
- "fdt_addr_r=0x02000000\0" \
- "fdtfile=bcm2835-rpi-b.dtb\0" \
- "ramdisk_addr_r=0x02100000\0" \
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- ENV_DEVICE_SETTINGS \
- ENV_MEM_LAYOUT_SETTINGS \
- BOOTENV
-
-#define CONFIG_BOOTDELAY 2
-
-#endif
#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FIT
+#endif
+
#endif /* ! __CONFIG_RUT_H */
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
/* FAT sd card locations. */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_MISC_INIT_R
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
"partitions=" PARTS_DEFAULT "\0" \
"optargs=\0" \
"mmcdev=0\0" \
- "mmcroot=/dev/mmcblk1p2 rw\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext4 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"setenv fdtfile dra7-evm.dtb; fi;" \
"if test $board_name = dra72x; then " \
"setenv fdtfile dra72-evm.dtb; fi;" \
+ "if test $board_name = beagle_x15; then " \
+ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* U-boot - Common settings for UniPhier Family */
-
-#ifndef __CONFIG_UNIPHIER_COMMON_H__
-#define __CONFIG_UNIPHIER_COMMON_H__
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) && \
- defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \
-are defined. Select only one of them."
-#endif
-
-/*
- * Support card address map
- */
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
-# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
-# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
-# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# define CONFIG_SUPPORT_CARD_BASE 0x08000000
-# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
-# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
-# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
-#endif
-
-#ifdef CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
-#define CONFIG_SYS_NS16550_CLK 12288000
-#define CONFIG_SYS_NS16550_REG_SIZE -2
-#endif
-
-#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
-#define CONFIG_SMC911X_32_BIT
-
-#define CONFIG_SYS_MALLOC_F_LEN 0x2000
-
-/*-----------------------------------------------------------------------
- * MMU and Cache Setting
- *----------------------------------------------------------------------*/
-
-/* Comment out the following to enable L1 cache */
-/* #define CONFIG_SYS_ICACHE_OFF */
-/* #define CONFIG_SYS_DCACHE_OFF */
-
-/* Comment out the following to enable L2 cache */
-#define CONFIG_UNIPHIER_L2CACHE_ON
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-#define CONFIG_TIMESTAMP
-
-/* FLASH related */
-#define CONFIG_MTD_DEVICE
-
-/*
- * uncomment the following to disable FLASH related code.
- */
-/* #define CONFIG_SYS_NO_FLASH */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_FLASH_BASE 0
-
-/*
- * flash_toggle does not work for out supoort card.
- * We need to use flash_status_poll.
- */
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
-
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-# define CONFIG_SYS_FLASH_BANKS_LIST {0x00000000}
-# define CONFIG_SYS_FLASH_BANKS_SIZES {0x02000000}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-# define CONFIG_SYS_FLASH_BANKS_LIST {0x04000000}
-# define CONFIG_SYS_FLASH_BANKS_SIZES {0x04000000}
-#endif
-
-/* serial console configuration */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_GENERIC_BOARD
-
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_USE_ARCH_MEMCPY
-#endif
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_CONS_INDEX 1
-
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
- */
-/* #define CONFIG_ENV_IS_IN_NAND */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET 0x0
-/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
-
-/* Time clock 1MHz */
-#define CONFIG_SYS_TIMER_RATE 1000000
-
-/*
- * By default, ARP timeout is 5 sec.
- * The first ARP request does not seem to work.
- * So we need to retry ARP request anyway.
- * We want to shrink the interval until the second ARP request.
- */
-#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_NAND /* NAND flash suppport */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 2
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_NAND_DENALI_ECC_SIZE 1024
-
-#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
-#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
-
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
-
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-
-/* USB */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-#define CONFIG_DOS_PARTITION
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-/*
- * Network Configuration
- */
-#define CONFIG_ETHADDR 00:21:83:24:00:00
-#define CONFIG_SERVERIP 192.168.11.1
-#define CONFIG_IPADDR 192.168.11.10
-#define CONFIG_GATEWAYIP 192.168.11.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 0x84000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_BOOTFILE "fit.itb"
-
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-
-#define CONFIG_BOOTCOMMAND "run $bootmode"
-
-#define CONFIG_ROOTPATH "/nfs/root/path"
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs $bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
- "tftpboot; bootm;"
-
-#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "image_offset=0x00080000\0" \
- "image_size=0x00f00000\0" \
- "verify=n\0" \
- "autostart=yes\0" \
- "norboot=run add_default_bootargs;" \
- "bootm $image_offset\0" \
- "nandboot=run add_default_bootargs;" \
- "nand read $loadaddr $image_offset $image_size;" \
- "bootm\0" \
- "add_default_bootargs=setenv bootargs $bootargs" \
- " console=ttyS0,$baudrate\0" \
-
-/* FIT support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-
-/* Open Firmware flat tree */
-#define CONFIG_OF_LIBFDT
-
-#define CONFIG_HAVE_ARM_SECURE
-
-/* Memory Size & Mapping */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
-
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
-/* Thre is no memory hole */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
-#else
-#define CONFIG_NR_DRAM_BANKS 2
-#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
-#endif
-
-#define CONFIG_SYS_TEXT_BASE 0x84000000
-
-#define CONFIG_BOARD_POSTCLK_INIT
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000)
-
-#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000)
-
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NAND_SUPPORT
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
-#define CONFIG_SPL_BOARD_INIT
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
-
-#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* U-boot - Common settings for UniPhier Family */
+
+#ifndef __CONFIG_UNIPHIER_COMMON_H__
+#define __CONFIG_UNIPHIER_COMMON_H__
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_DDR_NUM_CH0 2
+#define CONFIG_DDR_NUM_CH1 2
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x20000000
+#define CONFIG_SDRAM1_BASE 0xa0000000
+#define CONFIG_SDRAM1_SIZE 0x20000000
+#endif
+
+#if defined(CONFIG_MACH_PH1_LD4)
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x10000000
+#define CONFIG_SDRAM1_BASE 0x90000000
+#define CONFIG_SDRAM1_SIZE 0x10000000
+#endif
+
+#if defined(CONFIG_MACH_PH1_SLD8)
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x10000000
+#define CONFIG_SDRAM1_BASE 0x90000000
+#define CONFIG_SDRAM1_SIZE 0x10000000
+#endif
+
+/*
+ * Support card address map
+ */
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
+# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
+# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
+# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# define CONFIG_SUPPORT_CARD_BASE 0x08000000
+# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
+# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
+# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
+#endif
+
+#ifdef CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
+#define CONFIG_SYS_NS16550_CLK 12288000
+#define CONFIG_SYS_NS16550_REG_SIZE -2
+#endif
+
+/* TODO: move to Kconfig and device tree */
+#if 0
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SMC911X
+
+#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
+#define CONFIG_SMC911X_32_BIT
+
+#define CONFIG_SYS_MALLOC_F_LEN 0x2000
+
+/*-----------------------------------------------------------------------
+ * MMU and Cache Setting
+ *----------------------------------------------------------------------*/
+
+/* Comment out the following to enable L1 cache */
+/* #define CONFIG_SYS_ICACHE_OFF */
+/* #define CONFIG_SYS_DCACHE_OFF */
+
+/* Comment out the following to enable L2 cache */
+#define CONFIG_UNIPHIER_L2CACHE_ON
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP
+
+/* FLASH related */
+#define CONFIG_MTD_DEVICE
+
+/*
+ * uncomment the following to disable FLASH related code.
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_MONITOR_BASE 0
+#define CONFIG_SYS_FLASH_BASE 0
+
+/*
+ * flash_toggle does not work for out supoort card.
+ * We need to use flash_status_poll.
+ */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
+
+/* serial console configuration */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#endif
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_CONS_INDEX 1
+
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
+ */
+/* #define CONFIG_ENV_IS_IN_NAND */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x0
+/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+
+/* Time clock 1MHz */
+#define CONFIG_SYS_TIMER_RATE 1000000
+
+/*
+ * By default, ARP timeout is 5 sec.
+ * The first ARP request does not seem to work.
+ * So we need to retry ARP request anyway.
+ * We want to shrink the interval until the second ARP request.
+ */
+#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 2
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_NAND_DENALI_ECC_SIZE 1024
+
+#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
+#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
+
+#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
+
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+
+/* USB */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_ETHADDR 00:21:83:24:00:00
+#define CONFIG_SERVERIP 192.168.11.1
+#define CONFIG_IPADDR 192.168.11.10
+#define CONFIG_GATEWAYIP 192.168.11.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 0x84000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_BOOTFILE "fit.itb"
+
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+
+#define CONFIG_BOOTCOMMAND "run $bootmode"
+
+#define CONFIG_ROOTPATH "/nfs/root/path"
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs $bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
+ "tftpboot; bootm;"
+
+#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "image_offset=0x00080000\0" \
+ "image_size=0x00f00000\0" \
+ "verify=n\0" \
+ "norboot=run add_default_bootargs;" \
+ "bootm $image_offset\0" \
+ "nandboot=run add_default_bootargs;" \
+ "nand read $loadaddr $image_offset $image_size;" \
+ "bootm\0" \
+ "add_default_bootargs=setenv bootargs $bootargs" \
+ " console=ttyS0,$baudrate\0" \
+
+/* Open Firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_HAVE_ARM_SECURE
+
+/* Memory Size & Mapping */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
+
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
+/* Thre is no memory hole */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
+#else
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
+#endif
+
+#define CONFIG_SYS_TEXT_BASE 0x84000000
+
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define CONFIG_SPL_TEXT_BASE 0x00040000
+#endif
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_SPL_TEXT_BASE 0x00100000
+#endif
+
+#define CONFIG_BOARD_POSTCLK_INIT
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000)
+
+#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000)
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
+
+#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */
COMPAT_INTEL_MICROCODE, /* Intel microcode update */
COMPAT_MEMORY_SPD, /* Memory SPD information */
+ COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */
+ COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */
+ COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */
COMPAT_COUNT,
};
int fdtdec_get_alias_seq(const void *blob, const char *base, int node,
int *seqp);
-/**
- * Get the offset of the given alias node
- *
- * This looks up an alias in /aliases then finds the offset of that node.
- *
- * @param blob Device tree blob (if NULL, then error is returned)
- * @param name Alias name, e.g. "console"
- * @return Node offset referred to by that alias, or -ve FDT_ERR_...
- */
-int fdtdec_get_alias_node(const void *blob, const char *name);
-
/**
* Get the offset of the given chosen node
*
#define cond_resched() do { } while (0)
#define yield() do { } while (0)
-#define __user
#define __init
#define __exit
#define __devinit
#define __devinitdata
#define __devinitconst
-#define __iomem
#define kthread_create(...) __builtin_return_address(0)
#define kthread_stop(...) do { } while (0)
#define cdev_add(...) 0
#define cdev_del(...) do { } while (0)
-#define MAX_ERRNO 4095
-
#define prandom_u32(...) 0
typedef struct {
#define LLONG_MAX ((long long)(~0ULL>>1))
#define LLONG_MIN (-LLONG_MAX - 1)
#define ULLONG_MAX (~0ULL)
+#ifndef SIZE_MAX
#define SIZE_MAX (~(size_t)0)
+#endif
#define U8_MAX ((u8)~0U)
#define S8_MAX ((s8)(U8_MAX>>1))
#define OMAP_XHCI_BASE 0x488d0000
#define OMAP_OCP1_SCP_BASE 0x4A081000
#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif defined CONFIG_AM57XX
+#define OMAP_XHCI_BASE 0x48890000
+#define OMAP_OCP1_SCP_BASE 0x4A084c00
+#define OMAP_OTG_WRAPPER_BASE 0x48880000
#elif defined CONFIG_AM43XX
#define OMAP_XHCI_BASE 0x483d0000
#define OMAP_OCP1_SCP_BASE 0x483E8000
int mmc_legacy_init(int verbose);
#endif
+void board_mmc_power_init(void);
int board_mmc_init(bd_t *bis);
int cpu_mmc_init(bd_t *bis);
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
+/**
+ * pci_write_bar32() - Write the address of a BAR including control bits
+ *
+ * This writes a raw address (with control bits) to a bar
+ *
+ * @hose: PCI hose to use
+ * @dev: PCI device to update
+ * @barnum: BAR number (0-5)
+ * @addr: BAR address with control bits
+ */
+void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
+ u32 addr_and_ctrl);
+
+/**
+ * pci_read_bar32() - read the address of a bar
+ *
+ * @hose: PCI hose to use
+ * @dev: PCI device to inspect
+ * @barnum: BAR number (0-5)
+ * @return address of the bar, masking out any control bits
+ * */
+u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
+
#endif /* __ASSEMBLY__ */
#endif /* _PCI_H */
#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302
#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
-#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603
+#define PCI_DEVICE_ID_AMD_15H_M10H_F3 0x1403
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e
+#define PCI_DEVICE_ID_AMD_15H_NB_F0 0x1600
+#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
+#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
+#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603
+#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604
+#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605
+#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533
+#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
+#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
+#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A
#define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081
#define PCI_DEVICE_ID_AMD_LX_AES 0x2082
-#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c
#define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800
+#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b
+#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c
#define PCI_VENDOR_ID_TRIDENT 0x1023
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
#define PCI_DEVICE_ID_MATROX_G550 0x2527
#define PCI_DEVICE_ID_MATROX_VIA 0x4536
+#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS 0x14f2
+
#define PCI_VENDOR_ID_CT 0x102c
#define PCI_DEVICE_ID_CT_69000 0x00c0
#define PCI_DEVICE_ID_CT_65545 0x00d8
#define PCI_DEVICE_ID_SI_7018 0x7018
#define PCI_VENDOR_ID_HP 0x103c
+#define PCI_VENDOR_ID_HP_3PAR 0x1590
#define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005
#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006
#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008
#define PCI_DEVICE_ID_HP_CISSD 0x3238
#define PCI_DEVICE_ID_HP_CISSE 0x323a
#define PCI_DEVICE_ID_HP_CISSF 0x323b
+#define PCI_DEVICE_ID_HP_CISSH 0x323c
+#define PCI_DEVICE_ID_HP_CISSI 0x3239
#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031
#define PCI_VENDOR_ID_PCTECH 0x1042
#define PCI_DEVICE_ID_ELSA_QS3000 0x3000
#define PCI_VENDOR_ID_STMICRO 0x104A
+#define PCI_DEVICE_ID_STMICRO_USB_HOST 0xCC00
+#define PCI_DEVICE_ID_STMICRO_USB_OHCI 0xCC01
+#define PCI_DEVICE_ID_STMICRO_USB_OTG 0xCC02
+#define PCI_DEVICE_ID_STMICRO_UART_HWFC 0xCC03
+#define PCI_DEVICE_ID_STMICRO_UART_NO_HWFC 0xCC04
+#define PCI_DEVICE_ID_STMICRO_SOC_DMA 0xCC05
+#define PCI_DEVICE_ID_STMICRO_SATA 0xCC06
+#define PCI_DEVICE_ID_STMICRO_I2C 0xCC07
+#define PCI_DEVICE_ID_STMICRO_SPI_HS 0xCC08
+#define PCI_DEVICE_ID_STMICRO_MAC 0xCC09
+#define PCI_DEVICE_ID_STMICRO_SDIO_EMMC 0xCC0A
+#define PCI_DEVICE_ID_STMICRO_SDIO 0xCC0B
+#define PCI_DEVICE_ID_STMICRO_GPIO 0xCC0C
+#define PCI_DEVICE_ID_STMICRO_VIP 0xCC0D
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA 0xCC0E
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS 0xCC0F
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS 0xCC10
+#define PCI_DEVICE_ID_STMICRO_CAN 0xCC11
+#define PCI_DEVICE_ID_STMICRO_MLB 0xCC12
+#define PCI_DEVICE_ID_STMICRO_DBP 0xCC13
+#define PCI_DEVICE_ID_STMICRO_SATA_PHY 0xCC14
+#define PCI_DEVICE_ID_STMICRO_ESRAM 0xCC15
+#define PCI_DEVICE_ID_STMICRO_VIC 0xCC16
#define PCI_VENDOR_ID_BUSLOGIC 0x104B
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
#define PCI_VENDOR_ID_TUNDRA 0x10e3
#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000
+#define PCI_VENDOR_ID_AMCC 0x10e8
+
#define PCI_VENDOR_ID_INTERG 0x10ea
#define PCI_DEVICE_ID_INTERG_1682 0x1682
#define PCI_DEVICE_ID_INTERG_2000 0x2000
#define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041
#define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042
#define PCI_SUBDEVICE_ID_CREATIVE_SB08803 0x0043
+#define PCI_SUBDEVICE_ID_CREATIVE_SB1270 0x0062
#define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX 0x6000
#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */
#define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581
#define PCI_DEVICE_ID_VIA_VX800 0x8353
#define PCI_DEVICE_ID_VIA_VX855 0x8409
+#define PCI_DEVICE_ID_VIA_VX900 0x8410
#define PCI_DEVICE_ID_VIA_8371_1 0x8391
#define PCI_DEVICE_ID_VIA_82C598_1 0x8598
#define PCI_DEVICE_ID_VIA_838X_1 0xB188
#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476
#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478
#define PCI_DEVICE_ID_RICOH_R5C822 0x0822
+#define PCI_DEVICE_ID_RICOH_R5CE822 0xe822
+#define PCI_DEVICE_ID_RICOH_R5CE823 0xe823
#define PCI_DEVICE_ID_RICOH_R5C832 0x0832
#define PCI_DEVICE_ID_RICOH_R5C843 0x0843
#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334
#define PCI_VENDOR_ID_MARVELL 0x11ab
+#define PCI_VENDOR_ID_MARVELL_EXT 0x1b4b
#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146
#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430
#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460
#define PCI_VENDOR_ID_ESDGMBH 0x12fe
#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
+#define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */
+
#define PCI_VENDOR_ID_SIIG 0x131f
#define PCI_SUBVENDOR_ID_SIIG 0x131f
#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
#define PCI_VENDOR_ID_QUATECH 0x135C
#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010
#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020
+#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030
+#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040
#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050
#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060
+#define PCI_DEVICE_ID_QUATECH_QSCP100 0x0120
+#define PCI_DEVICE_ID_QUATECH_DSCP100 0x0130
+#define PCI_DEVICE_ID_QUATECH_QSCP200 0x0140
+#define PCI_DEVICE_ID_QUATECH_DSCP200 0x0150
+#define PCI_DEVICE_ID_QUATECH_QSCLP100 0x0170
+#define PCI_DEVICE_ID_QUATECH_DSCLP100 0x0180
+#define PCI_DEVICE_ID_QUATECH_DSC100E 0x0181
+#define PCI_DEVICE_ID_QUATECH_SSCLP100 0x0190
+#define PCI_DEVICE_ID_QUATECH_QSCLP200 0x01A0
+#define PCI_DEVICE_ID_QUATECH_DSCLP200 0x01B0
+#define PCI_DEVICE_ID_QUATECH_DSC200E 0x01B1
+#define PCI_DEVICE_ID_QUATECH_SSCLP200 0x01C0
+#define PCI_DEVICE_ID_QUATECH_ESCLP100 0x01E0
#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278
#define PCI_VENDOR_ID_SEALEVEL 0x135e
#define PCI_DEVICE_ID_EXAR_XR17C152 0x0152
#define PCI_DEVICE_ID_EXAR_XR17C154 0x0154
#define PCI_DEVICE_ID_EXAR_XR17C158 0x0158
+#define PCI_DEVICE_ID_EXAR_XR17V352 0x0352
+#define PCI_DEVICE_ID_EXAR_XR17V354 0x0354
+#define PCI_DEVICE_ID_EXAR_XR17V358 0x0358
#define PCI_VENDOR_ID_MICROGATE 0x13c0
#define PCI_DEVICE_ID_MICROGATE_USC 0x0010
#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
+#define PCI_VENDOR_ID_ADVANTECH 0x13fe
+
+#define PCI_VENDOR_ID_MEILHAUS 0x1402
+
#define PCI_VENDOR_ID_LAVA 0x1407
#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */
#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */
#define PCI_VENDOR_ID_CHELSIO 0x1425
+#define PCI_VENDOR_ID_ADLINK 0x144a
+
#define PCI_VENDOR_ID_SAMSUNG 0x144d
#define PCI_VENDOR_ID_GIGABYTE 0x1458
#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
#define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
+#define PCI_VENDOR_ID_AMPLICON 0x14dc
+
#define PCI_VENDOR_ID_BCM_GVC 0x14a4
#define PCI_VENDOR_ID_BROADCOM 0x14e4
#define PCI_DEVICE_ID_TIGON3_5752 0x1600
#define PCI_DEVICE_ID_NX2_57711E 0x1650
#define PCI_DEVICE_ID_TIGON3_5705 0x1653
#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
+#define PCI_DEVICE_ID_TIGON3_5719 0x1657
#define PCI_DEVICE_ID_TIGON3_5721 0x1659
#define PCI_DEVICE_ID_TIGON3_5722 0x165a
#define PCI_DEVICE_ID_TIGON3_5723 0x165b
#define PCI_DEVICE_ID_TIGON3_5705M 0x165d
#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
+#define PCI_DEVICE_ID_NX2_57712 0x1662
+#define PCI_DEVICE_ID_NX2_57712E 0x1663
+#define PCI_DEVICE_ID_NX2_57712_MF 0x1663
#define PCI_DEVICE_ID_TIGON3_5714 0x1668
#define PCI_DEVICE_ID_TIGON3_5714S 0x1669
#define PCI_DEVICE_ID_TIGON3_5780 0x166a
#define PCI_DEVICE_ID_TIGON3_5780S 0x166b
#define PCI_DEVICE_ID_TIGON3_5705F 0x166e
+#define PCI_DEVICE_ID_NX2_57712_VF 0x166f
#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
#define PCI_DEVICE_ID_TIGON3_5756 0x1674
+#define PCI_DEVICE_ID_TIGON3_5750 0x1676
#define PCI_DEVICE_ID_TIGON3_5751 0x1677
#define PCI_DEVICE_ID_TIGON3_5715 0x1678
#define PCI_DEVICE_ID_TIGON3_5715S 0x1679
#define PCI_DEVICE_ID_TIGON3_5761E 0x1680
#define PCI_DEVICE_ID_TIGON3_5761 0x1681
#define PCI_DEVICE_ID_TIGON3_5764 0x1684
+#define PCI_DEVICE_ID_NX2_57800 0x168a
+#define PCI_DEVICE_ID_NX2_57840 0x168d
+#define PCI_DEVICE_ID_NX2_57810 0x168e
#define PCI_DEVICE_ID_TIGON3_5787M 0x1693
#define PCI_DEVICE_ID_TIGON3_5782 0x1696
#define PCI_DEVICE_ID_TIGON3_5784 0x1698
#define PCI_DEVICE_ID_TIGON3_5787 0x169b
#define PCI_DEVICE_ID_TIGON3_5788 0x169c
#define PCI_DEVICE_ID_TIGON3_5789 0x169d
+#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1
+#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2
+#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4
+#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5
#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
+#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9
#define PCI_DEVICE_ID_NX2_5706S 0x16aa
#define PCI_DEVICE_ID_NX2_5708S 0x16ac
+#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad
+#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae
+#define PCI_DEVICE_ID_NX2_57810_VF 0x16af
#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
#define PCI_DEVICE_ID_TIGON3_5781 0x16dd
#define PCI_VENDOR_ID_TOPSPIN 0x1867
+#define PCI_VENDOR_ID_COMMTECH 0x18f7
+
#define PCI_VENDOR_ID_SILAN 0x1904
#define PCI_VENDOR_ID_RENESAS 0x1912
#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
#define PCI_DEVICE_ID_RENESAS_SH7786 0x0010
+#define PCI_VENDOR_ID_SOLARFLARE 0x1924
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0 0x0703
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1 0x6703
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B 0x0710
+
#define PCI_VENDOR_ID_TDI 0x192E
#define PCI_DEVICE_ID_TDI_EHCI 0x0101
#define PCI_VENDOR_ID_AZWAVE 0x1a3b
+#define PCI_VENDOR_ID_ASMEDIA 0x1b21
+
+#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
+#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
+
#define PCI_VENDOR_ID_TEKRAM 0x1de1
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_EESSC 0x0008
+#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
+#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
+#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320
#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321
#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329
#define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
+#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA 0x1c20
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68 0x1c44
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67 0x1c46
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67 0x1c47
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65 0x1c49
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67 0x1c4a
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67 0x1c4b
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65 0x1c4c
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67 0x1c4d
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67 0x1c4e
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67 0x1c4f
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65 0x1c50
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202 0x1c52
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204 0x1c54
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206 0x1c56
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61 0x1c5c
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI 0x1e31
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_B75 0x1e49
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_C216 0x1e53
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_H77 0x1e4A
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM70 0x1e5e
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM75 0x1e5d
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM76 0x1e59
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM77 0x1e57
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MBL_SAMPLE 0x1e42
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_NM70 0x1e5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q75 0x1e48
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q77 0x1e47
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QM77 0x1e55
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QS77 0x1e56
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_SFF_SAMPLE 0x1e43
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_UM77 0x1e58
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z75 0x1e46
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z77 0x1e44
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
+#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310
+#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX 0x231f
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411
#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f
+#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46
+#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0
+#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1
+#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4
+#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5
+#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41
+#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42
+#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43
+#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44
+#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
+#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0
#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
+#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3
#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
#define PCI_DEVICE_ID_INTEL_5100_22 0x65f6
#define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030
#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601
#define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119
#define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a
+#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186
#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4
#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5
#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca
#define PCI_DEVICE_ID_NETMOS_9845 0x9845
#define PCI_DEVICE_ID_NETMOS_9855 0x9855
#define PCI_DEVICE_ID_NETMOS_9865 0x9865
+#define PCI_DEVICE_ID_NETMOS_9900 0x9900
#define PCI_DEVICE_ID_NETMOS_9901 0x9901
+#define PCI_DEVICE_ID_NETMOS_9904 0x9904
+#define PCI_DEVICE_ID_NETMOS_9912 0x9912
+#define PCI_DEVICE_ID_NETMOS_9922 0x9922
#define PCI_VENDOR_ID_3COM_2 0xa727
#define PCI_VENDOR_ID_XEN 0x5853
#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
+
+#define PCI_VENDOR_ID_OCZ 0x1b85
--- /dev/null
+/*
+ * From coreboot file of same name
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PCI_ROM_H
+#define _PCI_ROM_H
+
+#define PCI_ROM_HDR 0xaa55
+#define PCI_VGA_RAM_IMAGE_START 0xc0000
+
+struct pci_rom_header {
+ uint16_t signature;
+ uint8_t size;
+ uint8_t init[3];
+ uint8_t reserved[0x12];
+ uint16_t data;
+};
+
+struct pci_rom_data {
+ uint32_t signature;
+ uint16_t vendor;
+ uint16_t device;
+ uint16_t reserved_1;
+ uint16_t dlen;
+ uint8_t drevision;
+ uint8_t class_lo;
+ uint16_t class_hi;
+ uint16_t ilen;
+ uint16_t irevision;
+ uint8_t type;
+ uint8_t indicator;
+ uint16_t reserved_2;
+};
+
+ /**
+ * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
+ *
+ * @dev: Video device containing the BIOS
+ * @int15_handler: Function to call to handle int 0x15
+ * @emulate: true to use the x86 emulator, false to run native
+ */
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate);
+
+/**
+ * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
+ *
+ * Some VGA option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ *
+ * @vendev: Vendor and device for the video device
+ * @return standard vendor and device expected by the ROM
+ */
+uint32_t board_map_oprom_vendev(uint32_t vendev);
+
+#endif
unsigned long mktime (unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, unsigned int);
+/**
+ * rtc_init() - Set up the real time clock ready for use
+ */
+void rtc_init(void);
+
#endif /* _RTC_H_ */
/* For initializing power device */
void twl4030_power_init(void);
/* For initializing mmc power */
-void twl4030_power_mmc_init(void);
+void twl4030_power_mmc_init(int dev_index);
/*
* LED
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+#ifndef _VBE_H
+#define _VBE_H
+
+/* these structs are for input from and output to OF */
+struct __packed screen_info {
+ u8 display_type; /* 0=NONE, 1= analog, 2=digital */
+ u16 screen_width;
+ u16 screen_height;
+ /* bytes per line in framebuffer, may be more than screen_width */
+ u16 screen_linebytes;
+ u8 color_depth; /* color depth in bits per pixel */
+ u32 framebuffer_address;
+ u8 edid_block_zero[128];
+};
+
+struct __packed screen_info_input {
+ u8 signature[4];
+ u16 size_reserved;
+ u8 monitor_number;
+ u16 max_screen_width;
+ u8 color_depth;
+};
+
+/* these structs only store the required a subset of the VBE-defined fields */
+struct __packed vbe_info {
+ char signature[4];
+ u16 version;
+ u8 *oem_string_ptr;
+ u32 capabilities;
+ u16 video_mode_list[256];
+ u16 total_memory;
+};
+
+struct __packed vesa_mode_info {
+ u16 mode_attributes; /* 00 */
+ u8 win_a_attributes; /* 02 */
+ u8 win_b_attributes; /* 03 */
+ u16 win_granularity; /* 04 */
+ u16 win_size; /* 06 */
+ u16 win_a_segment; /* 08 */
+ u16 win_b_segment; /* 0a */
+ u32 win_func_ptr; /* 0c */
+ u16 bytes_per_scanline; /* 10 */
+ u16 x_resolution; /* 12 */
+ u16 y_resolution; /* 14 */
+ u8 x_charsize; /* 16 */
+ u8 y_charsize; /* 17 */
+ u8 number_of_planes; /* 18 */
+ u8 bits_per_pixel; /* 19 */
+ u8 number_of_banks; /* 20 */
+ u8 memory_model; /* 21 */
+ u8 bank_size; /* 22 */
+ u8 number_of_image_pages; /* 23 */
+ u8 reserved_page;
+ u8 red_mask_size;
+ u8 red_mask_pos;
+ u8 green_mask_size;
+ u8 green_mask_pos;
+ u8 blue_mask_size;
+ u8 blue_mask_pos;
+ u8 reserved_mask_size;
+ u8 reserved_mask_pos;
+ u8 direct_color_mode_info;
+ u32 phys_base_ptr;
+ u32 offscreen_mem_offset;
+ u16 offscreen_mem_size;
+ u8 reserved[206];
+};
+
+struct vbe_mode_info {
+ u16 video_mode;
+ bool valid;
+ union {
+ struct vesa_mode_info vesa;
+ u8 mode_info_block[256];
+ };
+};
+
+struct vbe_ddc_info {
+ u8 port_number; /* i.e. monitor number */
+ u8 edid_transfer_time;
+ u8 ddc_level;
+ u8 edid_block_zero[128];
+};
+
+#define VESA_GET_INFO 0x4f00
+#define VESA_GET_MODE_INFO 0x4f01
+#define VESA_SET_MODE 0x4f02
+
+struct graphic_device;
+int vbe_get_video_info(struct graphic_device *gdev);
+
+#endif
/* Export Graphic Driver Control */
/******************************************************************************/
-typedef struct {
+typedef struct graphic_device {
unsigned int isaBase;
unsigned int pciBase;
unsigned int dprBase;
obj-$(CONFIG_LZMA) += lzma/
obj-$(CONFIG_LZO) += lzo/
obj-$(CONFIG_ZLIB) += zlib/
+obj-$(CONFIG_BZIP2) += bzip2/
obj-$(CONFIG_TIZEN) += tizen/
+obj-$(CONFIG_OF_LIBFDT) += libfdt/
+obj-$(CONFIG_FIT) += libfdt/
obj-$(CONFIG_AES) += aes.o
-obj-$(CONFIG_BZIP2) += bzlib.o
-obj-$(CONFIG_BZIP2) += bzlib_crctable.o
-obj-$(CONFIG_BZIP2) += bzlib_decompress.o
-obj-$(CONFIG_BZIP2) += bzlib_randtable.o
-obj-$(CONFIG_BZIP2) += bzlib_huffman.o
obj-$(CONFIG_USB_TTY) += circbuf.o
obj-y += crc7.o
obj-y += crc8.o
--- /dev/null
+obj-y += bzlib.o bzlib_crctable.o bzlib_decompress.o \
+ bzlib_randtable.o bzlib_huffman.o
--- /dev/null
+#include <config.h>
+#include <common.h>
+#include <watchdog.h>
+
+/*
+ * This file is a modified version of bzlib.c from the bzip2-1.0.2
+ * distribution which can be found at http://sources.redhat.com/bzip2/
+ */
+
+/*-------------------------------------------------------------*/
+/*--- Library top-level functions. ---*/
+/*--- bzlib.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+ This file is a part of bzip2 and/or libbzip2, a program and
+ library for lossless, block-sorting data compression.
+
+ Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+ 3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+ 4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Julian Seward, Cambridge, UK.
+ jseward@acm.org
+ bzip2/libbzip2 version 1.0 of 21 March 2000
+
+ This program is based on (at least) the work of:
+ Mike Burrows
+ David Wheeler
+ Peter Fenwick
+ Alistair Moffat
+ Radford Neal
+ Ian H. Witten
+ Robert Sedgewick
+ Jon L. Bentley
+
+ For more information on these sources, see the manual.
+--*/
+
+/*--
+ CHANGES
+ ~~~~~~~
+ 0.9.0 -- original version.
+
+ 0.9.0a/b -- no changes in this file.
+
+ 0.9.0c
+ * made zero-length BZ_FLUSH work correctly in bzCompress().
+ * fixed bzWrite/bzRead to ignore zero-length requests.
+ * fixed bzread to correctly handle read requests after EOF.
+ * wrong parameter order in call to bzDecompressInit in
+ bzBuffToBuffDecompress. Fixed.
+--*/
+
+#include "bzlib_private.h"
+
+/*---------------------------------------------------*/
+/*--- Compression stuff ---*/
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+#ifndef BZ_NO_STDIO
+void BZ2_bz__AssertH__fail ( int errcode )
+{
+ fprintf(stderr,
+ "\n\nbzip2/libbzip2: internal error number %d.\n"
+ "This is a bug in bzip2/libbzip2, %s.\n"
+ "Please report it to me at: jseward@acm.org. If this happened\n"
+ "when you were using some program which uses libbzip2 as a\n"
+ "component, you should also report this bug to the author(s)\n"
+ "of that program. Please make an effort to report this bug;\n"
+ "timely and accurate bug reports eventually lead to higher\n"
+ "quality software. Thanks. Julian Seward, 30 December 2001.\n\n",
+ errcode,
+ BZ2_bzlibVersion()
+ );
+
+ if (errcode == 1007) {
+ fprintf(stderr,
+ "\n*** A special note about internal error number 1007 ***\n"
+ "\n"
+ "Experience suggests that a common cause of i.e. 1007\n"
+ "is unreliable memory or other hardware. The 1007 assertion\n"
+ "just happens to cross-check the results of huge numbers of\n"
+ "memory reads/writes, and so acts (unintendedly) as a stress\n"
+ "test of your memory system.\n"
+ "\n"
+ "I suggest the following: try compressing the file again,\n"
+ "possibly monitoring progress in detail with the -vv flag.\n"
+ "\n"
+ "* If the error cannot be reproduced, and/or happens at different\n"
+ " points in compression, you may have a flaky memory system.\n"
+ " Try a memory-test program. I have used Memtest86\n"
+ " (www.memtest86.com). At the time of writing it is free (GPLd).\n"
+ " Memtest86 tests memory much more thorougly than your BIOSs\n"
+ " power-on test, and may find failures that the BIOS doesn't.\n"
+ "\n"
+ "* If the error can be repeatably reproduced, this is a bug in\n"
+ " bzip2, and I would very much like to hear about it. Please\n"
+ " let me know, and, ideally, save a copy of the file causing the\n"
+ " problem -- without which I will be unable to investigate it.\n"
+ "\n"
+ );
+ }
+
+ exit(3);
+}
+#endif
+
+
+/*---------------------------------------------------*/
+static
+int bz_config_ok ( void )
+{
+ if (sizeof(int) != 4) return 0;
+ if (sizeof(short) != 2) return 0;
+ if (sizeof(char) != 1) return 0;
+ return 1;
+}
+
+
+/*---------------------------------------------------*/
+static
+void* default_bzalloc ( void* opaque, Int32 items, Int32 size )
+{
+ void* v = malloc ( items * size );
+ return v;
+}
+
+static
+void default_bzfree ( void* opaque, void* addr )
+{
+ if (addr != NULL) free ( addr );
+}
+
+#ifndef BZ_NO_COMPRESS
+/*---------------------------------------------------*/
+static
+void prepare_new_block ( EState* s )
+{
+ Int32 i;
+ s->nblock = 0;
+ s->numZ = 0;
+ s->state_out_pos = 0;
+ BZ_INITIALISE_CRC ( s->blockCRC );
+ for (i = 0; i < 256; i++) s->inUse[i] = False;
+ s->blockNo++;
+}
+
+
+/*---------------------------------------------------*/
+static
+void init_RL ( EState* s )
+{
+ s->state_in_ch = 256;
+ s->state_in_len = 0;
+}
+
+
+static
+Bool isempty_RL ( EState* s )
+{
+ if (s->state_in_ch < 256 && s->state_in_len > 0)
+ return False; else
+ return True;
+}
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzCompressInit)
+ ( bz_stream* strm,
+ int blockSize100k,
+ int verbosity,
+ int workFactor )
+{
+ Int32 n;
+ EState* s;
+
+ if (!bz_config_ok()) return BZ_CONFIG_ERROR;
+
+ if (strm == NULL ||
+ blockSize100k < 1 || blockSize100k > 9 ||
+ workFactor < 0 || workFactor > 250)
+ return BZ_PARAM_ERROR;
+
+ if (workFactor == 0) workFactor = 30;
+ if (strm->bzalloc == NULL) strm->bzalloc = default_bzalloc;
+ if (strm->bzfree == NULL) strm->bzfree = default_bzfree;
+
+ s = BZALLOC( sizeof(EState) );
+ if (s == NULL) return BZ_MEM_ERROR;
+ s->strm = strm;
+
+ s->arr1 = NULL;
+ s->arr2 = NULL;
+ s->ftab = NULL;
+
+ n = 100000 * blockSize100k;
+ s->arr1 = BZALLOC( n * sizeof(UInt32) );
+ s->arr2 = BZALLOC( (n+BZ_N_OVERSHOOT) * sizeof(UInt32) );
+ s->ftab = BZALLOC( 65537 * sizeof(UInt32) );
+
+ if (s->arr1 == NULL || s->arr2 == NULL || s->ftab == NULL) {
+ if (s->arr1 != NULL) BZFREE(s->arr1);
+ if (s->arr2 != NULL) BZFREE(s->arr2);
+ if (s->ftab != NULL) BZFREE(s->ftab);
+ if (s != NULL) BZFREE(s);
+ return BZ_MEM_ERROR;
+ }
+
+ s->blockNo = 0;
+ s->state = BZ_S_INPUT;
+ s->mode = BZ_M_RUNNING;
+ s->combinedCRC = 0;
+ s->blockSize100k = blockSize100k;
+ s->nblockMAX = 100000 * blockSize100k - 19;
+ s->verbosity = verbosity;
+ s->workFactor = workFactor;
+
+ s->block = (UChar*)s->arr2;
+ s->mtfv = (UInt16*)s->arr1;
+ s->zbits = NULL;
+ s->ptr = (UInt32*)s->arr1;
+
+ strm->state = s;
+ strm->total_in_lo32 = 0;
+ strm->total_in_hi32 = 0;
+ strm->total_out_lo32 = 0;
+ strm->total_out_hi32 = 0;
+ init_RL ( s );
+ prepare_new_block ( s );
+ return BZ_OK;
+}
+
+
+/*---------------------------------------------------*/
+static
+void add_pair_to_block ( EState* s )
+{
+ Int32 i;
+ UChar ch = (UChar)(s->state_in_ch);
+ for (i = 0; i < s->state_in_len; i++) {
+ BZ_UPDATE_CRC( s->blockCRC, ch );
+ }
+ s->inUse[s->state_in_ch] = True;
+ switch (s->state_in_len) {
+ case 1:
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ break;
+ case 2:
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ break;
+ case 3:
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ break;
+ default:
+ s->inUse[s->state_in_len-4] = True;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = ((UChar)(s->state_in_len-4));
+ s->nblock++;
+ break;
+ }
+}
+
+
+/*---------------------------------------------------*/
+static
+void flush_RL ( EState* s )
+{
+ if (s->state_in_ch < 256) add_pair_to_block ( s );
+ init_RL ( s );
+}
+
+
+/*---------------------------------------------------*/
+#define ADD_CHAR_TO_BLOCK(zs,zchh0) \
+{ \
+ UInt32 zchh = (UInt32)(zchh0); \
+ /*-- fast track the common case --*/ \
+ if (zchh != zs->state_in_ch && \
+ zs->state_in_len == 1) { \
+ UChar ch = (UChar)(zs->state_in_ch); \
+ BZ_UPDATE_CRC( zs->blockCRC, ch ); \
+ zs->inUse[zs->state_in_ch] = True; \
+ zs->block[zs->nblock] = (UChar)ch; \
+ zs->nblock++; \
+ zs->state_in_ch = zchh; \
+ } \
+ else \
+ /*-- general, uncommon cases --*/ \
+ if (zchh != zs->state_in_ch || \
+ zs->state_in_len == 255) { \
+ if (zs->state_in_ch < 256) \
+ add_pair_to_block ( zs ); \
+ zs->state_in_ch = zchh; \
+ zs->state_in_len = 1; \
+ } else { \
+ zs->state_in_len++; \
+ } \
+}
+
+
+/*---------------------------------------------------*/
+static
+Bool copy_input_until_stop ( EState* s )
+{
+ Bool progress_in = False;
+
+ if (s->mode == BZ_M_RUNNING) {
+
+ /*-- fast track the common case --*/
+ while (True) {
+ /*-- block full? --*/
+ if (s->nblock >= s->nblockMAX) break;
+ /*-- no input? --*/
+ if (s->strm->avail_in == 0) break;
+ progress_in = True;
+ ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) );
+ s->strm->next_in++;
+ s->strm->avail_in--;
+ s->strm->total_in_lo32++;
+ if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++;
+ }
+
+ } else {
+
+ /*-- general, uncommon case --*/
+ while (True) {
+ /*-- block full? --*/
+ if (s->nblock >= s->nblockMAX) break;
+ /*-- no input? --*/
+ if (s->strm->avail_in == 0) break;
+ /*-- flush/finish end? --*/
+ if (s->avail_in_expect == 0) break;
+ progress_in = True;
+ ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) );
+ s->strm->next_in++;
+ s->strm->avail_in--;
+ s->strm->total_in_lo32++;
+ if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++;
+ s->avail_in_expect--;
+ }
+ }
+ return progress_in;
+}
+
+
+/*---------------------------------------------------*/
+static
+Bool copy_output_until_stop ( EState* s )
+{
+ Bool progress_out = False;
+
+ while (True) {
+
+ /*-- no output space? --*/
+ if (s->strm->avail_out == 0) break;
+
+ /*-- block done? --*/
+ if (s->state_out_pos >= s->numZ) break;
+
+ progress_out = True;
+ *(s->strm->next_out) = s->zbits[s->state_out_pos];
+ s->state_out_pos++;
+ s->strm->avail_out--;
+ s->strm->next_out++;
+ s->strm->total_out_lo32++;
+ if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
+ }
+
+ return progress_out;
+}
+
+
+/*---------------------------------------------------*/
+static
+Bool handle_compress ( bz_stream* strm )
+{
+ Bool progress_in = False;
+ Bool progress_out = False;
+ EState* s = strm->state;
+
+ while (True) {
+
+ if (s->state == BZ_S_OUTPUT) {
+ progress_out |= copy_output_until_stop ( s );
+ if (s->state_out_pos < s->numZ) break;
+ if (s->mode == BZ_M_FINISHING &&
+ s->avail_in_expect == 0 &&
+ isempty_RL(s)) break;
+ prepare_new_block ( s );
+ s->state = BZ_S_INPUT;
+ if (s->mode == BZ_M_FLUSHING &&
+ s->avail_in_expect == 0 &&
+ isempty_RL(s)) break;
+ }
+
+ if (s->state == BZ_S_INPUT) {
+ progress_in |= copy_input_until_stop ( s );
+ if (s->mode != BZ_M_RUNNING && s->avail_in_expect == 0) {
+ flush_RL ( s );
+ BZ2_compressBlock ( s, (Bool)(s->mode == BZ_M_FINISHING) );
+ s->state = BZ_S_OUTPUT;
+ }
+ else
+ if (s->nblock >= s->nblockMAX) {
+ BZ2_compressBlock ( s, False );
+ s->state = BZ_S_OUTPUT;
+ }
+ else
+ if (s->strm->avail_in == 0) {
+ break;
+ }
+ }
+
+ }
+
+ return progress_in || progress_out;
+}
+
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzCompress) ( bz_stream *strm, int action )
+{
+ Bool progress;
+ EState* s;
+ if (strm == NULL) return BZ_PARAM_ERROR;
+ s = strm->state;
+ if (s == NULL) return BZ_PARAM_ERROR;
+ if (s->strm != strm) return BZ_PARAM_ERROR;
+
+ preswitch:
+ switch (s->mode) {
+
+ case BZ_M_IDLE:
+ return BZ_SEQUENCE_ERROR;
+
+ case BZ_M_RUNNING:
+ if (action == BZ_RUN) {
+ progress = handle_compress ( strm );
+ return progress ? BZ_RUN_OK : BZ_PARAM_ERROR;
+ }
+ else
+ if (action == BZ_FLUSH) {
+ s->avail_in_expect = strm->avail_in;
+ s->mode = BZ_M_FLUSHING;
+ goto preswitch;
+ }
+ else
+ if (action == BZ_FINISH) {
+ s->avail_in_expect = strm->avail_in;
+ s->mode = BZ_M_FINISHING;
+ goto preswitch;
+ }
+ else
+ return BZ_PARAM_ERROR;
+
+ case BZ_M_FLUSHING:
+ if (action != BZ_FLUSH) return BZ_SEQUENCE_ERROR;
+ if (s->avail_in_expect != s->strm->avail_in)
+ return BZ_SEQUENCE_ERROR;
+ progress = handle_compress ( strm );
+ if (s->avail_in_expect > 0 || !isempty_RL(s) ||
+ s->state_out_pos < s->numZ) return BZ_FLUSH_OK;
+ s->mode = BZ_M_RUNNING;
+ return BZ_RUN_OK;
+
+ case BZ_M_FINISHING:
+ if (action != BZ_FINISH) return BZ_SEQUENCE_ERROR;
+ if (s->avail_in_expect != s->strm->avail_in)
+ return BZ_SEQUENCE_ERROR;
+ progress = handle_compress ( strm );
+ if (!progress) return BZ_SEQUENCE_ERROR;
+ if (s->avail_in_expect > 0 || !isempty_RL(s) ||
+ s->state_out_pos < s->numZ) return BZ_FINISH_OK;
+ s->mode = BZ_M_IDLE;
+ return BZ_STREAM_END;
+ }
+ return BZ_OK; /*--not reached--*/
+}
+
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzCompressEnd) ( bz_stream *strm )
+{
+ EState* s;
+ if (strm == NULL) return BZ_PARAM_ERROR;
+ s = strm->state;
+ if (s == NULL) return BZ_PARAM_ERROR;
+ if (s->strm != strm) return BZ_PARAM_ERROR;
+
+ if (s->arr1 != NULL) BZFREE(s->arr1);
+ if (s->arr2 != NULL) BZFREE(s->arr2);
+ if (s->ftab != NULL) BZFREE(s->ftab);
+ BZFREE(strm->state);
+
+ strm->state = NULL;
+
+ return BZ_OK;
+}
+#endif /* BZ_NO_COMPRESS */
+
+/*---------------------------------------------------*/
+/*--- Decompression stuff ---*/
+/*---------------------------------------------------*/
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzDecompressInit)
+ ( bz_stream* strm,
+ int verbosity,
+ int small )
+{
+ DState* s;
+
+ if (!bz_config_ok()) return BZ_CONFIG_ERROR;
+
+ if (strm == NULL) return BZ_PARAM_ERROR;
+ if (small != 0 && small != 1) return BZ_PARAM_ERROR;
+ if (verbosity < 0 || verbosity > 4) return BZ_PARAM_ERROR;
+
+ if (strm->bzalloc == NULL) strm->bzalloc = default_bzalloc;
+ if (strm->bzfree == NULL) strm->bzfree = default_bzfree;
+
+ s = BZALLOC( sizeof(DState) );
+ if (s == NULL) return BZ_MEM_ERROR;
+ s->strm = strm;
+ strm->state = s;
+ s->state = BZ_X_MAGIC_1;
+ s->bsLive = 0;
+ s->bsBuff = 0;
+ s->calculatedCombinedCRC = 0;
+ strm->total_in_lo32 = 0;
+ strm->total_in_hi32 = 0;
+ strm->total_out_lo32 = 0;
+ strm->total_out_hi32 = 0;
+ s->smallDecompress = (Bool)small;
+ s->ll4 = NULL;
+ s->ll16 = NULL;
+ s->tt = NULL;
+ s->currBlockNo = 0;
+ s->verbosity = verbosity;
+
+ return BZ_OK;
+}
+
+
+/*---------------------------------------------------*/
+static
+void unRLE_obuf_to_output_FAST ( DState* s )
+{
+ UChar k1;
+
+ if (s->blockRandomised) {
+
+ while (True) {
+ /* try to finish existing run */
+ while (True) {
+ if (s->strm->avail_out == 0) return;
+ if (s->state_out_len == 0) break;
+ *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
+ BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
+ s->state_out_len--;
+ s->strm->next_out++;
+ s->strm->avail_out--;
+ s->strm->total_out_lo32++;
+ if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
+ }
+
+ /* can a new run be started? */
+ if (s->nblock_used == s->save_nblock+1) return;
+
+
+ s->state_out_len = 1;
+ s->state_out_ch = s->k0;
+ BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 2;
+ BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 3;
+ BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ s->state_out_len = ((Int32)k1) + 4;
+ BZ_GET_FAST(s->k0); BZ_RAND_UPD_MASK;
+ s->k0 ^= BZ_RAND_MASK; s->nblock_used++;
+ }
+
+ } else {
+
+ /* restore */
+ UInt32 c_calculatedBlockCRC = s->calculatedBlockCRC;
+ UChar c_state_out_ch = s->state_out_ch;
+ Int32 c_state_out_len = s->state_out_len;
+ Int32 c_nblock_used = s->nblock_used;
+ Int32 c_k0 = s->k0;
+ UInt32* c_tt = s->tt;
+ UInt32 c_tPos = s->tPos;
+ char* cs_next_out = s->strm->next_out;
+ unsigned int cs_avail_out = s->strm->avail_out;
+ /* end restore */
+
+ UInt32 avail_out_INIT = cs_avail_out;
+ Int32 s_save_nblockPP = s->save_nblock+1;
+ unsigned int total_out_lo32_old;
+
+ while (True) {
+
+ /* try to finish existing run */
+ if (c_state_out_len > 0) {
+ while (True) {
+ if (cs_avail_out == 0) goto return_notr;
+ if (c_state_out_len == 1) break;
+ *( (UChar*)(cs_next_out) ) = c_state_out_ch;
+ BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch );
+ c_state_out_len--;
+ cs_next_out++;
+ cs_avail_out--;
+ }
+ s_state_out_len_eq_one:
+ {
+ if (cs_avail_out == 0) {
+ c_state_out_len = 1; goto return_notr;
+ };
+ *( (UChar*)(cs_next_out) ) = c_state_out_ch;
+ BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch );
+ cs_next_out++;
+ cs_avail_out--;
+ }
+ }
+ /* can a new run be started? */
+ if (c_nblock_used == s_save_nblockPP) {
+ c_state_out_len = 0; goto return_notr;
+ };
+ c_state_out_ch = c_k0;
+ BZ_GET_FAST_C(k1); c_nblock_used++;
+ if (k1 != c_k0) {
+ c_k0 = k1; goto s_state_out_len_eq_one;
+ };
+ if (c_nblock_used == s_save_nblockPP)
+ goto s_state_out_len_eq_one;
+
+ c_state_out_len = 2;
+ BZ_GET_FAST_C(k1); c_nblock_used++;
+ if (c_nblock_used == s_save_nblockPP) continue;
+ if (k1 != c_k0) { c_k0 = k1; continue; };
+
+ c_state_out_len = 3;
+ BZ_GET_FAST_C(k1); c_nblock_used++;
+ if (c_nblock_used == s_save_nblockPP) continue;
+ if (k1 != c_k0) { c_k0 = k1; continue; };
+
+ BZ_GET_FAST_C(k1); c_nblock_used++;
+ c_state_out_len = ((Int32)k1) + 4;
+ BZ_GET_FAST_C(c_k0); c_nblock_used++;
+ }
+
+ return_notr:
+ total_out_lo32_old = s->strm->total_out_lo32;
+ s->strm->total_out_lo32 += (avail_out_INIT - cs_avail_out);
+ if (s->strm->total_out_lo32 < total_out_lo32_old)
+ s->strm->total_out_hi32++;
+
+ /* save */
+ s->calculatedBlockCRC = c_calculatedBlockCRC;
+ s->state_out_ch = c_state_out_ch;
+ s->state_out_len = c_state_out_len;
+ s->nblock_used = c_nblock_used;
+ s->k0 = c_k0;
+ s->tt = c_tt;
+ s->tPos = c_tPos;
+ s->strm->next_out = cs_next_out;
+ s->strm->avail_out = cs_avail_out;
+ /* end save */
+ }
+}
+
+
+/*---------------------------------------------------*/
+__inline__ Int32 BZ2_indexIntoF ( Int32 indx, Int32 *cftab )
+{
+ Int32 nb, na, mid;
+ nb = 0;
+ na = 256;
+ do {
+ mid = (nb + na) >> 1;
+ if (indx >= cftab[mid]) nb = mid; else na = mid;
+ }
+ while (na - nb != 1);
+ return nb;
+}
+
+
+/*---------------------------------------------------*/
+static
+void unRLE_obuf_to_output_SMALL ( DState* s )
+{
+ UChar k1;
+
+ if (s->blockRandomised) {
+
+ while (True) {
+ /* try to finish existing run */
+ while (True) {
+ if (s->strm->avail_out == 0) return;
+ if (s->state_out_len == 0) break;
+ *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
+ BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
+ s->state_out_len--;
+ s->strm->next_out++;
+ s->strm->avail_out--;
+ s->strm->total_out_lo32++;
+ if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
+ }
+
+ /* can a new run be started? */
+ if (s->nblock_used == s->save_nblock+1) return;
+
+
+ s->state_out_len = 1;
+ s->state_out_ch = s->k0;
+ BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 2;
+ BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 3;
+ BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ s->state_out_len = ((Int32)k1) + 4;
+ BZ_GET_SMALL(s->k0); BZ_RAND_UPD_MASK;
+ s->k0 ^= BZ_RAND_MASK; s->nblock_used++;
+ }
+
+ } else {
+
+ while (True) {
+ /* try to finish existing run */
+ while (True) {
+ if (s->strm->avail_out == 0) return;
+ if (s->state_out_len == 0) break;
+ *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
+ BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
+ s->state_out_len--;
+ s->strm->next_out++;
+ s->strm->avail_out--;
+ s->strm->total_out_lo32++;
+ if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
+ }
+
+ /* can a new run be started? */
+ if (s->nblock_used == s->save_nblock+1) return;
+
+ s->state_out_len = 1;
+ s->state_out_ch = s->k0;
+ BZ_GET_SMALL(k1); s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 2;
+ BZ_GET_SMALL(k1); s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 3;
+ BZ_GET_SMALL(k1); s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ BZ_GET_SMALL(k1); s->nblock_used++;
+ s->state_out_len = ((Int32)k1) + 4;
+ BZ_GET_SMALL(s->k0); s->nblock_used++;
+ }
+
+ }
+}
+
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzDecompress) ( bz_stream *strm )
+{
+ DState* s;
+ if (strm == NULL) return BZ_PARAM_ERROR;
+ s = strm->state;
+ if (s == NULL) return BZ_PARAM_ERROR;
+ if (s->strm != strm) return BZ_PARAM_ERROR;
+
+ while (True) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+ if (s->state == BZ_X_IDLE) return BZ_SEQUENCE_ERROR;
+ if (s->state == BZ_X_OUTPUT) {
+ if (s->smallDecompress)
+ unRLE_obuf_to_output_SMALL ( s ); else
+ unRLE_obuf_to_output_FAST ( s );
+ if (s->nblock_used == s->save_nblock+1 && s->state_out_len == 0) {
+ BZ_FINALISE_CRC ( s->calculatedBlockCRC );
+ if (s->verbosity >= 3)
+ VPrintf2 ( " {0x%x, 0x%x}", s->storedBlockCRC,
+ s->calculatedBlockCRC );
+ if (s->verbosity >= 2) VPrintf0 ( "]" );
+ if (s->calculatedBlockCRC != s->storedBlockCRC)
+ return BZ_DATA_ERROR;
+ s->calculatedCombinedCRC
+ = (s->calculatedCombinedCRC << 1) |
+ (s->calculatedCombinedCRC >> 31);
+ s->calculatedCombinedCRC ^= s->calculatedBlockCRC;
+ s->state = BZ_X_BLKHDR_1;
+ } else {
+ return BZ_OK;
+ }
+ }
+ if (s->state >= BZ_X_MAGIC_1) {
+ Int32 r = BZ2_decompress ( s );
+ if (r == BZ_STREAM_END) {
+ if (s->verbosity >= 3)
+ VPrintf2 ( "\n combined CRCs: stored = 0x%x, computed = 0x%x",
+ s->storedCombinedCRC, s->calculatedCombinedCRC );
+ if (s->calculatedCombinedCRC != s->storedCombinedCRC)
+ return BZ_DATA_ERROR;
+ return r;
+ }
+ if (s->state != BZ_X_OUTPUT) return r;
+ }
+ }
+
+ AssertH ( 0, 6001 );
+
+ return 0; /*NOTREACHED*/
+}
+
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzDecompressEnd) ( bz_stream *strm )
+{
+ DState* s;
+ if (strm == NULL) return BZ_PARAM_ERROR;
+ s = strm->state;
+ if (s == NULL) return BZ_PARAM_ERROR;
+ if (s->strm != strm) return BZ_PARAM_ERROR;
+
+ if (s->tt != NULL) BZFREE(s->tt);
+ if (s->ll16 != NULL) BZFREE(s->ll16);
+ if (s->ll4 != NULL) BZFREE(s->ll4);
+
+ BZFREE(strm->state);
+ strm->state = NULL;
+
+ return BZ_OK;
+}
+
+
+#ifndef BZ_NO_STDIO
+/*---------------------------------------------------*/
+/*--- File I/O stuff ---*/
+/*---------------------------------------------------*/
+
+#define BZ_SETERR(eee) \
+{ \
+ if (bzerror != NULL) *bzerror = eee; \
+ if (bzf != NULL) bzf->lastErr = eee; \
+}
+
+typedef
+ struct {
+ FILE* handle;
+ Char buf[BZ_MAX_UNUSED];
+ Int32 bufN;
+ Bool writing;
+ bz_stream strm;
+ Int32 lastErr;
+ Bool initialisedOk;
+ }
+ bzFile;
+
+
+/*---------------------------------------------*/
+static Bool myfeof ( FILE* f )
+{
+ Int32 c = fgetc ( f );
+ if (c == EOF) return True;
+ ungetc ( c, f );
+ return False;
+}
+
+
+/*---------------------------------------------------*/
+BZFILE* BZ_API(BZ2_bzWriteOpen)
+ ( int* bzerror,
+ FILE* f,
+ int blockSize100k,
+ int verbosity,
+ int workFactor )
+{
+ Int32 ret;
+ bzFile* bzf = NULL;
+
+ BZ_SETERR(BZ_OK);
+
+ if (f == NULL ||
+ (blockSize100k < 1 || blockSize100k > 9) ||
+ (workFactor < 0 || workFactor > 250) ||
+ (verbosity < 0 || verbosity > 4))
+ { BZ_SETERR(BZ_PARAM_ERROR); return NULL; };
+
+ if (ferror(f))
+ { BZ_SETERR(BZ_IO_ERROR); return NULL; };
+
+ bzf = malloc ( sizeof(bzFile) );
+ if (bzf == NULL)
+ { BZ_SETERR(BZ_MEM_ERROR); return NULL; };
+
+ BZ_SETERR(BZ_OK);
+ bzf->initialisedOk = False;
+ bzf->bufN = 0;
+ bzf->handle = f;
+ bzf->writing = True;
+ bzf->strm.bzalloc = NULL;
+ bzf->strm.bzfree = NULL;
+ bzf->strm.opaque = NULL;
+
+ if (workFactor == 0) workFactor = 30;
+ ret = BZ2_bzCompressInit ( &(bzf->strm), blockSize100k,
+ verbosity, workFactor );
+ if (ret != BZ_OK)
+ { BZ_SETERR(ret); free(bzf); return NULL; };
+
+ bzf->strm.avail_in = 0;
+ bzf->initialisedOk = True;
+ return bzf;
+}
+
+
+/*---------------------------------------------------*/
+void BZ_API(BZ2_bzWrite)
+ ( int* bzerror,
+ BZFILE* b,
+ void* buf,
+ int len )
+{
+ Int32 n, n2, ret;
+ bzFile* bzf = (bzFile*)b;
+
+ BZ_SETERR(BZ_OK);
+ if (bzf == NULL || buf == NULL || len < 0)
+ { BZ_SETERR(BZ_PARAM_ERROR); return; };
+ if (!(bzf->writing))
+ { BZ_SETERR(BZ_SEQUENCE_ERROR); return; };
+ if (ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return; };
+
+ if (len == 0)
+ { BZ_SETERR(BZ_OK); return; };
+
+ bzf->strm.avail_in = len;
+ bzf->strm.next_in = buf;
+
+ while (True) {
+ bzf->strm.avail_out = BZ_MAX_UNUSED;
+ bzf->strm.next_out = bzf->buf;
+ ret = BZ2_bzCompress ( &(bzf->strm), BZ_RUN );
+ if (ret != BZ_RUN_OK)
+ { BZ_SETERR(ret); return; };
+
+ if (bzf->strm.avail_out < BZ_MAX_UNUSED) {
+ n = BZ_MAX_UNUSED - bzf->strm.avail_out;
+ n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar),
+ n, bzf->handle );
+ if (n != n2 || ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return; };
+ }
+
+ if (bzf->strm.avail_in == 0)
+ { BZ_SETERR(BZ_OK); return; };
+ }
+}
+
+
+/*---------------------------------------------------*/
+void BZ_API(BZ2_bzWriteClose)
+ ( int* bzerror,
+ BZFILE* b,
+ int abandon,
+ unsigned int* nbytes_in,
+ unsigned int* nbytes_out )
+{
+ BZ2_bzWriteClose64 ( bzerror, b, abandon,
+ nbytes_in, NULL, nbytes_out, NULL );
+}
+
+
+void BZ_API(BZ2_bzWriteClose64)
+ ( int* bzerror,
+ BZFILE* b,
+ int abandon,
+ unsigned int* nbytes_in_lo32,
+ unsigned int* nbytes_in_hi32,
+ unsigned int* nbytes_out_lo32,
+ unsigned int* nbytes_out_hi32 )
+{
+ Int32 n, n2, ret;
+ bzFile* bzf = (bzFile*)b;
+
+ if (bzf == NULL)
+ { BZ_SETERR(BZ_OK); return; };
+ if (!(bzf->writing))
+ { BZ_SETERR(BZ_SEQUENCE_ERROR); return; };
+ if (ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return; };
+
+ if (nbytes_in_lo32 != NULL) *nbytes_in_lo32 = 0;
+ if (nbytes_in_hi32 != NULL) *nbytes_in_hi32 = 0;
+ if (nbytes_out_lo32 != NULL) *nbytes_out_lo32 = 0;
+ if (nbytes_out_hi32 != NULL) *nbytes_out_hi32 = 0;
+
+ if ((!abandon) && bzf->lastErr == BZ_OK) {
+ while (True) {
+ bzf->strm.avail_out = BZ_MAX_UNUSED;
+ bzf->strm.next_out = bzf->buf;
+ ret = BZ2_bzCompress ( &(bzf->strm), BZ_FINISH );
+ if (ret != BZ_FINISH_OK && ret != BZ_STREAM_END)
+ { BZ_SETERR(ret); return; };
+
+ if (bzf->strm.avail_out < BZ_MAX_UNUSED) {
+ n = BZ_MAX_UNUSED - bzf->strm.avail_out;
+ n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar),
+ n, bzf->handle );
+ if (n != n2 || ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return; };
+ }
+
+ if (ret == BZ_STREAM_END) break;
+ }
+ }
+
+ if ( !abandon && !ferror ( bzf->handle ) ) {
+ fflush ( bzf->handle );
+ if (ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return; };
+ }
+
+ if (nbytes_in_lo32 != NULL)
+ *nbytes_in_lo32 = bzf->strm.total_in_lo32;
+ if (nbytes_in_hi32 != NULL)
+ *nbytes_in_hi32 = bzf->strm.total_in_hi32;
+ if (nbytes_out_lo32 != NULL)
+ *nbytes_out_lo32 = bzf->strm.total_out_lo32;
+ if (nbytes_out_hi32 != NULL)
+ *nbytes_out_hi32 = bzf->strm.total_out_hi32;
+
+ BZ_SETERR(BZ_OK);
+ BZ2_bzCompressEnd ( &(bzf->strm) );
+ free ( bzf );
+}
+
+
+/*---------------------------------------------------*/
+BZFILE* BZ_API(BZ2_bzReadOpen)
+ ( int* bzerror,
+ FILE* f,
+ int verbosity,
+ int small,
+ void* unused,
+ int nUnused )
+{
+ bzFile* bzf = NULL;
+ int ret;
+
+ BZ_SETERR(BZ_OK);
+
+ if (f == NULL ||
+ (small != 0 && small != 1) ||
+ (verbosity < 0 || verbosity > 4) ||
+ (unused == NULL && nUnused != 0) ||
+ (unused != NULL && (nUnused < 0 || nUnused > BZ_MAX_UNUSED)))
+ { BZ_SETERR(BZ_PARAM_ERROR); return NULL; };
+
+ if (ferror(f))
+ { BZ_SETERR(BZ_IO_ERROR); return NULL; };
+
+ bzf = malloc ( sizeof(bzFile) );
+ if (bzf == NULL)
+ { BZ_SETERR(BZ_MEM_ERROR); return NULL; };
+
+ BZ_SETERR(BZ_OK);
+
+ bzf->initialisedOk = False;
+ bzf->handle = f;
+ bzf->bufN = 0;
+ bzf->writing = False;
+ bzf->strm.bzalloc = NULL;
+ bzf->strm.bzfree = NULL;
+ bzf->strm.opaque = NULL;
+
+ while (nUnused > 0) {
+ bzf->buf[bzf->bufN] = *((UChar*)(unused)); bzf->bufN++;
+ unused = ((void*)( 1 + ((UChar*)(unused)) ));
+ nUnused--;
+ }
+
+ ret = BZ2_bzDecompressInit ( &(bzf->strm), verbosity, small );
+ if (ret != BZ_OK)
+ { BZ_SETERR(ret); free(bzf); return NULL; };
+
+ bzf->strm.avail_in = bzf->bufN;
+ bzf->strm.next_in = bzf->buf;
+
+ bzf->initialisedOk = True;
+ return bzf;
+}
+
+
+/*---------------------------------------------------*/
+void BZ_API(BZ2_bzReadClose) ( int *bzerror, BZFILE *b )
+{
+ bzFile* bzf = (bzFile*)b;
+
+ BZ_SETERR(BZ_OK);
+ if (bzf == NULL)
+ { BZ_SETERR(BZ_OK); return; };
+
+ if (bzf->writing)
+ { BZ_SETERR(BZ_SEQUENCE_ERROR); return; };
+
+ if (bzf->initialisedOk)
+ (void)BZ2_bzDecompressEnd ( &(bzf->strm) );
+ free ( bzf );
+}
+
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzRead)
+ ( int* bzerror,
+ BZFILE* b,
+ void* buf,
+ int len )
+{
+ Int32 n, ret;
+ bzFile* bzf = (bzFile*)b;
+
+ BZ_SETERR(BZ_OK);
+
+ if (bzf == NULL || buf == NULL || len < 0)
+ { BZ_SETERR(BZ_PARAM_ERROR); return 0; };
+
+ if (bzf->writing)
+ { BZ_SETERR(BZ_SEQUENCE_ERROR); return 0; };
+
+ if (len == 0)
+ { BZ_SETERR(BZ_OK); return 0; };
+
+ bzf->strm.avail_out = len;
+ bzf->strm.next_out = buf;
+
+ while (True) {
+
+ if (ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return 0; };
+
+ if (bzf->strm.avail_in == 0 && !myfeof(bzf->handle)) {
+ n = fread ( bzf->buf, sizeof(UChar),
+ BZ_MAX_UNUSED, bzf->handle );
+ if (ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return 0; };
+ bzf->bufN = n;
+ bzf->strm.avail_in = bzf->bufN;
+ bzf->strm.next_in = bzf->buf;
+ }
+
+ ret = BZ2_bzDecompress ( &(bzf->strm) );
+
+ if (ret != BZ_OK && ret != BZ_STREAM_END)
+ { BZ_SETERR(ret); return 0; };
+
+ if (ret == BZ_OK && myfeof(bzf->handle) &&
+ bzf->strm.avail_in == 0 && bzf->strm.avail_out > 0)
+ { BZ_SETERR(BZ_UNEXPECTED_EOF); return 0; };
+
+ if (ret == BZ_STREAM_END)
+ { BZ_SETERR(BZ_STREAM_END);
+ return len - bzf->strm.avail_out; };
+ if (bzf->strm.avail_out == 0)
+ { BZ_SETERR(BZ_OK); return len; };
+
+ }
+
+ return 0; /*not reached*/
+}
+
+
+/*---------------------------------------------------*/
+void BZ_API(BZ2_bzReadGetUnused)
+ ( int* bzerror,
+ BZFILE* b,
+ void** unused,
+ int* nUnused )
+{
+ bzFile* bzf = (bzFile*)b;
+ if (bzf == NULL)
+ { BZ_SETERR(BZ_PARAM_ERROR); return; };
+ if (bzf->lastErr != BZ_STREAM_END)
+ { BZ_SETERR(BZ_SEQUENCE_ERROR); return; };
+ if (unused == NULL || nUnused == NULL)
+ { BZ_SETERR(BZ_PARAM_ERROR); return; };
+
+ BZ_SETERR(BZ_OK);
+ *nUnused = bzf->strm.avail_in;
+ *unused = bzf->strm.next_in;
+}
+#endif
+
+
+/*---------------------------------------------------*/
+/*--- Misc convenience stuff ---*/
+/*---------------------------------------------------*/
+#ifndef BZ_NO_COMPRESS
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzBuffToBuffCompress)
+ ( char* dest,
+ unsigned int* destLen,
+ char* source,
+ unsigned int sourceLen,
+ int blockSize100k,
+ int verbosity,
+ int workFactor )
+{
+ bz_stream strm;
+ int ret;
+
+ if (dest == NULL || destLen == NULL ||
+ source == NULL ||
+ blockSize100k < 1 || blockSize100k > 9 ||
+ verbosity < 0 || verbosity > 4 ||
+ workFactor < 0 || workFactor > 250)
+ return BZ_PARAM_ERROR;
+
+ if (workFactor == 0) workFactor = 30;
+ strm.bzalloc = NULL;
+ strm.bzfree = NULL;
+ strm.opaque = NULL;
+ ret = BZ2_bzCompressInit ( &strm, blockSize100k,
+ verbosity, workFactor );
+ if (ret != BZ_OK) return ret;
+
+ strm.next_in = source;
+ strm.next_out = dest;
+ strm.avail_in = sourceLen;
+ strm.avail_out = *destLen;
+
+ ret = BZ2_bzCompress ( &strm, BZ_FINISH );
+ if (ret == BZ_FINISH_OK) goto output_overflow;
+ if (ret != BZ_STREAM_END) goto errhandler;
+
+ /* normal termination */
+ *destLen -= strm.avail_out;
+ BZ2_bzCompressEnd ( &strm );
+ return BZ_OK;
+
+ output_overflow:
+ BZ2_bzCompressEnd ( &strm );
+ return BZ_OUTBUFF_FULL;
+
+ errhandler:
+ BZ2_bzCompressEnd ( &strm );
+ return ret;
+}
+#endif /* BZ_NO_COMPRESS */
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzBuffToBuffDecompress)
+ ( char* dest,
+ unsigned int* destLen,
+ char* source,
+ unsigned int sourceLen,
+ int small,
+ int verbosity )
+{
+ bz_stream strm;
+ int ret;
+
+ if (destLen == NULL || source == NULL)
+ return BZ_PARAM_ERROR;
+
+ strm.bzalloc = NULL;
+ strm.bzfree = NULL;
+ strm.opaque = NULL;
+ ret = BZ2_bzDecompressInit ( &strm, verbosity, small );
+ if (ret != BZ_OK) return ret;
+
+ strm.next_in = source;
+ strm.next_out = dest;
+ strm.avail_in = sourceLen;
+ strm.avail_out = *destLen;
+
+ ret = BZ2_bzDecompress ( &strm );
+ if (ret == BZ_OK) goto output_overflow_or_eof;
+ if (ret != BZ_STREAM_END) goto errhandler;
+
+ /* normal termination */
+ *destLen -= strm.avail_out;
+ BZ2_bzDecompressEnd ( &strm );
+ return BZ_OK;
+
+ output_overflow_or_eof:
+ if (strm.avail_out > 0) {
+ BZ2_bzDecompressEnd ( &strm );
+ return BZ_UNEXPECTED_EOF;
+ } else {
+ BZ2_bzDecompressEnd ( &strm );
+ return BZ_OUTBUFF_FULL;
+ };
+
+ errhandler:
+ BZ2_bzDecompressEnd ( &strm );
+ return ret;
+}
+
+
+/*---------------------------------------------------*/
+/*--
+ Code contributed by Yoshioka Tsuneo
+ (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
+ to support better zlib compatibility.
+ This code is not _officially_ part of libbzip2 (yet);
+ I haven't tested it, documented it, or considered the
+ threading-safeness of it.
+ If this code breaks, please contact both Yoshioka and me.
+--*/
+/*---------------------------------------------------*/
+
+/*---------------------------------------------------*/
+/*--
+ return version like "0.9.0c".
+--*/
+const char * BZ_API(BZ2_bzlibVersion)(void)
+{
+ return BZ_VERSION;
+}
+
+
+#ifndef BZ_NO_STDIO
+/*---------------------------------------------------*/
+
+#if defined(_WIN32) || defined(OS2) || defined(MSDOS)
+# include <fcntl.h>
+# include <io.h>
+# define SET_BINARY_MODE(file) setmode(fileno(file),O_BINARY)
+#else
+# define SET_BINARY_MODE(file)
+#endif
+static
+BZFILE * bzopen_or_bzdopen
+ ( const char *path, /* no use when bzdopen */
+ int fd, /* no use when bzdopen */
+ const char *mode,
+ int open_mode) /* bzopen: 0, bzdopen:1 */
+{
+ int bzerr;
+ char unused[BZ_MAX_UNUSED];
+ int blockSize100k = 9;
+ int writing = 0;
+ char mode2[10] = "";
+ FILE *fp = NULL;
+ BZFILE *bzfp = NULL;
+ int verbosity = 0;
+ int workFactor = 30;
+ int smallMode = 0;
+ int nUnused = 0;
+
+ if (mode == NULL) return NULL;
+ while (*mode) {
+ switch (*mode) {
+ case 'r':
+ writing = 0; break;
+ case 'w':
+ writing = 1; break;
+ case 's':
+ smallMode = 1; break;
+ default:
+ if (isdigit((int)(*mode))) {
+ blockSize100k = *mode-BZ_HDR_0;
+ }
+ }
+ mode++;
+ }
+ strcat(mode2, writing ? "w" : "r" );
+ strcat(mode2,"b"); /* binary mode */
+
+ if (open_mode==0) {
+ if (path==NULL || strcmp(path,"")==0) {
+ fp = (writing ? stdout : stdin);
+ SET_BINARY_MODE(fp);
+ } else {
+ fp = fopen(path,mode2);
+ }
+ } else {
+#ifdef BZ_STRICT_ANSI
+ fp = NULL;
+#else
+ fp = fdopen(fd,mode2);
+#endif
+ }
+ if (fp == NULL) return NULL;
+
+ if (writing) {
+ /* Guard against total chaos and anarchy -- JRS */
+ if (blockSize100k < 1) blockSize100k = 1;
+ if (blockSize100k > 9) blockSize100k = 9;
+ bzfp = BZ2_bzWriteOpen(&bzerr,fp,blockSize100k,
+ verbosity,workFactor);
+ } else {
+ bzfp = BZ2_bzReadOpen(&bzerr,fp,verbosity,smallMode,
+ unused,nUnused);
+ }
+ if (bzfp == NULL) {
+ if (fp != stdin && fp != stdout) fclose(fp);
+ return NULL;
+ }
+ return bzfp;
+}
+
+
+/*---------------------------------------------------*/
+/*--
+ open file for read or write.
+ ex) bzopen("file","w9")
+ case path="" or NULL => use stdin or stdout.
+--*/
+BZFILE * BZ_API(BZ2_bzopen)
+ ( const char *path,
+ const char *mode )
+{
+ return bzopen_or_bzdopen(path,-1,mode,/*bzopen*/0);
+}
+
+
+/*---------------------------------------------------*/
+BZFILE * BZ_API(BZ2_bzdopen)
+ ( int fd,
+ const char *mode )
+{
+ return bzopen_or_bzdopen(NULL,fd,mode,/*bzdopen*/1);
+}
+
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzread) (BZFILE* b, void* buf, int len )
+{
+ int bzerr, nread;
+ if (((bzFile*)b)->lastErr == BZ_STREAM_END) return 0;
+ nread = BZ2_bzRead(&bzerr,b,buf,len);
+ if (bzerr == BZ_OK || bzerr == BZ_STREAM_END) {
+ return nread;
+ } else {
+ return -1;
+ }
+}
+
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzwrite) (BZFILE* b, void* buf, int len )
+{
+ int bzerr;
+
+ BZ2_bzWrite(&bzerr,b,buf,len);
+ if(bzerr == BZ_OK){
+ return len;
+ }else{
+ return -1;
+ }
+}
+
+
+/*---------------------------------------------------*/
+int BZ_API(BZ2_bzflush) (BZFILE *b)
+{
+ /* do nothing now... */
+ return 0;
+}
+
+
+/*---------------------------------------------------*/
+void BZ_API(BZ2_bzclose) (BZFILE* b)
+{
+ int bzerr;
+ FILE *fp = ((bzFile *)b)->handle;
+
+ if (b==NULL) {return;}
+ if(((bzFile*)b)->writing){
+ BZ2_bzWriteClose(&bzerr,b,0,NULL,NULL);
+ if(bzerr != BZ_OK){
+ BZ2_bzWriteClose(NULL,b,1,NULL,NULL);
+ }
+ }else{
+ BZ2_bzReadClose(&bzerr,b);
+ }
+ if(fp!=stdin && fp!=stdout){
+ fclose(fp);
+ }
+}
+
+
+/*---------------------------------------------------*/
+/*--
+ return last error code
+--*/
+static char *bzerrorstrings[] = {
+ "OK"
+ ,"SEQUENCE_ERROR"
+ ,"PARAM_ERROR"
+ ,"MEM_ERROR"
+ ,"DATA_ERROR"
+ ,"DATA_ERROR_MAGIC"
+ ,"IO_ERROR"
+ ,"UNEXPECTED_EOF"
+ ,"OUTBUFF_FULL"
+ ,"CONFIG_ERROR"
+ ,"???" /* for future */
+ ,"???" /* for future */
+ ,"???" /* for future */
+ ,"???" /* for future */
+ ,"???" /* for future */
+ ,"???" /* for future */
+};
+
+
+const char * BZ_API(BZ2_bzerror) (BZFILE *b, int *errnum)
+{
+ int err = ((bzFile *)b)->lastErr;
+
+ if(err>0) err = 0;
+ *errnum = err;
+ return bzerrorstrings[err*-1];
+}
+#endif
+
+void bz_internal_error(int errcode)
+{
+ printf ("BZIP2 internal error %d\n", errcode);
+}
+
+/*-------------------------------------------------------------*/
+/*--- end bzlib.c ---*/
+/*-------------------------------------------------------------*/
--- /dev/null
+#include <config.h>
+
+/*-------------------------------------------------------------*/
+/*--- Table for doing CRCs ---*/
+/*--- crctable.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+ This file is a part of bzip2 and/or libbzip2, a program and
+ library for lossless, block-sorting data compression.
+
+ Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+ 3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+ 4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Julian Seward, Cambridge, UK.
+ jseward@acm.org
+ bzip2/libbzip2 version 1.0 of 21 March 2000
+
+ This program is based on (at least) the work of:
+ Mike Burrows
+ David Wheeler
+ Peter Fenwick
+ Alistair Moffat
+ Radford Neal
+ Ian H. Witten
+ Robert Sedgewick
+ Jon L. Bentley
+
+ For more information on these sources, see the manual.
+--*/
+
+
+#include "bzlib_private.h"
+
+/*--
+ I think this is an implementation of the AUTODIN-II,
+ Ethernet & FDDI 32-bit CRC standard. Vaguely derived
+ from code by Rob Warnock, in Section 51 of the
+ comp.compression FAQ.
+--*/
+
+UInt32 BZ2_crc32Table[256] = {
+
+ /*-- Ugly, innit? --*/
+
+ 0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L,
+ 0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L,
+ 0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L,
+ 0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL,
+ 0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L,
+ 0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L,
+ 0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L,
+ 0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL,
+ 0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L,
+ 0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L,
+ 0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L,
+ 0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL,
+ 0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L,
+ 0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L,
+ 0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L,
+ 0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL,
+ 0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL,
+ 0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L,
+ 0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L,
+ 0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL,
+ 0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL,
+ 0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L,
+ 0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L,
+ 0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL,
+ 0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL,
+ 0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L,
+ 0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L,
+ 0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL,
+ 0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL,
+ 0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L,
+ 0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L,
+ 0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL,
+ 0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L,
+ 0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL,
+ 0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL,
+ 0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L,
+ 0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L,
+ 0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL,
+ 0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL,
+ 0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L,
+ 0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L,
+ 0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL,
+ 0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL,
+ 0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L,
+ 0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L,
+ 0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL,
+ 0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL,
+ 0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L,
+ 0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L,
+ 0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL,
+ 0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L,
+ 0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L,
+ 0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L,
+ 0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL,
+ 0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L,
+ 0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L,
+ 0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L,
+ 0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL,
+ 0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L,
+ 0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L,
+ 0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L,
+ 0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL,
+ 0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L,
+ 0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L
+};
+
+
+/*-------------------------------------------------------------*/
+/*--- end crctable.c ---*/
+/*-------------------------------------------------------------*/
--- /dev/null
+#include <config.h>
+#include <common.h>
+#include <watchdog.h>
+
+/*-------------------------------------------------------------*/
+/*--- Decompression machinery ---*/
+/*--- decompress.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+ This file is a part of bzip2 and/or libbzip2, a program and
+ library for lossless, block-sorting data compression.
+
+ Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+ 3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+ 4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Julian Seward, Cambridge, UK.
+ jseward@acm.org
+ bzip2/libbzip2 version 1.0 of 21 March 2000
+
+ This program is based on (at least) the work of:
+ Mike Burrows
+ David Wheeler
+ Peter Fenwick
+ Alistair Moffat
+ Radford Neal
+ Ian H. Witten
+ Robert Sedgewick
+ Jon L. Bentley
+
+ For more information on these sources, see the manual.
+--*/
+
+
+#include "bzlib_private.h"
+
+
+/*---------------------------------------------------*/
+static
+void makeMaps_d ( DState* s )
+{
+ Int32 i;
+ s->nInUse = 0;
+ for (i = 0; i < 256; i++)
+ if (s->inUse[i]) {
+ s->seqToUnseq[s->nInUse] = i;
+ s->nInUse++;
+ }
+}
+
+
+/*---------------------------------------------------*/
+#define RETURN(rrr) \
+ { retVal = rrr; goto save_state_and_return; };
+
+#define GET_BITS(lll,vvv,nnn) \
+ case lll: s->state = lll; \
+ while (True) { \
+ if (s->bsLive >= nnn) { \
+ UInt32 v; \
+ v = (s->bsBuff >> \
+ (s->bsLive-nnn)) & ((1 << nnn)-1); \
+ s->bsLive -= nnn; \
+ vvv = v; \
+ break; \
+ } \
+ if (s->strm->avail_in == 0) RETURN(BZ_OK); \
+ s->bsBuff \
+ = (s->bsBuff << 8) | \
+ ((UInt32) \
+ (*((UChar*)(s->strm->next_in)))); \
+ s->bsLive += 8; \
+ s->strm->next_in++; \
+ s->strm->avail_in--; \
+ s->strm->total_in_lo32++; \
+ if (s->strm->total_in_lo32 == 0) \
+ s->strm->total_in_hi32++; \
+ }
+
+#define GET_UCHAR(lll,uuu) \
+ GET_BITS(lll,uuu,8)
+
+#define GET_BIT(lll,uuu) \
+ GET_BITS(lll,uuu,1)
+
+/*---------------------------------------------------*/
+#define GET_MTF_VAL(label1,label2,lval) \
+{ \
+ if (groupPos == 0) { \
+ groupNo++; \
+ if (groupNo >= nSelectors) \
+ RETURN(BZ_DATA_ERROR); \
+ groupPos = BZ_G_SIZE; \
+ gSel = s->selector[groupNo]; \
+ gMinlen = s->minLens[gSel]; \
+ gLimit = &(s->limit[gSel][0]); \
+ gPerm = &(s->perm[gSel][0]); \
+ gBase = &(s->base[gSel][0]); \
+ } \
+ groupPos--; \
+ zn = gMinlen; \
+ GET_BITS(label1, zvec, zn); \
+ while (1) { \
+ if (zn > 20 /* the longest code */) \
+ RETURN(BZ_DATA_ERROR); \
+ if (zvec <= gLimit[zn]) break; \
+ zn++; \
+ GET_BIT(label2, zj); \
+ zvec = (zvec << 1) | zj; \
+ }; \
+ if (zvec - gBase[zn] < 0 \
+ || zvec - gBase[zn] >= BZ_MAX_ALPHA_SIZE) \
+ RETURN(BZ_DATA_ERROR); \
+ lval = gPerm[zvec - gBase[zn]]; \
+}
+
+
+/*---------------------------------------------------*/
+Int32 BZ2_decompress ( DState* s )
+{
+ UChar uc;
+ Int32 retVal;
+ Int32 minLen, maxLen;
+ bz_stream* strm = s->strm;
+
+ /* stuff that needs to be saved/restored */
+ Int32 i;
+ Int32 j;
+ Int32 t;
+ Int32 alphaSize;
+ Int32 nGroups;
+ Int32 nSelectors;
+ Int32 EOB;
+ Int32 groupNo;
+ Int32 groupPos;
+ Int32 nextSym;
+ Int32 nblockMAX;
+ Int32 nblock;
+ Int32 es;
+ Int32 N;
+ Int32 curr;
+ Int32 zt;
+ Int32 zn;
+ Int32 zvec;
+ Int32 zj;
+ Int32 gSel;
+ Int32 gMinlen;
+ Int32* gLimit;
+ Int32* gBase;
+ Int32* gPerm;
+
+ if (s->state == BZ_X_MAGIC_1) {
+ /*initialise the save area*/
+ s->save_i = 0;
+ s->save_j = 0;
+ s->save_t = 0;
+ s->save_alphaSize = 0;
+ s->save_nGroups = 0;
+ s->save_nSelectors = 0;
+ s->save_EOB = 0;
+ s->save_groupNo = 0;
+ s->save_groupPos = 0;
+ s->save_nextSym = 0;
+ s->save_nblockMAX = 0;
+ s->save_nblock = 0;
+ s->save_es = 0;
+ s->save_N = 0;
+ s->save_curr = 0;
+ s->save_zt = 0;
+ s->save_zn = 0;
+ s->save_zvec = 0;
+ s->save_zj = 0;
+ s->save_gSel = 0;
+ s->save_gMinlen = 0;
+ s->save_gLimit = NULL;
+ s->save_gBase = NULL;
+ s->save_gPerm = NULL;
+ }
+
+ /*restore from the save area*/
+ i = s->save_i;
+ j = s->save_j;
+ t = s->save_t;
+ alphaSize = s->save_alphaSize;
+ nGroups = s->save_nGroups;
+ nSelectors = s->save_nSelectors;
+ EOB = s->save_EOB;
+ groupNo = s->save_groupNo;
+ groupPos = s->save_groupPos;
+ nextSym = s->save_nextSym;
+ nblockMAX = s->save_nblockMAX;
+ nblock = s->save_nblock;
+ es = s->save_es;
+ N = s->save_N;
+ curr = s->save_curr;
+ zt = s->save_zt;
+ zn = s->save_zn;
+ zvec = s->save_zvec;
+ zj = s->save_zj;
+ gSel = s->save_gSel;
+ gMinlen = s->save_gMinlen;
+ gLimit = s->save_gLimit;
+ gBase = s->save_gBase;
+ gPerm = s->save_gPerm;
+
+ retVal = BZ_OK;
+
+ switch (s->state) {
+
+ GET_UCHAR(BZ_X_MAGIC_1, uc);
+ if (uc != BZ_HDR_B) RETURN(BZ_DATA_ERROR_MAGIC);
+
+ GET_UCHAR(BZ_X_MAGIC_2, uc);
+ if (uc != BZ_HDR_Z) RETURN(BZ_DATA_ERROR_MAGIC);
+
+ GET_UCHAR(BZ_X_MAGIC_3, uc)
+ if (uc != BZ_HDR_h) RETURN(BZ_DATA_ERROR_MAGIC);
+
+ GET_BITS(BZ_X_MAGIC_4, s->blockSize100k, 8)
+ if (s->blockSize100k < (BZ_HDR_0 + 1) ||
+ s->blockSize100k > (BZ_HDR_0 + 9)) RETURN(BZ_DATA_ERROR_MAGIC);
+ s->blockSize100k -= BZ_HDR_0;
+
+ if (s->smallDecompress) {
+ s->ll16 = BZALLOC( s->blockSize100k * 100000 * sizeof(UInt16) );
+ s->ll4 = BZALLOC(
+ ((1 + s->blockSize100k * 100000) >> 1) * sizeof(UChar)
+ );
+ if (s->ll16 == NULL || s->ll4 == NULL) RETURN(BZ_MEM_ERROR);
+ } else {
+ s->tt = BZALLOC( s->blockSize100k * 100000 * sizeof(Int32) );
+ if (s->tt == NULL) RETURN(BZ_MEM_ERROR);
+ }
+
+ GET_UCHAR(BZ_X_BLKHDR_1, uc);
+
+ if (uc == 0x17) goto endhdr_2;
+ if (uc != 0x31) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_BLKHDR_2, uc);
+ if (uc != 0x41) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_BLKHDR_3, uc);
+ if (uc != 0x59) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_BLKHDR_4, uc);
+ if (uc != 0x26) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_BLKHDR_5, uc);
+ if (uc != 0x53) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_BLKHDR_6, uc);
+ if (uc != 0x59) RETURN(BZ_DATA_ERROR);
+
+ s->currBlockNo++;
+ if (s->verbosity >= 2)
+ VPrintf1 ( "\n [%d: huff+mtf ", s->currBlockNo );
+
+ s->storedBlockCRC = 0;
+ GET_UCHAR(BZ_X_BCRC_1, uc);
+ s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
+ GET_UCHAR(BZ_X_BCRC_2, uc);
+ s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
+ GET_UCHAR(BZ_X_BCRC_3, uc);
+ s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
+ GET_UCHAR(BZ_X_BCRC_4, uc);
+ s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
+
+ GET_BITS(BZ_X_RANDBIT, s->blockRandomised, 1);
+
+ s->origPtr = 0;
+ GET_UCHAR(BZ_X_ORIGPTR_1, uc);
+ s->origPtr = (s->origPtr << 8) | ((Int32)uc);
+ GET_UCHAR(BZ_X_ORIGPTR_2, uc);
+ s->origPtr = (s->origPtr << 8) | ((Int32)uc);
+ GET_UCHAR(BZ_X_ORIGPTR_3, uc);
+ s->origPtr = (s->origPtr << 8) | ((Int32)uc);
+
+ if (s->origPtr < 0)
+ RETURN(BZ_DATA_ERROR);
+ if (s->origPtr > 10 + 100000*s->blockSize100k)
+ RETURN(BZ_DATA_ERROR);
+
+ /*--- Receive the mapping table ---*/
+ for (i = 0; i < 16; i++) {
+ GET_BIT(BZ_X_MAPPING_1, uc);
+ if (uc == 1)
+ s->inUse16[i] = True; else
+ s->inUse16[i] = False;
+ }
+
+ for (i = 0; i < 256; i++) s->inUse[i] = False;
+
+ for (i = 0; i < 16; i++)
+ if (s->inUse16[i])
+ for (j = 0; j < 16; j++) {
+ GET_BIT(BZ_X_MAPPING_2, uc);
+ if (uc == 1) s->inUse[i * 16 + j] = True;
+ }
+ makeMaps_d ( s );
+ if (s->nInUse == 0) RETURN(BZ_DATA_ERROR);
+ alphaSize = s->nInUse+2;
+
+ /*--- Now the selectors ---*/
+ GET_BITS(BZ_X_SELECTOR_1, nGroups, 3);
+ if (nGroups < 2 || nGroups > 6) RETURN(BZ_DATA_ERROR);
+ GET_BITS(BZ_X_SELECTOR_2, nSelectors, 15);
+ if (nSelectors < 1) RETURN(BZ_DATA_ERROR);
+ for (i = 0; i < nSelectors; i++) {
+ j = 0;
+ while (True) {
+ GET_BIT(BZ_X_SELECTOR_3, uc);
+ if (uc == 0) break;
+ j++;
+ if (j >= nGroups) RETURN(BZ_DATA_ERROR);
+ }
+ s->selectorMtf[i] = j;
+ }
+
+ /*--- Undo the MTF values for the selectors. ---*/
+ {
+ UChar pos[BZ_N_GROUPS], tmp, v;
+ for (v = 0; v < nGroups; v++) pos[v] = v;
+
+ for (i = 0; i < nSelectors; i++) {
+ v = s->selectorMtf[i];
+ tmp = pos[v];
+ while (v > 0) { pos[v] = pos[v-1]; v--; }
+ pos[0] = tmp;
+ s->selector[i] = tmp;
+ }
+ }
+
+ /*--- Now the coding tables ---*/
+ for (t = 0; t < nGroups; t++) {
+ GET_BITS(BZ_X_CODING_1, curr, 5);
+ for (i = 0; i < alphaSize; i++) {
+ while (True) {
+ if (curr < 1 || curr > 20) RETURN(BZ_DATA_ERROR);
+ GET_BIT(BZ_X_CODING_2, uc);
+ if (uc == 0) break;
+ GET_BIT(BZ_X_CODING_3, uc);
+ if (uc == 0) curr++; else curr--;
+ }
+ s->len[t][i] = curr;
+ }
+ }
+
+ /*--- Create the Huffman decoding tables ---*/
+ for (t = 0; t < nGroups; t++) {
+ minLen = 32;
+ maxLen = 0;
+ for (i = 0; i < alphaSize; i++) {
+ if (s->len[t][i] > maxLen) maxLen = s->len[t][i];
+ if (s->len[t][i] < minLen) minLen = s->len[t][i];
+ }
+ BZ2_hbCreateDecodeTables (
+ &(s->limit[t][0]),
+ &(s->base[t][0]),
+ &(s->perm[t][0]),
+ &(s->len[t][0]),
+ minLen, maxLen, alphaSize
+ );
+ s->minLens[t] = minLen;
+ }
+
+ /*--- Now the MTF values ---*/
+
+ EOB = s->nInUse+1;
+ nblockMAX = 100000 * s->blockSize100k;
+ groupNo = -1;
+ groupPos = 0;
+
+ for (i = 0; i <= 255; i++) s->unzftab[i] = 0;
+
+ /*-- MTF init --*/
+ {
+ Int32 ii, jj, kk;
+ kk = MTFA_SIZE-1;
+ for (ii = 256 / MTFL_SIZE - 1; ii >= 0; ii--) {
+ for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
+ s->mtfa[kk] = (UChar)(ii * MTFL_SIZE + jj);
+ kk--;
+ }
+ s->mtfbase[ii] = kk + 1;
+ }
+ }
+ /*-- end MTF init --*/
+
+ nblock = 0;
+ GET_MTF_VAL(BZ_X_MTF_1, BZ_X_MTF_2, nextSym);
+
+ while (True) {
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+ if (nextSym == EOB) break;
+
+ if (nextSym == BZ_RUNA || nextSym == BZ_RUNB) {
+
+ es = -1;
+ N = 1;
+ do {
+ if (nextSym == BZ_RUNA) es = es + (0+1) * N; else
+ if (nextSym == BZ_RUNB) es = es + (1+1) * N;
+ N = N * 2;
+ GET_MTF_VAL(BZ_X_MTF_3, BZ_X_MTF_4, nextSym);
+ }
+ while (nextSym == BZ_RUNA || nextSym == BZ_RUNB);
+
+ es++;
+ uc = s->seqToUnseq[ s->mtfa[s->mtfbase[0]] ];
+ s->unzftab[uc] += es;
+
+ if (s->smallDecompress)
+ while (es > 0) {
+ if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+ s->ll16[nblock] = (UInt16)uc;
+ nblock++;
+ es--;
+ }
+ else
+ while (es > 0) {
+ if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+ s->tt[nblock] = (UInt32)uc;
+ nblock++;
+ es--;
+ };
+
+ continue;
+
+ } else {
+
+ if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+
+ /*-- uc = MTF ( nextSym-1 ) --*/
+ {
+ Int32 ii, jj, kk, pp, lno, off;
+ UInt32 nn;
+ nn = (UInt32)(nextSym - 1);
+
+ if (nn < MTFL_SIZE) {
+ /* avoid general-case expense */
+ pp = s->mtfbase[0];
+ uc = s->mtfa[pp+nn];
+ while (nn > 3) {
+ Int32 z = pp+nn;
+ s->mtfa[(z) ] = s->mtfa[(z)-1];
+ s->mtfa[(z)-1] = s->mtfa[(z)-2];
+ s->mtfa[(z)-2] = s->mtfa[(z)-3];
+ s->mtfa[(z)-3] = s->mtfa[(z)-4];
+ nn -= 4;
+ }
+ while (nn > 0) {
+ s->mtfa[(pp+nn)] = s->mtfa[(pp+nn)-1]; nn--;
+ };
+ s->mtfa[pp] = uc;
+ } else {
+ /* general case */
+ lno = nn / MTFL_SIZE;
+ off = nn % MTFL_SIZE;
+ pp = s->mtfbase[lno] + off;
+ uc = s->mtfa[pp];
+ while (pp > s->mtfbase[lno]) {
+ s->mtfa[pp] = s->mtfa[pp-1]; pp--;
+ };
+ s->mtfbase[lno]++;
+ while (lno > 0) {
+ s->mtfbase[lno]--;
+ s->mtfa[s->mtfbase[lno]]
+ = s->mtfa[s->mtfbase[lno-1] + MTFL_SIZE - 1];
+ lno--;
+ }
+ s->mtfbase[0]--;
+ s->mtfa[s->mtfbase[0]] = uc;
+ if (s->mtfbase[0] == 0) {
+ kk = MTFA_SIZE-1;
+ for (ii = 256 / MTFL_SIZE-1; ii >= 0; ii--) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+ for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
+ s->mtfa[kk] = s->mtfa[s->mtfbase[ii] + jj];
+ kk--;
+ }
+ s->mtfbase[ii] = kk + 1;
+ }
+ }
+ }
+ }
+ /*-- end uc = MTF ( nextSym-1 ) --*/
+
+ s->unzftab[s->seqToUnseq[uc]]++;
+ if (s->smallDecompress)
+ s->ll16[nblock] = (UInt16)(s->seqToUnseq[uc]); else
+ s->tt[nblock] = (UInt32)(s->seqToUnseq[uc]);
+ nblock++;
+
+ GET_MTF_VAL(BZ_X_MTF_5, BZ_X_MTF_6, nextSym);
+ continue;
+ }
+ }
+
+ /* Now we know what nblock is, we can do a better sanity
+ check on s->origPtr.
+ */
+ if (s->origPtr < 0 || s->origPtr >= nblock)
+ RETURN(BZ_DATA_ERROR);
+
+ s->state_out_len = 0;
+ s->state_out_ch = 0;
+ BZ_INITIALISE_CRC ( s->calculatedBlockCRC );
+ s->state = BZ_X_OUTPUT;
+ if (s->verbosity >= 2) VPrintf0 ( "rt+rld" );
+
+ /*-- Set up cftab to facilitate generation of T^(-1) --*/
+ s->cftab[0] = 0;
+ for (i = 1; i <= 256; i++) s->cftab[i] = s->unzftab[i-1];
+ for (i = 1; i <= 256; i++) s->cftab[i] += s->cftab[i-1];
+
+ if (s->smallDecompress) {
+
+ /*-- Make a copy of cftab, used in generation of T --*/
+ for (i = 0; i <= 256; i++) s->cftabCopy[i] = s->cftab[i];
+
+ /*-- compute the T vector --*/
+ for (i = 0; i < nblock; i++) {
+ uc = (UChar)(s->ll16[i]);
+ SET_LL(i, s->cftabCopy[uc]);
+ s->cftabCopy[uc]++;
+ }
+
+ /*-- Compute T^(-1) by pointer reversal on T --*/
+ i = s->origPtr;
+ j = GET_LL(i);
+ do {
+ Int32 tmp = GET_LL(j);
+ SET_LL(j, i);
+ i = j;
+ j = tmp;
+ }
+ while (i != s->origPtr);
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+ s->tPos = s->origPtr;
+ s->nblock_used = 0;
+ if (s->blockRandomised) {
+ BZ_RAND_INIT_MASK;
+ BZ_GET_SMALL(s->k0); s->nblock_used++;
+ BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
+ } else {
+ BZ_GET_SMALL(s->k0); s->nblock_used++;
+ }
+
+ } else {
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+ /*-- compute the T^(-1) vector --*/
+ for (i = 0; i < nblock; i++) {
+ uc = (UChar)(s->tt[i] & 0xff);
+ s->tt[s->cftab[uc]] |= (i << 8);
+ s->cftab[uc]++;
+ }
+
+ s->tPos = s->tt[s->origPtr] >> 8;
+ s->nblock_used = 0;
+ if (s->blockRandomised) {
+ BZ_RAND_INIT_MASK;
+ BZ_GET_FAST(s->k0); s->nblock_used++;
+ BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
+ } else {
+ BZ_GET_FAST(s->k0); s->nblock_used++;
+ }
+
+ }
+
+ RETURN(BZ_OK);
+
+
+ endhdr_2:
+
+ GET_UCHAR(BZ_X_ENDHDR_2, uc);
+ if (uc != 0x72) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_ENDHDR_3, uc);
+ if (uc != 0x45) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_ENDHDR_4, uc);
+ if (uc != 0x38) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_ENDHDR_5, uc);
+ if (uc != 0x50) RETURN(BZ_DATA_ERROR);
+ GET_UCHAR(BZ_X_ENDHDR_6, uc);
+ if (uc != 0x90) RETURN(BZ_DATA_ERROR);
+
+ s->storedCombinedCRC = 0;
+ GET_UCHAR(BZ_X_CCRC_1, uc);
+ s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
+ GET_UCHAR(BZ_X_CCRC_2, uc);
+ s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
+ GET_UCHAR(BZ_X_CCRC_3, uc);
+ s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
+ GET_UCHAR(BZ_X_CCRC_4, uc);
+ s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
+
+ s->state = BZ_X_IDLE;
+ RETURN(BZ_STREAM_END);
+
+ default: AssertH ( False, 4001 );
+ }
+
+ AssertH ( False, 4002 );
+
+ save_state_and_return:
+
+ s->save_i = i;
+ s->save_j = j;
+ s->save_t = t;
+ s->save_alphaSize = alphaSize;
+ s->save_nGroups = nGroups;
+ s->save_nSelectors = nSelectors;
+ s->save_EOB = EOB;
+ s->save_groupNo = groupNo;
+ s->save_groupPos = groupPos;
+ s->save_nextSym = nextSym;
+ s->save_nblockMAX = nblockMAX;
+ s->save_nblock = nblock;
+ s->save_es = es;
+ s->save_N = N;
+ s->save_curr = curr;
+ s->save_zt = zt;
+ s->save_zn = zn;
+ s->save_zvec = zvec;
+ s->save_zj = zj;
+ s->save_gSel = gSel;
+ s->save_gMinlen = gMinlen;
+ s->save_gLimit = gLimit;
+ s->save_gBase = gBase;
+ s->save_gPerm = gPerm;
+
+ return retVal;
+}
+
+
+/*-------------------------------------------------------------*/
+/*--- end decompress.c ---*/
+/*-------------------------------------------------------------*/
--- /dev/null
+#include <config.h>
+
+/*-------------------------------------------------------------*/
+/*--- Huffman coding low-level stuff ---*/
+/*--- huffman.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+ This file is a part of bzip2 and/or libbzip2, a program and
+ library for lossless, block-sorting data compression.
+
+ Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+ 3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+ 4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Julian Seward, Cambridge, UK.
+ jseward@acm.org
+ bzip2/libbzip2 version 1.0 of 21 March 2000
+
+ This program is based on (at least) the work of:
+ Mike Burrows
+ David Wheeler
+ Peter Fenwick
+ Alistair Moffat
+ Radford Neal
+ Ian H. Witten
+ Robert Sedgewick
+ Jon L. Bentley
+
+ For more information on these sources, see the manual.
+--*/
+
+
+#include "bzlib_private.h"
+
+/*---------------------------------------------------*/
+#define WEIGHTOF(zz0) ((zz0) & 0xffffff00)
+#define DEPTHOF(zz1) ((zz1) & 0x000000ff)
+#define MYMAX(zz2,zz3) ((zz2) > (zz3) ? (zz2) : (zz3))
+
+#define ADDWEIGHTS(zw1,zw2) \
+ (WEIGHTOF(zw1)+WEIGHTOF(zw2)) | \
+ (1 + MYMAX(DEPTHOF(zw1),DEPTHOF(zw2)))
+
+#define UPHEAP(z) \
+{ \
+ Int32 zz, tmp; \
+ zz = z; tmp = heap[zz]; \
+ while (weight[tmp] < weight[heap[zz >> 1]]) { \
+ heap[zz] = heap[zz >> 1]; \
+ zz >>= 1; \
+ } \
+ heap[zz] = tmp; \
+}
+
+#define DOWNHEAP(z) \
+{ \
+ Int32 zz, yy, tmp; \
+ zz = z; tmp = heap[zz]; \
+ while (True) { \
+ yy = zz << 1; \
+ if (yy > nHeap) break; \
+ if (yy < nHeap && \
+ weight[heap[yy+1]] < weight[heap[yy]]) \
+ yy++; \
+ if (weight[tmp] < weight[heap[yy]]) break; \
+ heap[zz] = heap[yy]; \
+ zz = yy; \
+ } \
+ heap[zz] = tmp; \
+}
+
+
+/*---------------------------------------------------*/
+void BZ2_hbMakeCodeLengths ( UChar *len,
+ Int32 *freq,
+ Int32 alphaSize,
+ Int32 maxLen )
+{
+ /*--
+ Nodes and heap entries run from 1. Entry 0
+ for both the heap and nodes is a sentinel.
+ --*/
+ Int32 nNodes, nHeap, n1, n2, i, j, k;
+ Bool tooLong;
+
+ Int32 heap [ BZ_MAX_ALPHA_SIZE + 2 ];
+ Int32 weight [ BZ_MAX_ALPHA_SIZE * 2 ];
+ Int32 parent [ BZ_MAX_ALPHA_SIZE * 2 ];
+
+ for (i = 0; i < alphaSize; i++)
+ weight[i+1] = (freq[i] == 0 ? 1 : freq[i]) << 8;
+
+ while (True) {
+
+ nNodes = alphaSize;
+ nHeap = 0;
+
+ heap[0] = 0;
+ weight[0] = 0;
+ parent[0] = -2;
+
+ for (i = 1; i <= alphaSize; i++) {
+ parent[i] = -1;
+ nHeap++;
+ heap[nHeap] = i;
+ UPHEAP(nHeap);
+ }
+
+ AssertH( nHeap < (BZ_MAX_ALPHA_SIZE+2), 2001 );
+
+ while (nHeap > 1) {
+ n1 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
+ n2 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
+ nNodes++;
+ parent[n1] = parent[n2] = nNodes;
+ weight[nNodes] = ADDWEIGHTS(weight[n1], weight[n2]);
+ parent[nNodes] = -1;
+ nHeap++;
+ heap[nHeap] = nNodes;
+ UPHEAP(nHeap);
+ }
+
+ AssertH( nNodes < (BZ_MAX_ALPHA_SIZE * 2), 2002 );
+
+ tooLong = False;
+ for (i = 1; i <= alphaSize; i++) {
+ j = 0;
+ k = i;
+ while (parent[k] >= 0) { k = parent[k]; j++; }
+ len[i-1] = j;
+ if (j > maxLen) tooLong = True;
+ }
+
+ if (! tooLong) break;
+
+ for (i = 1; i < alphaSize; i++) {
+ j = weight[i] >> 8;
+ j = 1 + (j / 2);
+ weight[i] = j << 8;
+ }
+ }
+}
+
+
+/*---------------------------------------------------*/
+void BZ2_hbAssignCodes ( Int32 *code,
+ UChar *length,
+ Int32 minLen,
+ Int32 maxLen,
+ Int32 alphaSize )
+{
+ Int32 n, vec, i;
+
+ vec = 0;
+ for (n = minLen; n <= maxLen; n++) {
+ for (i = 0; i < alphaSize; i++)
+ if (length[i] == n) { code[i] = vec; vec++; };
+ vec <<= 1;
+ }
+}
+
+
+/*---------------------------------------------------*/
+void BZ2_hbCreateDecodeTables ( Int32 *limit,
+ Int32 *base,
+ Int32 *perm,
+ UChar *length,
+ Int32 minLen,
+ Int32 maxLen,
+ Int32 alphaSize )
+{
+ Int32 pp, i, j, vec;
+
+ pp = 0;
+ for (i = minLen; i <= maxLen; i++)
+ for (j = 0; j < alphaSize; j++)
+ if (length[j] == i) { perm[pp] = j; pp++; };
+
+ for (i = 0; i < BZ_MAX_CODE_LEN; i++) base[i] = 0;
+ for (i = 0; i < alphaSize; i++) base[length[i]+1]++;
+
+ for (i = 1; i < BZ_MAX_CODE_LEN; i++) base[i] += base[i-1];
+
+ for (i = 0; i < BZ_MAX_CODE_LEN; i++) limit[i] = 0;
+ vec = 0;
+
+ for (i = minLen; i <= maxLen; i++) {
+ vec += (base[i+1] - base[i]);
+ limit[i] = vec-1;
+ vec <<= 1;
+ }
+ for (i = minLen + 1; i <= maxLen; i++)
+ base[i] = ((limit[i-1] + 1) << 1) - base[i];
+}
+
+
+/*-------------------------------------------------------------*/
+/*--- end huffman.c ---*/
+/*-------------------------------------------------------------*/
--- /dev/null
+/*
+ * This file is a modified version of bzlib_private.h from the bzip2-1.0.2
+ * distribution which can be found at http://sources.redhat.com/bzip2/
+ */
+
+/*-------------------------------------------------------------*/
+/*--- Private header file for the library. ---*/
+/*--- bzlib_private.h ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+ This file is a part of bzip2 and/or libbzip2, a program and
+ library for lossless, block-sorting data compression.
+
+ Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+ 3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+ 4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Julian Seward, Cambridge, UK.
+ jseward@acm.org
+ bzip2/libbzip2 version 1.0 of 21 March 2000
+
+ This program is based on (at least) the work of:
+ Mike Burrows
+ David Wheeler
+ Peter Fenwick
+ Alistair Moffat
+ Radford Neal
+ Ian H. Witten
+ Robert Sedgewick
+ Jon L. Bentley
+
+ For more information on these sources, see the manual.
+--*/
+
+
+#ifndef _BZLIB_PRIVATE_H
+#define _BZLIB_PRIVATE_H
+
+#include <malloc.h>
+
+#include "bzlib.h"
+
+#ifndef BZ_NO_STDIO
+#include <stdio.h>
+#include <ctype.h>
+#include <string.h>
+#endif
+
+
+/*-- General stuff. --*/
+
+#define BZ_VERSION "1.0.2, 30-Dec-2001"
+
+typedef char Char;
+typedef unsigned char Bool;
+typedef unsigned char UChar;
+typedef int Int32;
+typedef unsigned int UInt32;
+typedef short Int16;
+typedef unsigned short UInt16;
+
+#define True ((Bool)1)
+#define False ((Bool)0)
+
+#ifndef __GNUC__
+#define __inline__ /* */
+#endif
+
+#ifndef BZ_NO_STDIO
+extern void BZ2_bz__AssertH__fail ( int errcode );
+#define AssertH(cond,errcode) \
+ { if (!(cond)) BZ2_bz__AssertH__fail ( errcode ); }
+#if BZ_DEBUG
+#define AssertD(cond,msg) \
+ { if (!(cond)) { \
+ fprintf ( stderr, \
+ "\n\nlibbzip2(debug build): internal error\n\t%s\n", msg );\
+ exit(1); \
+ }}
+#else
+#define AssertD(cond,msg) /* */
+#endif
+#define VPrintf0(zf) \
+ fprintf(stderr,zf)
+#define VPrintf1(zf,za1) \
+ fprintf(stderr,zf,za1)
+#define VPrintf2(zf,za1,za2) \
+ fprintf(stderr,zf,za1,za2)
+#define VPrintf3(zf,za1,za2,za3) \
+ fprintf(stderr,zf,za1,za2,za3)
+#define VPrintf4(zf,za1,za2,za3,za4) \
+ fprintf(stderr,zf,za1,za2,za3,za4)
+#define VPrintf5(zf,za1,za2,za3,za4,za5) \
+ fprintf(stderr,zf,za1,za2,za3,za4,za5)
+#else
+extern void bz_internal_error ( int errcode );
+#define AssertH(cond,errcode) \
+ { if (!(cond)) bz_internal_error ( errcode ); }
+#define AssertD(cond,msg) /* */
+#define VPrintf0(zf) /* */
+#define VPrintf1(zf,za1) /* */
+#define VPrintf2(zf,za1,za2) /* */
+#define VPrintf3(zf,za1,za2,za3) /* */
+#define VPrintf4(zf,za1,za2,za3,za4) /* */
+#define VPrintf5(zf,za1,za2,za3,za4,za5) /* */
+#endif
+
+
+#define BZALLOC(nnn) (strm->bzalloc)(strm->opaque,(nnn),1)
+#define BZFREE(ppp) (strm->bzfree)(strm->opaque,(ppp))
+
+
+/*-- Header bytes. --*/
+
+#define BZ_HDR_B 0x42 /* 'B' */
+#define BZ_HDR_Z 0x5a /* 'Z' */
+#define BZ_HDR_h 0x68 /* 'h' */
+#define BZ_HDR_0 0x30 /* '0' */
+
+/*-- Constants for the back end. --*/
+
+#define BZ_MAX_ALPHA_SIZE 258
+#define BZ_MAX_CODE_LEN 23
+
+#define BZ_RUNA 0
+#define BZ_RUNB 1
+
+#define BZ_N_GROUPS 6
+#define BZ_G_SIZE 50
+#define BZ_N_ITERS 4
+
+#define BZ_MAX_SELECTORS (2 + (900000 / BZ_G_SIZE))
+
+
+/*-- Stuff for randomising repetitive blocks. --*/
+
+extern Int32 BZ2_rNums[512];
+
+#define BZ_RAND_DECLS \
+ Int32 rNToGo; \
+ Int32 rTPos \
+
+#define BZ_RAND_INIT_MASK \
+ s->rNToGo = 0; \
+ s->rTPos = 0 \
+
+#define BZ_RAND_MASK ((s->rNToGo == 1) ? 1 : 0)
+
+#define BZ_RAND_UPD_MASK \
+ if (s->rNToGo == 0) { \
+ s->rNToGo = BZ2_rNums[s->rTPos]; \
+ s->rTPos++; \
+ if (s->rTPos == 512) s->rTPos = 0; \
+ } \
+ s->rNToGo--;
+
+
+/*-- Stuff for doing CRCs. --*/
+
+extern UInt32 BZ2_crc32Table[256];
+
+#define BZ_INITIALISE_CRC(crcVar) \
+{ \
+ crcVar = 0xffffffffL; \
+}
+
+#define BZ_FINALISE_CRC(crcVar) \
+{ \
+ crcVar = ~(crcVar); \
+}
+
+#define BZ_UPDATE_CRC(crcVar,cha) \
+{ \
+ crcVar = (crcVar << 8) ^ \
+ BZ2_crc32Table[(crcVar >> 24) ^ \
+ ((UChar)cha)]; \
+}
+
+
+/*-- States and modes for compression. --*/
+
+#define BZ_M_IDLE 1
+#define BZ_M_RUNNING 2
+#define BZ_M_FLUSHING 3
+#define BZ_M_FINISHING 4
+
+#define BZ_S_OUTPUT 1
+#define BZ_S_INPUT 2
+
+#define BZ_N_RADIX 2
+#define BZ_N_QSORT 12
+#define BZ_N_SHELL 18
+#define BZ_N_OVERSHOOT (BZ_N_RADIX + BZ_N_QSORT + BZ_N_SHELL + 2)
+
+
+/*-- Structure holding all the compression-side stuff. --*/
+
+typedef
+ struct {
+ /* pointer back to the struct bz_stream */
+ bz_stream* strm;
+
+ /* mode this stream is in, and whether inputting */
+ /* or outputting data */
+ Int32 mode;
+ Int32 state;
+
+ /* remembers avail_in when flush/finish requested */
+ UInt32 avail_in_expect;
+
+ /* for doing the block sorting */
+ UInt32* arr1;
+ UInt32* arr2;
+ UInt32* ftab;
+ Int32 origPtr;
+
+ /* aliases for arr1 and arr2 */
+ UInt32* ptr;
+ UChar* block;
+ UInt16* mtfv;
+ UChar* zbits;
+
+ /* for deciding when to use the fallback sorting algorithm */
+ Int32 workFactor;
+
+ /* run-length-encoding of the input */
+ UInt32 state_in_ch;
+ Int32 state_in_len;
+ BZ_RAND_DECLS;
+
+ /* input and output limits and current posns */
+ Int32 nblock;
+ Int32 nblockMAX;
+ Int32 numZ;
+ Int32 state_out_pos;
+
+ /* map of bytes used in block */
+ Int32 nInUse;
+ Bool inUse[256];
+ UChar unseqToSeq[256];
+
+ /* the buffer for bit stream creation */
+ UInt32 bsBuff;
+ Int32 bsLive;
+
+ /* block and combined CRCs */
+ UInt32 blockCRC;
+ UInt32 combinedCRC;
+
+ /* misc administratium */
+ Int32 verbosity;
+ Int32 blockNo;
+ Int32 blockSize100k;
+
+ /* stuff for coding the MTF values */
+ Int32 nMTF;
+ Int32 mtfFreq [BZ_MAX_ALPHA_SIZE];
+ UChar selector [BZ_MAX_SELECTORS];
+ UChar selectorMtf[BZ_MAX_SELECTORS];
+
+ UChar len [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+ Int32 code [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+ Int32 rfreq [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+ /* second dimension: only 3 needed; 4 makes index calculations faster */
+ UInt32 len_pack[BZ_MAX_ALPHA_SIZE][4];
+
+ }
+ EState;
+
+
+/*-- externs for compression. --*/
+
+extern void
+BZ2_blockSort ( EState* );
+
+extern void
+BZ2_compressBlock ( EState*, Bool );
+
+extern void
+BZ2_bsInitWrite ( EState* );
+
+extern void
+BZ2_hbAssignCodes ( Int32*, UChar*, Int32, Int32, Int32 );
+
+extern void
+BZ2_hbMakeCodeLengths ( UChar*, Int32*, Int32, Int32 );
+
+
+/*-- states for decompression. --*/
+
+#define BZ_X_IDLE 1
+#define BZ_X_OUTPUT 2
+
+#define BZ_X_MAGIC_1 10
+#define BZ_X_MAGIC_2 11
+#define BZ_X_MAGIC_3 12
+#define BZ_X_MAGIC_4 13
+#define BZ_X_BLKHDR_1 14
+#define BZ_X_BLKHDR_2 15
+#define BZ_X_BLKHDR_3 16
+#define BZ_X_BLKHDR_4 17
+#define BZ_X_BLKHDR_5 18
+#define BZ_X_BLKHDR_6 19
+#define BZ_X_BCRC_1 20
+#define BZ_X_BCRC_2 21
+#define BZ_X_BCRC_3 22
+#define BZ_X_BCRC_4 23
+#define BZ_X_RANDBIT 24
+#define BZ_X_ORIGPTR_1 25
+#define BZ_X_ORIGPTR_2 26
+#define BZ_X_ORIGPTR_3 27
+#define BZ_X_MAPPING_1 28
+#define BZ_X_MAPPING_2 29
+#define BZ_X_SELECTOR_1 30
+#define BZ_X_SELECTOR_2 31
+#define BZ_X_SELECTOR_3 32
+#define BZ_X_CODING_1 33
+#define BZ_X_CODING_2 34
+#define BZ_X_CODING_3 35
+#define BZ_X_MTF_1 36
+#define BZ_X_MTF_2 37
+#define BZ_X_MTF_3 38
+#define BZ_X_MTF_4 39
+#define BZ_X_MTF_5 40
+#define BZ_X_MTF_6 41
+#define BZ_X_ENDHDR_2 42
+#define BZ_X_ENDHDR_3 43
+#define BZ_X_ENDHDR_4 44
+#define BZ_X_ENDHDR_5 45
+#define BZ_X_ENDHDR_6 46
+#define BZ_X_CCRC_1 47
+#define BZ_X_CCRC_2 48
+#define BZ_X_CCRC_3 49
+#define BZ_X_CCRC_4 50
+
+
+/*-- Constants for the fast MTF decoder. --*/
+
+#define MTFA_SIZE 4096
+#define MTFL_SIZE 16
+
+
+/*-- Structure holding all the decompression-side stuff. --*/
+
+typedef
+ struct {
+ /* pointer back to the struct bz_stream */
+ bz_stream* strm;
+
+ /* state indicator for this stream */
+ Int32 state;
+
+ /* for doing the final run-length decoding */
+ UChar state_out_ch;
+ Int32 state_out_len;
+ Bool blockRandomised;
+ BZ_RAND_DECLS;
+
+ /* the buffer for bit stream reading */
+ UInt32 bsBuff;
+ Int32 bsLive;
+
+ /* misc administratium */
+ Int32 blockSize100k;
+ Bool smallDecompress;
+ Int32 currBlockNo;
+ Int32 verbosity;
+
+ /* for undoing the Burrows-Wheeler transform */
+ Int32 origPtr;
+ UInt32 tPos;
+ Int32 k0;
+ Int32 unzftab[256];
+ Int32 nblock_used;
+ Int32 cftab[257];
+ Int32 cftabCopy[257];
+
+ /* for undoing the Burrows-Wheeler transform (FAST) */
+ UInt32 *tt;
+
+ /* for undoing the Burrows-Wheeler transform (SMALL) */
+ UInt16 *ll16;
+ UChar *ll4;
+
+ /* stored and calculated CRCs */
+ UInt32 storedBlockCRC;
+ UInt32 storedCombinedCRC;
+ UInt32 calculatedBlockCRC;
+ UInt32 calculatedCombinedCRC;
+
+ /* map of bytes used in block */
+ Int32 nInUse;
+ Bool inUse[256];
+ Bool inUse16[16];
+ UChar seqToUnseq[256];
+
+ /* for decoding the MTF values */
+ UChar mtfa [MTFA_SIZE];
+ Int32 mtfbase[256 / MTFL_SIZE];
+ UChar selector [BZ_MAX_SELECTORS];
+ UChar selectorMtf[BZ_MAX_SELECTORS];
+ UChar len [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+
+ Int32 limit [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+ Int32 base [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+ Int32 perm [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+ Int32 minLens[BZ_N_GROUPS];
+
+ /* save area for scalars in the main decompress code */
+ Int32 save_i;
+ Int32 save_j;
+ Int32 save_t;
+ Int32 save_alphaSize;
+ Int32 save_nGroups;
+ Int32 save_nSelectors;
+ Int32 save_EOB;
+ Int32 save_groupNo;
+ Int32 save_groupPos;
+ Int32 save_nextSym;
+ Int32 save_nblockMAX;
+ Int32 save_nblock;
+ Int32 save_es;
+ Int32 save_N;
+ Int32 save_curr;
+ Int32 save_zt;
+ Int32 save_zn;
+ Int32 save_zvec;
+ Int32 save_zj;
+ Int32 save_gSel;
+ Int32 save_gMinlen;
+ Int32* save_gLimit;
+ Int32* save_gBase;
+ Int32* save_gPerm;
+
+ }
+ DState;
+
+
+/*-- Macros for decompression. --*/
+
+#define BZ_GET_FAST(cccc) \
+ s->tPos = s->tt[s->tPos]; \
+ cccc = (UChar)(s->tPos & 0xff); \
+ s->tPos >>= 8;
+
+#define BZ_GET_FAST_C(cccc) \
+ c_tPos = c_tt[c_tPos]; \
+ cccc = (UChar)(c_tPos & 0xff); \
+ c_tPos >>= 8;
+
+#define SET_LL4(i,n) \
+ { if (((i) & 0x1) == 0) \
+ s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0xf0) | (n); else \
+ s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0x0f) | ((n) << 4); \
+ }
+
+#define GET_LL4(i) \
+ ((((UInt32)(s->ll4[(i) >> 1])) >> (((i) << 2) & 0x4)) & 0xF)
+
+#define SET_LL(i,n) \
+ { s->ll16[i] = (UInt16)(n & 0x0000ffff); \
+ SET_LL4(i, n >> 16); \
+ }
+
+#define GET_LL(i) \
+ (((UInt32)s->ll16[i]) | (GET_LL4(i) << 16))
+
+#define BZ_GET_SMALL(cccc) \
+ cccc = BZ2_indexIntoF ( s->tPos, s->cftab ); \
+ s->tPos = GET_LL(s->tPos);
+
+
+/*-- externs for decompression. --*/
+
+extern Int32
+BZ2_indexIntoF ( Int32, Int32* );
+
+extern Int32
+BZ2_decompress ( DState* );
+
+extern void
+BZ2_hbCreateDecodeTables ( Int32*, Int32*, Int32*, UChar*,
+ Int32, Int32, Int32 );
+
+
+#endif
+
+
+/*-- BZ_NO_STDIO seems to make NULL disappear on some platforms. --*/
+
+#ifdef BZ_NO_STDIO
+#ifndef NULL
+#define NULL 0
+#endif
+#endif
+
+
+/*-------------------------------------------------------------*/
+/*--- end bzlib_private.h ---*/
+/*-------------------------------------------------------------*/
--- /dev/null
+#include <config.h>
+
+/*-------------------------------------------------------------*/
+/*--- Table for randomising repetitive blocks ---*/
+/*--- randtable.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+ This file is a part of bzip2 and/or libbzip2, a program and
+ library for lossless, block-sorting data compression.
+
+ Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. The origin of this software must not be misrepresented; you must
+ not claim that you wrote the original software. If you use this
+ software in a product, an acknowledgment in the product
+ documentation would be appreciated but is not required.
+
+ 3. Altered source versions must be plainly marked as such, and must
+ not be misrepresented as being the original software.
+
+ 4. The name of the author may not be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Julian Seward, Cambridge, UK.
+ jseward@acm.org
+ bzip2/libbzip2 version 1.0 of 21 March 2000
+
+ This program is based on (at least) the work of:
+ Mike Burrows
+ David Wheeler
+ Peter Fenwick
+ Alistair Moffat
+ Radford Neal
+ Ian H. Witten
+ Robert Sedgewick
+ Jon L. Bentley
+
+ For more information on these sources, see the manual.
+--*/
+
+
+#include "bzlib_private.h"
+
+
+/*---------------------------------------------*/
+Int32 BZ2_rNums[512] = {
+ 619, 720, 127, 481, 931, 816, 813, 233, 566, 247,
+ 985, 724, 205, 454, 863, 491, 741, 242, 949, 214,
+ 733, 859, 335, 708, 621, 574, 73, 654, 730, 472,
+ 419, 436, 278, 496, 867, 210, 399, 680, 480, 51,
+ 878, 465, 811, 169, 869, 675, 611, 697, 867, 561,
+ 862, 687, 507, 283, 482, 129, 807, 591, 733, 623,
+ 150, 238, 59, 379, 684, 877, 625, 169, 643, 105,
+ 170, 607, 520, 932, 727, 476, 693, 425, 174, 647,
+ 73, 122, 335, 530, 442, 853, 695, 249, 445, 515,
+ 909, 545, 703, 919, 874, 474, 882, 500, 594, 612,
+ 641, 801, 220, 162, 819, 984, 589, 513, 495, 799,
+ 161, 604, 958, 533, 221, 400, 386, 867, 600, 782,
+ 382, 596, 414, 171, 516, 375, 682, 485, 911, 276,
+ 98, 553, 163, 354, 666, 933, 424, 341, 533, 870,
+ 227, 730, 475, 186, 263, 647, 537, 686, 600, 224,
+ 469, 68, 770, 919, 190, 373, 294, 822, 808, 206,
+ 184, 943, 795, 384, 383, 461, 404, 758, 839, 887,
+ 715, 67, 618, 276, 204, 918, 873, 777, 604, 560,
+ 951, 160, 578, 722, 79, 804, 96, 409, 713, 940,
+ 652, 934, 970, 447, 318, 353, 859, 672, 112, 785,
+ 645, 863, 803, 350, 139, 93, 354, 99, 820, 908,
+ 609, 772, 154, 274, 580, 184, 79, 626, 630, 742,
+ 653, 282, 762, 623, 680, 81, 927, 626, 789, 125,
+ 411, 521, 938, 300, 821, 78, 343, 175, 128, 250,
+ 170, 774, 972, 275, 999, 639, 495, 78, 352, 126,
+ 857, 956, 358, 619, 580, 124, 737, 594, 701, 612,
+ 669, 112, 134, 694, 363, 992, 809, 743, 168, 974,
+ 944, 375, 748, 52, 600, 747, 642, 182, 862, 81,
+ 344, 805, 988, 739, 511, 655, 814, 334, 249, 515,
+ 897, 955, 664, 981, 649, 113, 974, 459, 893, 228,
+ 433, 837, 553, 268, 926, 240, 102, 654, 459, 51,
+ 686, 754, 806, 760, 493, 403, 415, 394, 687, 700,
+ 946, 670, 656, 610, 738, 392, 760, 799, 887, 653,
+ 978, 321, 576, 617, 626, 502, 894, 679, 243, 440,
+ 680, 879, 194, 572, 640, 724, 926, 56, 204, 700,
+ 707, 151, 457, 449, 797, 195, 791, 558, 945, 679,
+ 297, 59, 87, 824, 713, 663, 412, 693, 342, 606,
+ 134, 108, 571, 364, 631, 212, 174, 643, 304, 329,
+ 343, 97, 430, 751, 497, 314, 983, 374, 822, 928,
+ 140, 206, 73, 263, 980, 736, 876, 478, 430, 305,
+ 170, 514, 364, 692, 829, 82, 855, 953, 676, 246,
+ 369, 970, 294, 750, 807, 827, 150, 790, 288, 923,
+ 804, 378, 215, 828, 592, 281, 565, 555, 710, 82,
+ 896, 831, 547, 261, 524, 462, 293, 465, 502, 56,
+ 661, 821, 976, 991, 658, 869, 905, 758, 745, 193,
+ 768, 550, 608, 933, 378, 286, 215, 979, 792, 961,
+ 61, 688, 793, 644, 986, 403, 106, 366, 905, 644,
+ 372, 567, 466, 434, 645, 210, 389, 550, 919, 135,
+ 780, 773, 635, 389, 707, 100, 626, 958, 165, 504,
+ 920, 176, 193, 713, 857, 265, 203, 50, 668, 108,
+ 645, 990, 626, 197, 510, 357, 358, 850, 858, 364,
+ 936, 638
+};
+
+
+/*-------------------------------------------------------------*/
+/*--- end randtable.c ---*/
+/*-------------------------------------------------------------*/
+++ /dev/null
-#include <config.h>
-#include <common.h>
-#include <watchdog.h>
-
-/*
- * This file is a modified version of bzlib.c from the bzip2-1.0.2
- * distribution which can be found at http://sources.redhat.com/bzip2/
- */
-
-/*-------------------------------------------------------------*/
-/*--- Library top-level functions. ---*/
-/*--- bzlib.c ---*/
-/*-------------------------------------------------------------*/
-
-/*--
- This file is a part of bzip2 and/or libbzip2, a program and
- library for lossless, block-sorting data compression.
-
- Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. The origin of this software must not be misrepresented; you must
- not claim that you wrote the original software. If you use this
- software in a product, an acknowledgment in the product
- documentation would be appreciated but is not required.
-
- 3. Altered source versions must be plainly marked as such, and must
- not be misrepresented as being the original software.
-
- 4. The name of the author may not be used to endorse or promote
- products derived from this software without specific prior written
- permission.
-
- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- Julian Seward, Cambridge, UK.
- jseward@acm.org
- bzip2/libbzip2 version 1.0 of 21 March 2000
-
- This program is based on (at least) the work of:
- Mike Burrows
- David Wheeler
- Peter Fenwick
- Alistair Moffat
- Radford Neal
- Ian H. Witten
- Robert Sedgewick
- Jon L. Bentley
-
- For more information on these sources, see the manual.
---*/
-
-/*--
- CHANGES
- ~~~~~~~
- 0.9.0 -- original version.
-
- 0.9.0a/b -- no changes in this file.
-
- 0.9.0c
- * made zero-length BZ_FLUSH work correctly in bzCompress().
- * fixed bzWrite/bzRead to ignore zero-length requests.
- * fixed bzread to correctly handle read requests after EOF.
- * wrong parameter order in call to bzDecompressInit in
- bzBuffToBuffDecompress. Fixed.
---*/
-
-#include "bzlib_private.h"
-
-/*---------------------------------------------------*/
-/*--- Compression stuff ---*/
-/*---------------------------------------------------*/
-
-
-/*---------------------------------------------------*/
-#ifndef BZ_NO_STDIO
-void BZ2_bz__AssertH__fail ( int errcode )
-{
- fprintf(stderr,
- "\n\nbzip2/libbzip2: internal error number %d.\n"
- "This is a bug in bzip2/libbzip2, %s.\n"
- "Please report it to me at: jseward@acm.org. If this happened\n"
- "when you were using some program which uses libbzip2 as a\n"
- "component, you should also report this bug to the author(s)\n"
- "of that program. Please make an effort to report this bug;\n"
- "timely and accurate bug reports eventually lead to higher\n"
- "quality software. Thanks. Julian Seward, 30 December 2001.\n\n",
- errcode,
- BZ2_bzlibVersion()
- );
-
- if (errcode == 1007) {
- fprintf(stderr,
- "\n*** A special note about internal error number 1007 ***\n"
- "\n"
- "Experience suggests that a common cause of i.e. 1007\n"
- "is unreliable memory or other hardware. The 1007 assertion\n"
- "just happens to cross-check the results of huge numbers of\n"
- "memory reads/writes, and so acts (unintendedly) as a stress\n"
- "test of your memory system.\n"
- "\n"
- "I suggest the following: try compressing the file again,\n"
- "possibly monitoring progress in detail with the -vv flag.\n"
- "\n"
- "* If the error cannot be reproduced, and/or happens at different\n"
- " points in compression, you may have a flaky memory system.\n"
- " Try a memory-test program. I have used Memtest86\n"
- " (www.memtest86.com). At the time of writing it is free (GPLd).\n"
- " Memtest86 tests memory much more thorougly than your BIOSs\n"
- " power-on test, and may find failures that the BIOS doesn't.\n"
- "\n"
- "* If the error can be repeatably reproduced, this is a bug in\n"
- " bzip2, and I would very much like to hear about it. Please\n"
- " let me know, and, ideally, save a copy of the file causing the\n"
- " problem -- without which I will be unable to investigate it.\n"
- "\n"
- );
- }
-
- exit(3);
-}
-#endif
-
-
-/*---------------------------------------------------*/
-static
-int bz_config_ok ( void )
-{
- if (sizeof(int) != 4) return 0;
- if (sizeof(short) != 2) return 0;
- if (sizeof(char) != 1) return 0;
- return 1;
-}
-
-
-/*---------------------------------------------------*/
-static
-void* default_bzalloc ( void* opaque, Int32 items, Int32 size )
-{
- void* v = malloc ( items * size );
- return v;
-}
-
-static
-void default_bzfree ( void* opaque, void* addr )
-{
- if (addr != NULL) free ( addr );
-}
-
-#ifndef BZ_NO_COMPRESS
-/*---------------------------------------------------*/
-static
-void prepare_new_block ( EState* s )
-{
- Int32 i;
- s->nblock = 0;
- s->numZ = 0;
- s->state_out_pos = 0;
- BZ_INITIALISE_CRC ( s->blockCRC );
- for (i = 0; i < 256; i++) s->inUse[i] = False;
- s->blockNo++;
-}
-
-
-/*---------------------------------------------------*/
-static
-void init_RL ( EState* s )
-{
- s->state_in_ch = 256;
- s->state_in_len = 0;
-}
-
-
-static
-Bool isempty_RL ( EState* s )
-{
- if (s->state_in_ch < 256 && s->state_in_len > 0)
- return False; else
- return True;
-}
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzCompressInit)
- ( bz_stream* strm,
- int blockSize100k,
- int verbosity,
- int workFactor )
-{
- Int32 n;
- EState* s;
-
- if (!bz_config_ok()) return BZ_CONFIG_ERROR;
-
- if (strm == NULL ||
- blockSize100k < 1 || blockSize100k > 9 ||
- workFactor < 0 || workFactor > 250)
- return BZ_PARAM_ERROR;
-
- if (workFactor == 0) workFactor = 30;
- if (strm->bzalloc == NULL) strm->bzalloc = default_bzalloc;
- if (strm->bzfree == NULL) strm->bzfree = default_bzfree;
-
- s = BZALLOC( sizeof(EState) );
- if (s == NULL) return BZ_MEM_ERROR;
- s->strm = strm;
-
- s->arr1 = NULL;
- s->arr2 = NULL;
- s->ftab = NULL;
-
- n = 100000 * blockSize100k;
- s->arr1 = BZALLOC( n * sizeof(UInt32) );
- s->arr2 = BZALLOC( (n+BZ_N_OVERSHOOT) * sizeof(UInt32) );
- s->ftab = BZALLOC( 65537 * sizeof(UInt32) );
-
- if (s->arr1 == NULL || s->arr2 == NULL || s->ftab == NULL) {
- if (s->arr1 != NULL) BZFREE(s->arr1);
- if (s->arr2 != NULL) BZFREE(s->arr2);
- if (s->ftab != NULL) BZFREE(s->ftab);
- if (s != NULL) BZFREE(s);
- return BZ_MEM_ERROR;
- }
-
- s->blockNo = 0;
- s->state = BZ_S_INPUT;
- s->mode = BZ_M_RUNNING;
- s->combinedCRC = 0;
- s->blockSize100k = blockSize100k;
- s->nblockMAX = 100000 * blockSize100k - 19;
- s->verbosity = verbosity;
- s->workFactor = workFactor;
-
- s->block = (UChar*)s->arr2;
- s->mtfv = (UInt16*)s->arr1;
- s->zbits = NULL;
- s->ptr = (UInt32*)s->arr1;
-
- strm->state = s;
- strm->total_in_lo32 = 0;
- strm->total_in_hi32 = 0;
- strm->total_out_lo32 = 0;
- strm->total_out_hi32 = 0;
- init_RL ( s );
- prepare_new_block ( s );
- return BZ_OK;
-}
-
-
-/*---------------------------------------------------*/
-static
-void add_pair_to_block ( EState* s )
-{
- Int32 i;
- UChar ch = (UChar)(s->state_in_ch);
- for (i = 0; i < s->state_in_len; i++) {
- BZ_UPDATE_CRC( s->blockCRC, ch );
- }
- s->inUse[s->state_in_ch] = True;
- switch (s->state_in_len) {
- case 1:
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- break;
- case 2:
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- break;
- case 3:
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- break;
- default:
- s->inUse[s->state_in_len-4] = True;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = ((UChar)(s->state_in_len-4));
- s->nblock++;
- break;
- }
-}
-
-
-/*---------------------------------------------------*/
-static
-void flush_RL ( EState* s )
-{
- if (s->state_in_ch < 256) add_pair_to_block ( s );
- init_RL ( s );
-}
-
-
-/*---------------------------------------------------*/
-#define ADD_CHAR_TO_BLOCK(zs,zchh0) \
-{ \
- UInt32 zchh = (UInt32)(zchh0); \
- /*-- fast track the common case --*/ \
- if (zchh != zs->state_in_ch && \
- zs->state_in_len == 1) { \
- UChar ch = (UChar)(zs->state_in_ch); \
- BZ_UPDATE_CRC( zs->blockCRC, ch ); \
- zs->inUse[zs->state_in_ch] = True; \
- zs->block[zs->nblock] = (UChar)ch; \
- zs->nblock++; \
- zs->state_in_ch = zchh; \
- } \
- else \
- /*-- general, uncommon cases --*/ \
- if (zchh != zs->state_in_ch || \
- zs->state_in_len == 255) { \
- if (zs->state_in_ch < 256) \
- add_pair_to_block ( zs ); \
- zs->state_in_ch = zchh; \
- zs->state_in_len = 1; \
- } else { \
- zs->state_in_len++; \
- } \
-}
-
-
-/*---------------------------------------------------*/
-static
-Bool copy_input_until_stop ( EState* s )
-{
- Bool progress_in = False;
-
- if (s->mode == BZ_M_RUNNING) {
-
- /*-- fast track the common case --*/
- while (True) {
- /*-- block full? --*/
- if (s->nblock >= s->nblockMAX) break;
- /*-- no input? --*/
- if (s->strm->avail_in == 0) break;
- progress_in = True;
- ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) );
- s->strm->next_in++;
- s->strm->avail_in--;
- s->strm->total_in_lo32++;
- if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++;
- }
-
- } else {
-
- /*-- general, uncommon case --*/
- while (True) {
- /*-- block full? --*/
- if (s->nblock >= s->nblockMAX) break;
- /*-- no input? --*/
- if (s->strm->avail_in == 0) break;
- /*-- flush/finish end? --*/
- if (s->avail_in_expect == 0) break;
- progress_in = True;
- ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) );
- s->strm->next_in++;
- s->strm->avail_in--;
- s->strm->total_in_lo32++;
- if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++;
- s->avail_in_expect--;
- }
- }
- return progress_in;
-}
-
-
-/*---------------------------------------------------*/
-static
-Bool copy_output_until_stop ( EState* s )
-{
- Bool progress_out = False;
-
- while (True) {
-
- /*-- no output space? --*/
- if (s->strm->avail_out == 0) break;
-
- /*-- block done? --*/
- if (s->state_out_pos >= s->numZ) break;
-
- progress_out = True;
- *(s->strm->next_out) = s->zbits[s->state_out_pos];
- s->state_out_pos++;
- s->strm->avail_out--;
- s->strm->next_out++;
- s->strm->total_out_lo32++;
- if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
- }
-
- return progress_out;
-}
-
-
-/*---------------------------------------------------*/
-static
-Bool handle_compress ( bz_stream* strm )
-{
- Bool progress_in = False;
- Bool progress_out = False;
- EState* s = strm->state;
-
- while (True) {
-
- if (s->state == BZ_S_OUTPUT) {
- progress_out |= copy_output_until_stop ( s );
- if (s->state_out_pos < s->numZ) break;
- if (s->mode == BZ_M_FINISHING &&
- s->avail_in_expect == 0 &&
- isempty_RL(s)) break;
- prepare_new_block ( s );
- s->state = BZ_S_INPUT;
- if (s->mode == BZ_M_FLUSHING &&
- s->avail_in_expect == 0 &&
- isempty_RL(s)) break;
- }
-
- if (s->state == BZ_S_INPUT) {
- progress_in |= copy_input_until_stop ( s );
- if (s->mode != BZ_M_RUNNING && s->avail_in_expect == 0) {
- flush_RL ( s );
- BZ2_compressBlock ( s, (Bool)(s->mode == BZ_M_FINISHING) );
- s->state = BZ_S_OUTPUT;
- }
- else
- if (s->nblock >= s->nblockMAX) {
- BZ2_compressBlock ( s, False );
- s->state = BZ_S_OUTPUT;
- }
- else
- if (s->strm->avail_in == 0) {
- break;
- }
- }
-
- }
-
- return progress_in || progress_out;
-}
-
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzCompress) ( bz_stream *strm, int action )
-{
- Bool progress;
- EState* s;
- if (strm == NULL) return BZ_PARAM_ERROR;
- s = strm->state;
- if (s == NULL) return BZ_PARAM_ERROR;
- if (s->strm != strm) return BZ_PARAM_ERROR;
-
- preswitch:
- switch (s->mode) {
-
- case BZ_M_IDLE:
- return BZ_SEQUENCE_ERROR;
-
- case BZ_M_RUNNING:
- if (action == BZ_RUN) {
- progress = handle_compress ( strm );
- return progress ? BZ_RUN_OK : BZ_PARAM_ERROR;
- }
- else
- if (action == BZ_FLUSH) {
- s->avail_in_expect = strm->avail_in;
- s->mode = BZ_M_FLUSHING;
- goto preswitch;
- }
- else
- if (action == BZ_FINISH) {
- s->avail_in_expect = strm->avail_in;
- s->mode = BZ_M_FINISHING;
- goto preswitch;
- }
- else
- return BZ_PARAM_ERROR;
-
- case BZ_M_FLUSHING:
- if (action != BZ_FLUSH) return BZ_SEQUENCE_ERROR;
- if (s->avail_in_expect != s->strm->avail_in)
- return BZ_SEQUENCE_ERROR;
- progress = handle_compress ( strm );
- if (s->avail_in_expect > 0 || !isempty_RL(s) ||
- s->state_out_pos < s->numZ) return BZ_FLUSH_OK;
- s->mode = BZ_M_RUNNING;
- return BZ_RUN_OK;
-
- case BZ_M_FINISHING:
- if (action != BZ_FINISH) return BZ_SEQUENCE_ERROR;
- if (s->avail_in_expect != s->strm->avail_in)
- return BZ_SEQUENCE_ERROR;
- progress = handle_compress ( strm );
- if (!progress) return BZ_SEQUENCE_ERROR;
- if (s->avail_in_expect > 0 || !isempty_RL(s) ||
- s->state_out_pos < s->numZ) return BZ_FINISH_OK;
- s->mode = BZ_M_IDLE;
- return BZ_STREAM_END;
- }
- return BZ_OK; /*--not reached--*/
-}
-
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzCompressEnd) ( bz_stream *strm )
-{
- EState* s;
- if (strm == NULL) return BZ_PARAM_ERROR;
- s = strm->state;
- if (s == NULL) return BZ_PARAM_ERROR;
- if (s->strm != strm) return BZ_PARAM_ERROR;
-
- if (s->arr1 != NULL) BZFREE(s->arr1);
- if (s->arr2 != NULL) BZFREE(s->arr2);
- if (s->ftab != NULL) BZFREE(s->ftab);
- BZFREE(strm->state);
-
- strm->state = NULL;
-
- return BZ_OK;
-}
-#endif /* BZ_NO_COMPRESS */
-
-/*---------------------------------------------------*/
-/*--- Decompression stuff ---*/
-/*---------------------------------------------------*/
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzDecompressInit)
- ( bz_stream* strm,
- int verbosity,
- int small )
-{
- DState* s;
-
- if (!bz_config_ok()) return BZ_CONFIG_ERROR;
-
- if (strm == NULL) return BZ_PARAM_ERROR;
- if (small != 0 && small != 1) return BZ_PARAM_ERROR;
- if (verbosity < 0 || verbosity > 4) return BZ_PARAM_ERROR;
-
- if (strm->bzalloc == NULL) strm->bzalloc = default_bzalloc;
- if (strm->bzfree == NULL) strm->bzfree = default_bzfree;
-
- s = BZALLOC( sizeof(DState) );
- if (s == NULL) return BZ_MEM_ERROR;
- s->strm = strm;
- strm->state = s;
- s->state = BZ_X_MAGIC_1;
- s->bsLive = 0;
- s->bsBuff = 0;
- s->calculatedCombinedCRC = 0;
- strm->total_in_lo32 = 0;
- strm->total_in_hi32 = 0;
- strm->total_out_lo32 = 0;
- strm->total_out_hi32 = 0;
- s->smallDecompress = (Bool)small;
- s->ll4 = NULL;
- s->ll16 = NULL;
- s->tt = NULL;
- s->currBlockNo = 0;
- s->verbosity = verbosity;
-
- return BZ_OK;
-}
-
-
-/*---------------------------------------------------*/
-static
-void unRLE_obuf_to_output_FAST ( DState* s )
-{
- UChar k1;
-
- if (s->blockRandomised) {
-
- while (True) {
- /* try to finish existing run */
- while (True) {
- if (s->strm->avail_out == 0) return;
- if (s->state_out_len == 0) break;
- *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
- BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
- s->state_out_len--;
- s->strm->next_out++;
- s->strm->avail_out--;
- s->strm->total_out_lo32++;
- if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
- }
-
- /* can a new run be started? */
- if (s->nblock_used == s->save_nblock+1) return;
-
-
- s->state_out_len = 1;
- s->state_out_ch = s->k0;
- BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 2;
- BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 3;
- BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- s->state_out_len = ((Int32)k1) + 4;
- BZ_GET_FAST(s->k0); BZ_RAND_UPD_MASK;
- s->k0 ^= BZ_RAND_MASK; s->nblock_used++;
- }
-
- } else {
-
- /* restore */
- UInt32 c_calculatedBlockCRC = s->calculatedBlockCRC;
- UChar c_state_out_ch = s->state_out_ch;
- Int32 c_state_out_len = s->state_out_len;
- Int32 c_nblock_used = s->nblock_used;
- Int32 c_k0 = s->k0;
- UInt32* c_tt = s->tt;
- UInt32 c_tPos = s->tPos;
- char* cs_next_out = s->strm->next_out;
- unsigned int cs_avail_out = s->strm->avail_out;
- /* end restore */
-
- UInt32 avail_out_INIT = cs_avail_out;
- Int32 s_save_nblockPP = s->save_nblock+1;
- unsigned int total_out_lo32_old;
-
- while (True) {
-
- /* try to finish existing run */
- if (c_state_out_len > 0) {
- while (True) {
- if (cs_avail_out == 0) goto return_notr;
- if (c_state_out_len == 1) break;
- *( (UChar*)(cs_next_out) ) = c_state_out_ch;
- BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch );
- c_state_out_len--;
- cs_next_out++;
- cs_avail_out--;
- }
- s_state_out_len_eq_one:
- {
- if (cs_avail_out == 0) {
- c_state_out_len = 1; goto return_notr;
- };
- *( (UChar*)(cs_next_out) ) = c_state_out_ch;
- BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch );
- cs_next_out++;
- cs_avail_out--;
- }
- }
- /* can a new run be started? */
- if (c_nblock_used == s_save_nblockPP) {
- c_state_out_len = 0; goto return_notr;
- };
- c_state_out_ch = c_k0;
- BZ_GET_FAST_C(k1); c_nblock_used++;
- if (k1 != c_k0) {
- c_k0 = k1; goto s_state_out_len_eq_one;
- };
- if (c_nblock_used == s_save_nblockPP)
- goto s_state_out_len_eq_one;
-
- c_state_out_len = 2;
- BZ_GET_FAST_C(k1); c_nblock_used++;
- if (c_nblock_used == s_save_nblockPP) continue;
- if (k1 != c_k0) { c_k0 = k1; continue; };
-
- c_state_out_len = 3;
- BZ_GET_FAST_C(k1); c_nblock_used++;
- if (c_nblock_used == s_save_nblockPP) continue;
- if (k1 != c_k0) { c_k0 = k1; continue; };
-
- BZ_GET_FAST_C(k1); c_nblock_used++;
- c_state_out_len = ((Int32)k1) + 4;
- BZ_GET_FAST_C(c_k0); c_nblock_used++;
- }
-
- return_notr:
- total_out_lo32_old = s->strm->total_out_lo32;
- s->strm->total_out_lo32 += (avail_out_INIT - cs_avail_out);
- if (s->strm->total_out_lo32 < total_out_lo32_old)
- s->strm->total_out_hi32++;
-
- /* save */
- s->calculatedBlockCRC = c_calculatedBlockCRC;
- s->state_out_ch = c_state_out_ch;
- s->state_out_len = c_state_out_len;
- s->nblock_used = c_nblock_used;
- s->k0 = c_k0;
- s->tt = c_tt;
- s->tPos = c_tPos;
- s->strm->next_out = cs_next_out;
- s->strm->avail_out = cs_avail_out;
- /* end save */
- }
-}
-
-
-/*---------------------------------------------------*/
-__inline__ Int32 BZ2_indexIntoF ( Int32 indx, Int32 *cftab )
-{
- Int32 nb, na, mid;
- nb = 0;
- na = 256;
- do {
- mid = (nb + na) >> 1;
- if (indx >= cftab[mid]) nb = mid; else na = mid;
- }
- while (na - nb != 1);
- return nb;
-}
-
-
-/*---------------------------------------------------*/
-static
-void unRLE_obuf_to_output_SMALL ( DState* s )
-{
- UChar k1;
-
- if (s->blockRandomised) {
-
- while (True) {
- /* try to finish existing run */
- while (True) {
- if (s->strm->avail_out == 0) return;
- if (s->state_out_len == 0) break;
- *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
- BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
- s->state_out_len--;
- s->strm->next_out++;
- s->strm->avail_out--;
- s->strm->total_out_lo32++;
- if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
- }
-
- /* can a new run be started? */
- if (s->nblock_used == s->save_nblock+1) return;
-
-
- s->state_out_len = 1;
- s->state_out_ch = s->k0;
- BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 2;
- BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 3;
- BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- s->state_out_len = ((Int32)k1) + 4;
- BZ_GET_SMALL(s->k0); BZ_RAND_UPD_MASK;
- s->k0 ^= BZ_RAND_MASK; s->nblock_used++;
- }
-
- } else {
-
- while (True) {
- /* try to finish existing run */
- while (True) {
- if (s->strm->avail_out == 0) return;
- if (s->state_out_len == 0) break;
- *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
- BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
- s->state_out_len--;
- s->strm->next_out++;
- s->strm->avail_out--;
- s->strm->total_out_lo32++;
- if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
- }
-
- /* can a new run be started? */
- if (s->nblock_used == s->save_nblock+1) return;
-
- s->state_out_len = 1;
- s->state_out_ch = s->k0;
- BZ_GET_SMALL(k1); s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 2;
- BZ_GET_SMALL(k1); s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 3;
- BZ_GET_SMALL(k1); s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- BZ_GET_SMALL(k1); s->nblock_used++;
- s->state_out_len = ((Int32)k1) + 4;
- BZ_GET_SMALL(s->k0); s->nblock_used++;
- }
-
- }
-}
-
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzDecompress) ( bz_stream *strm )
-{
- DState* s;
- if (strm == NULL) return BZ_PARAM_ERROR;
- s = strm->state;
- if (s == NULL) return BZ_PARAM_ERROR;
- if (s->strm != strm) return BZ_PARAM_ERROR;
-
- while (True) {
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
-#endif
- if (s->state == BZ_X_IDLE) return BZ_SEQUENCE_ERROR;
- if (s->state == BZ_X_OUTPUT) {
- if (s->smallDecompress)
- unRLE_obuf_to_output_SMALL ( s ); else
- unRLE_obuf_to_output_FAST ( s );
- if (s->nblock_used == s->save_nblock+1 && s->state_out_len == 0) {
- BZ_FINALISE_CRC ( s->calculatedBlockCRC );
- if (s->verbosity >= 3)
- VPrintf2 ( " {0x%x, 0x%x}", s->storedBlockCRC,
- s->calculatedBlockCRC );
- if (s->verbosity >= 2) VPrintf0 ( "]" );
- if (s->calculatedBlockCRC != s->storedBlockCRC)
- return BZ_DATA_ERROR;
- s->calculatedCombinedCRC
- = (s->calculatedCombinedCRC << 1) |
- (s->calculatedCombinedCRC >> 31);
- s->calculatedCombinedCRC ^= s->calculatedBlockCRC;
- s->state = BZ_X_BLKHDR_1;
- } else {
- return BZ_OK;
- }
- }
- if (s->state >= BZ_X_MAGIC_1) {
- Int32 r = BZ2_decompress ( s );
- if (r == BZ_STREAM_END) {
- if (s->verbosity >= 3)
- VPrintf2 ( "\n combined CRCs: stored = 0x%x, computed = 0x%x",
- s->storedCombinedCRC, s->calculatedCombinedCRC );
- if (s->calculatedCombinedCRC != s->storedCombinedCRC)
- return BZ_DATA_ERROR;
- return r;
- }
- if (s->state != BZ_X_OUTPUT) return r;
- }
- }
-
- AssertH ( 0, 6001 );
-
- return 0; /*NOTREACHED*/
-}
-
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzDecompressEnd) ( bz_stream *strm )
-{
- DState* s;
- if (strm == NULL) return BZ_PARAM_ERROR;
- s = strm->state;
- if (s == NULL) return BZ_PARAM_ERROR;
- if (s->strm != strm) return BZ_PARAM_ERROR;
-
- if (s->tt != NULL) BZFREE(s->tt);
- if (s->ll16 != NULL) BZFREE(s->ll16);
- if (s->ll4 != NULL) BZFREE(s->ll4);
-
- BZFREE(strm->state);
- strm->state = NULL;
-
- return BZ_OK;
-}
-
-
-#ifndef BZ_NO_STDIO
-/*---------------------------------------------------*/
-/*--- File I/O stuff ---*/
-/*---------------------------------------------------*/
-
-#define BZ_SETERR(eee) \
-{ \
- if (bzerror != NULL) *bzerror = eee; \
- if (bzf != NULL) bzf->lastErr = eee; \
-}
-
-typedef
- struct {
- FILE* handle;
- Char buf[BZ_MAX_UNUSED];
- Int32 bufN;
- Bool writing;
- bz_stream strm;
- Int32 lastErr;
- Bool initialisedOk;
- }
- bzFile;
-
-
-/*---------------------------------------------*/
-static Bool myfeof ( FILE* f )
-{
- Int32 c = fgetc ( f );
- if (c == EOF) return True;
- ungetc ( c, f );
- return False;
-}
-
-
-/*---------------------------------------------------*/
-BZFILE* BZ_API(BZ2_bzWriteOpen)
- ( int* bzerror,
- FILE* f,
- int blockSize100k,
- int verbosity,
- int workFactor )
-{
- Int32 ret;
- bzFile* bzf = NULL;
-
- BZ_SETERR(BZ_OK);
-
- if (f == NULL ||
- (blockSize100k < 1 || blockSize100k > 9) ||
- (workFactor < 0 || workFactor > 250) ||
- (verbosity < 0 || verbosity > 4))
- { BZ_SETERR(BZ_PARAM_ERROR); return NULL; };
-
- if (ferror(f))
- { BZ_SETERR(BZ_IO_ERROR); return NULL; };
-
- bzf = malloc ( sizeof(bzFile) );
- if (bzf == NULL)
- { BZ_SETERR(BZ_MEM_ERROR); return NULL; };
-
- BZ_SETERR(BZ_OK);
- bzf->initialisedOk = False;
- bzf->bufN = 0;
- bzf->handle = f;
- bzf->writing = True;
- bzf->strm.bzalloc = NULL;
- bzf->strm.bzfree = NULL;
- bzf->strm.opaque = NULL;
-
- if (workFactor == 0) workFactor = 30;
- ret = BZ2_bzCompressInit ( &(bzf->strm), blockSize100k,
- verbosity, workFactor );
- if (ret != BZ_OK)
- { BZ_SETERR(ret); free(bzf); return NULL; };
-
- bzf->strm.avail_in = 0;
- bzf->initialisedOk = True;
- return bzf;
-}
-
-
-/*---------------------------------------------------*/
-void BZ_API(BZ2_bzWrite)
- ( int* bzerror,
- BZFILE* b,
- void* buf,
- int len )
-{
- Int32 n, n2, ret;
- bzFile* bzf = (bzFile*)b;
-
- BZ_SETERR(BZ_OK);
- if (bzf == NULL || buf == NULL || len < 0)
- { BZ_SETERR(BZ_PARAM_ERROR); return; };
- if (!(bzf->writing))
- { BZ_SETERR(BZ_SEQUENCE_ERROR); return; };
- if (ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return; };
-
- if (len == 0)
- { BZ_SETERR(BZ_OK); return; };
-
- bzf->strm.avail_in = len;
- bzf->strm.next_in = buf;
-
- while (True) {
- bzf->strm.avail_out = BZ_MAX_UNUSED;
- bzf->strm.next_out = bzf->buf;
- ret = BZ2_bzCompress ( &(bzf->strm), BZ_RUN );
- if (ret != BZ_RUN_OK)
- { BZ_SETERR(ret); return; };
-
- if (bzf->strm.avail_out < BZ_MAX_UNUSED) {
- n = BZ_MAX_UNUSED - bzf->strm.avail_out;
- n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar),
- n, bzf->handle );
- if (n != n2 || ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return; };
- }
-
- if (bzf->strm.avail_in == 0)
- { BZ_SETERR(BZ_OK); return; };
- }
-}
-
-
-/*---------------------------------------------------*/
-void BZ_API(BZ2_bzWriteClose)
- ( int* bzerror,
- BZFILE* b,
- int abandon,
- unsigned int* nbytes_in,
- unsigned int* nbytes_out )
-{
- BZ2_bzWriteClose64 ( bzerror, b, abandon,
- nbytes_in, NULL, nbytes_out, NULL );
-}
-
-
-void BZ_API(BZ2_bzWriteClose64)
- ( int* bzerror,
- BZFILE* b,
- int abandon,
- unsigned int* nbytes_in_lo32,
- unsigned int* nbytes_in_hi32,
- unsigned int* nbytes_out_lo32,
- unsigned int* nbytes_out_hi32 )
-{
- Int32 n, n2, ret;
- bzFile* bzf = (bzFile*)b;
-
- if (bzf == NULL)
- { BZ_SETERR(BZ_OK); return; };
- if (!(bzf->writing))
- { BZ_SETERR(BZ_SEQUENCE_ERROR); return; };
- if (ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return; };
-
- if (nbytes_in_lo32 != NULL) *nbytes_in_lo32 = 0;
- if (nbytes_in_hi32 != NULL) *nbytes_in_hi32 = 0;
- if (nbytes_out_lo32 != NULL) *nbytes_out_lo32 = 0;
- if (nbytes_out_hi32 != NULL) *nbytes_out_hi32 = 0;
-
- if ((!abandon) && bzf->lastErr == BZ_OK) {
- while (True) {
- bzf->strm.avail_out = BZ_MAX_UNUSED;
- bzf->strm.next_out = bzf->buf;
- ret = BZ2_bzCompress ( &(bzf->strm), BZ_FINISH );
- if (ret != BZ_FINISH_OK && ret != BZ_STREAM_END)
- { BZ_SETERR(ret); return; };
-
- if (bzf->strm.avail_out < BZ_MAX_UNUSED) {
- n = BZ_MAX_UNUSED - bzf->strm.avail_out;
- n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar),
- n, bzf->handle );
- if (n != n2 || ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return; };
- }
-
- if (ret == BZ_STREAM_END) break;
- }
- }
-
- if ( !abandon && !ferror ( bzf->handle ) ) {
- fflush ( bzf->handle );
- if (ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return; };
- }
-
- if (nbytes_in_lo32 != NULL)
- *nbytes_in_lo32 = bzf->strm.total_in_lo32;
- if (nbytes_in_hi32 != NULL)
- *nbytes_in_hi32 = bzf->strm.total_in_hi32;
- if (nbytes_out_lo32 != NULL)
- *nbytes_out_lo32 = bzf->strm.total_out_lo32;
- if (nbytes_out_hi32 != NULL)
- *nbytes_out_hi32 = bzf->strm.total_out_hi32;
-
- BZ_SETERR(BZ_OK);
- BZ2_bzCompressEnd ( &(bzf->strm) );
- free ( bzf );
-}
-
-
-/*---------------------------------------------------*/
-BZFILE* BZ_API(BZ2_bzReadOpen)
- ( int* bzerror,
- FILE* f,
- int verbosity,
- int small,
- void* unused,
- int nUnused )
-{
- bzFile* bzf = NULL;
- int ret;
-
- BZ_SETERR(BZ_OK);
-
- if (f == NULL ||
- (small != 0 && small != 1) ||
- (verbosity < 0 || verbosity > 4) ||
- (unused == NULL && nUnused != 0) ||
- (unused != NULL && (nUnused < 0 || nUnused > BZ_MAX_UNUSED)))
- { BZ_SETERR(BZ_PARAM_ERROR); return NULL; };
-
- if (ferror(f))
- { BZ_SETERR(BZ_IO_ERROR); return NULL; };
-
- bzf = malloc ( sizeof(bzFile) );
- if (bzf == NULL)
- { BZ_SETERR(BZ_MEM_ERROR); return NULL; };
-
- BZ_SETERR(BZ_OK);
-
- bzf->initialisedOk = False;
- bzf->handle = f;
- bzf->bufN = 0;
- bzf->writing = False;
- bzf->strm.bzalloc = NULL;
- bzf->strm.bzfree = NULL;
- bzf->strm.opaque = NULL;
-
- while (nUnused > 0) {
- bzf->buf[bzf->bufN] = *((UChar*)(unused)); bzf->bufN++;
- unused = ((void*)( 1 + ((UChar*)(unused)) ));
- nUnused--;
- }
-
- ret = BZ2_bzDecompressInit ( &(bzf->strm), verbosity, small );
- if (ret != BZ_OK)
- { BZ_SETERR(ret); free(bzf); return NULL; };
-
- bzf->strm.avail_in = bzf->bufN;
- bzf->strm.next_in = bzf->buf;
-
- bzf->initialisedOk = True;
- return bzf;
-}
-
-
-/*---------------------------------------------------*/
-void BZ_API(BZ2_bzReadClose) ( int *bzerror, BZFILE *b )
-{
- bzFile* bzf = (bzFile*)b;
-
- BZ_SETERR(BZ_OK);
- if (bzf == NULL)
- { BZ_SETERR(BZ_OK); return; };
-
- if (bzf->writing)
- { BZ_SETERR(BZ_SEQUENCE_ERROR); return; };
-
- if (bzf->initialisedOk)
- (void)BZ2_bzDecompressEnd ( &(bzf->strm) );
- free ( bzf );
-}
-
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzRead)
- ( int* bzerror,
- BZFILE* b,
- void* buf,
- int len )
-{
- Int32 n, ret;
- bzFile* bzf = (bzFile*)b;
-
- BZ_SETERR(BZ_OK);
-
- if (bzf == NULL || buf == NULL || len < 0)
- { BZ_SETERR(BZ_PARAM_ERROR); return 0; };
-
- if (bzf->writing)
- { BZ_SETERR(BZ_SEQUENCE_ERROR); return 0; };
-
- if (len == 0)
- { BZ_SETERR(BZ_OK); return 0; };
-
- bzf->strm.avail_out = len;
- bzf->strm.next_out = buf;
-
- while (True) {
-
- if (ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return 0; };
-
- if (bzf->strm.avail_in == 0 && !myfeof(bzf->handle)) {
- n = fread ( bzf->buf, sizeof(UChar),
- BZ_MAX_UNUSED, bzf->handle );
- if (ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return 0; };
- bzf->bufN = n;
- bzf->strm.avail_in = bzf->bufN;
- bzf->strm.next_in = bzf->buf;
- }
-
- ret = BZ2_bzDecompress ( &(bzf->strm) );
-
- if (ret != BZ_OK && ret != BZ_STREAM_END)
- { BZ_SETERR(ret); return 0; };
-
- if (ret == BZ_OK && myfeof(bzf->handle) &&
- bzf->strm.avail_in == 0 && bzf->strm.avail_out > 0)
- { BZ_SETERR(BZ_UNEXPECTED_EOF); return 0; };
-
- if (ret == BZ_STREAM_END)
- { BZ_SETERR(BZ_STREAM_END);
- return len - bzf->strm.avail_out; };
- if (bzf->strm.avail_out == 0)
- { BZ_SETERR(BZ_OK); return len; };
-
- }
-
- return 0; /*not reached*/
-}
-
-
-/*---------------------------------------------------*/
-void BZ_API(BZ2_bzReadGetUnused)
- ( int* bzerror,
- BZFILE* b,
- void** unused,
- int* nUnused )
-{
- bzFile* bzf = (bzFile*)b;
- if (bzf == NULL)
- { BZ_SETERR(BZ_PARAM_ERROR); return; };
- if (bzf->lastErr != BZ_STREAM_END)
- { BZ_SETERR(BZ_SEQUENCE_ERROR); return; };
- if (unused == NULL || nUnused == NULL)
- { BZ_SETERR(BZ_PARAM_ERROR); return; };
-
- BZ_SETERR(BZ_OK);
- *nUnused = bzf->strm.avail_in;
- *unused = bzf->strm.next_in;
-}
-#endif
-
-
-/*---------------------------------------------------*/
-/*--- Misc convenience stuff ---*/
-/*---------------------------------------------------*/
-#ifndef BZ_NO_COMPRESS
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzBuffToBuffCompress)
- ( char* dest,
- unsigned int* destLen,
- char* source,
- unsigned int sourceLen,
- int blockSize100k,
- int verbosity,
- int workFactor )
-{
- bz_stream strm;
- int ret;
-
- if (dest == NULL || destLen == NULL ||
- source == NULL ||
- blockSize100k < 1 || blockSize100k > 9 ||
- verbosity < 0 || verbosity > 4 ||
- workFactor < 0 || workFactor > 250)
- return BZ_PARAM_ERROR;
-
- if (workFactor == 0) workFactor = 30;
- strm.bzalloc = NULL;
- strm.bzfree = NULL;
- strm.opaque = NULL;
- ret = BZ2_bzCompressInit ( &strm, blockSize100k,
- verbosity, workFactor );
- if (ret != BZ_OK) return ret;
-
- strm.next_in = source;
- strm.next_out = dest;
- strm.avail_in = sourceLen;
- strm.avail_out = *destLen;
-
- ret = BZ2_bzCompress ( &strm, BZ_FINISH );
- if (ret == BZ_FINISH_OK) goto output_overflow;
- if (ret != BZ_STREAM_END) goto errhandler;
-
- /* normal termination */
- *destLen -= strm.avail_out;
- BZ2_bzCompressEnd ( &strm );
- return BZ_OK;
-
- output_overflow:
- BZ2_bzCompressEnd ( &strm );
- return BZ_OUTBUFF_FULL;
-
- errhandler:
- BZ2_bzCompressEnd ( &strm );
- return ret;
-}
-#endif /* BZ_NO_COMPRESS */
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzBuffToBuffDecompress)
- ( char* dest,
- unsigned int* destLen,
- char* source,
- unsigned int sourceLen,
- int small,
- int verbosity )
-{
- bz_stream strm;
- int ret;
-
- if (destLen == NULL || source == NULL)
- return BZ_PARAM_ERROR;
-
- strm.bzalloc = NULL;
- strm.bzfree = NULL;
- strm.opaque = NULL;
- ret = BZ2_bzDecompressInit ( &strm, verbosity, small );
- if (ret != BZ_OK) return ret;
-
- strm.next_in = source;
- strm.next_out = dest;
- strm.avail_in = sourceLen;
- strm.avail_out = *destLen;
-
- ret = BZ2_bzDecompress ( &strm );
- if (ret == BZ_OK) goto output_overflow_or_eof;
- if (ret != BZ_STREAM_END) goto errhandler;
-
- /* normal termination */
- *destLen -= strm.avail_out;
- BZ2_bzDecompressEnd ( &strm );
- return BZ_OK;
-
- output_overflow_or_eof:
- if (strm.avail_out > 0) {
- BZ2_bzDecompressEnd ( &strm );
- return BZ_UNEXPECTED_EOF;
- } else {
- BZ2_bzDecompressEnd ( &strm );
- return BZ_OUTBUFF_FULL;
- };
-
- errhandler:
- BZ2_bzDecompressEnd ( &strm );
- return ret;
-}
-
-
-/*---------------------------------------------------*/
-/*--
- Code contributed by Yoshioka Tsuneo
- (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
- to support better zlib compatibility.
- This code is not _officially_ part of libbzip2 (yet);
- I haven't tested it, documented it, or considered the
- threading-safeness of it.
- If this code breaks, please contact both Yoshioka and me.
---*/
-/*---------------------------------------------------*/
-
-/*---------------------------------------------------*/
-/*--
- return version like "0.9.0c".
---*/
-const char * BZ_API(BZ2_bzlibVersion)(void)
-{
- return BZ_VERSION;
-}
-
-
-#ifndef BZ_NO_STDIO
-/*---------------------------------------------------*/
-
-#if defined(_WIN32) || defined(OS2) || defined(MSDOS)
-# include <fcntl.h>
-# include <io.h>
-# define SET_BINARY_MODE(file) setmode(fileno(file),O_BINARY)
-#else
-# define SET_BINARY_MODE(file)
-#endif
-static
-BZFILE * bzopen_or_bzdopen
- ( const char *path, /* no use when bzdopen */
- int fd, /* no use when bzdopen */
- const char *mode,
- int open_mode) /* bzopen: 0, bzdopen:1 */
-{
- int bzerr;
- char unused[BZ_MAX_UNUSED];
- int blockSize100k = 9;
- int writing = 0;
- char mode2[10] = "";
- FILE *fp = NULL;
- BZFILE *bzfp = NULL;
- int verbosity = 0;
- int workFactor = 30;
- int smallMode = 0;
- int nUnused = 0;
-
- if (mode == NULL) return NULL;
- while (*mode) {
- switch (*mode) {
- case 'r':
- writing = 0; break;
- case 'w':
- writing = 1; break;
- case 's':
- smallMode = 1; break;
- default:
- if (isdigit((int)(*mode))) {
- blockSize100k = *mode-BZ_HDR_0;
- }
- }
- mode++;
- }
- strcat(mode2, writing ? "w" : "r" );
- strcat(mode2,"b"); /* binary mode */
-
- if (open_mode==0) {
- if (path==NULL || strcmp(path,"")==0) {
- fp = (writing ? stdout : stdin);
- SET_BINARY_MODE(fp);
- } else {
- fp = fopen(path,mode2);
- }
- } else {
-#ifdef BZ_STRICT_ANSI
- fp = NULL;
-#else
- fp = fdopen(fd,mode2);
-#endif
- }
- if (fp == NULL) return NULL;
-
- if (writing) {
- /* Guard against total chaos and anarchy -- JRS */
- if (blockSize100k < 1) blockSize100k = 1;
- if (blockSize100k > 9) blockSize100k = 9;
- bzfp = BZ2_bzWriteOpen(&bzerr,fp,blockSize100k,
- verbosity,workFactor);
- } else {
- bzfp = BZ2_bzReadOpen(&bzerr,fp,verbosity,smallMode,
- unused,nUnused);
- }
- if (bzfp == NULL) {
- if (fp != stdin && fp != stdout) fclose(fp);
- return NULL;
- }
- return bzfp;
-}
-
-
-/*---------------------------------------------------*/
-/*--
- open file for read or write.
- ex) bzopen("file","w9")
- case path="" or NULL => use stdin or stdout.
---*/
-BZFILE * BZ_API(BZ2_bzopen)
- ( const char *path,
- const char *mode )
-{
- return bzopen_or_bzdopen(path,-1,mode,/*bzopen*/0);
-}
-
-
-/*---------------------------------------------------*/
-BZFILE * BZ_API(BZ2_bzdopen)
- ( int fd,
- const char *mode )
-{
- return bzopen_or_bzdopen(NULL,fd,mode,/*bzdopen*/1);
-}
-
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzread) (BZFILE* b, void* buf, int len )
-{
- int bzerr, nread;
- if (((bzFile*)b)->lastErr == BZ_STREAM_END) return 0;
- nread = BZ2_bzRead(&bzerr,b,buf,len);
- if (bzerr == BZ_OK || bzerr == BZ_STREAM_END) {
- return nread;
- } else {
- return -1;
- }
-}
-
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzwrite) (BZFILE* b, void* buf, int len )
-{
- int bzerr;
-
- BZ2_bzWrite(&bzerr,b,buf,len);
- if(bzerr == BZ_OK){
- return len;
- }else{
- return -1;
- }
-}
-
-
-/*---------------------------------------------------*/
-int BZ_API(BZ2_bzflush) (BZFILE *b)
-{
- /* do nothing now... */
- return 0;
-}
-
-
-/*---------------------------------------------------*/
-void BZ_API(BZ2_bzclose) (BZFILE* b)
-{
- int bzerr;
- FILE *fp = ((bzFile *)b)->handle;
-
- if (b==NULL) {return;}
- if(((bzFile*)b)->writing){
- BZ2_bzWriteClose(&bzerr,b,0,NULL,NULL);
- if(bzerr != BZ_OK){
- BZ2_bzWriteClose(NULL,b,1,NULL,NULL);
- }
- }else{
- BZ2_bzReadClose(&bzerr,b);
- }
- if(fp!=stdin && fp!=stdout){
- fclose(fp);
- }
-}
-
-
-/*---------------------------------------------------*/
-/*--
- return last error code
---*/
-static char *bzerrorstrings[] = {
- "OK"
- ,"SEQUENCE_ERROR"
- ,"PARAM_ERROR"
- ,"MEM_ERROR"
- ,"DATA_ERROR"
- ,"DATA_ERROR_MAGIC"
- ,"IO_ERROR"
- ,"UNEXPECTED_EOF"
- ,"OUTBUFF_FULL"
- ,"CONFIG_ERROR"
- ,"???" /* for future */
- ,"???" /* for future */
- ,"???" /* for future */
- ,"???" /* for future */
- ,"???" /* for future */
- ,"???" /* for future */
-};
-
-
-const char * BZ_API(BZ2_bzerror) (BZFILE *b, int *errnum)
-{
- int err = ((bzFile *)b)->lastErr;
-
- if(err>0) err = 0;
- *errnum = err;
- return bzerrorstrings[err*-1];
-}
-#endif
-
-void bz_internal_error(int errcode)
-{
- printf ("BZIP2 internal error %d\n", errcode);
-}
-
-/*-------------------------------------------------------------*/
-/*--- end bzlib.c ---*/
-/*-------------------------------------------------------------*/
+++ /dev/null
-#include <config.h>
-
-/*-------------------------------------------------------------*/
-/*--- Table for doing CRCs ---*/
-/*--- crctable.c ---*/
-/*-------------------------------------------------------------*/
-
-/*--
- This file is a part of bzip2 and/or libbzip2, a program and
- library for lossless, block-sorting data compression.
-
- Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. The origin of this software must not be misrepresented; you must
- not claim that you wrote the original software. If you use this
- software in a product, an acknowledgment in the product
- documentation would be appreciated but is not required.
-
- 3. Altered source versions must be plainly marked as such, and must
- not be misrepresented as being the original software.
-
- 4. The name of the author may not be used to endorse or promote
- products derived from this software without specific prior written
- permission.
-
- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- Julian Seward, Cambridge, UK.
- jseward@acm.org
- bzip2/libbzip2 version 1.0 of 21 March 2000
-
- This program is based on (at least) the work of:
- Mike Burrows
- David Wheeler
- Peter Fenwick
- Alistair Moffat
- Radford Neal
- Ian H. Witten
- Robert Sedgewick
- Jon L. Bentley
-
- For more information on these sources, see the manual.
---*/
-
-
-#include "bzlib_private.h"
-
-/*--
- I think this is an implementation of the AUTODIN-II,
- Ethernet & FDDI 32-bit CRC standard. Vaguely derived
- from code by Rob Warnock, in Section 51 of the
- comp.compression FAQ.
---*/
-
-UInt32 BZ2_crc32Table[256] = {
-
- /*-- Ugly, innit? --*/
-
- 0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L,
- 0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L,
- 0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L,
- 0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL,
- 0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L,
- 0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L,
- 0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L,
- 0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL,
- 0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L,
- 0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L,
- 0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L,
- 0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL,
- 0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L,
- 0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L,
- 0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L,
- 0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL,
- 0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL,
- 0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L,
- 0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L,
- 0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL,
- 0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL,
- 0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L,
- 0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L,
- 0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL,
- 0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL,
- 0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L,
- 0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L,
- 0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL,
- 0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL,
- 0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L,
- 0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L,
- 0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL,
- 0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L,
- 0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL,
- 0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL,
- 0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L,
- 0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L,
- 0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL,
- 0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL,
- 0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L,
- 0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L,
- 0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL,
- 0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL,
- 0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L,
- 0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L,
- 0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL,
- 0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL,
- 0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L,
- 0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L,
- 0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL,
- 0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L,
- 0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L,
- 0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L,
- 0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL,
- 0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L,
- 0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L,
- 0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L,
- 0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL,
- 0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L,
- 0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L,
- 0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L,
- 0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL,
- 0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L,
- 0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L
-};
-
-
-/*-------------------------------------------------------------*/
-/*--- end crctable.c ---*/
-/*-------------------------------------------------------------*/
+++ /dev/null
-#include <config.h>
-#include <common.h>
-#include <watchdog.h>
-
-/*-------------------------------------------------------------*/
-/*--- Decompression machinery ---*/
-/*--- decompress.c ---*/
-/*-------------------------------------------------------------*/
-
-/*--
- This file is a part of bzip2 and/or libbzip2, a program and
- library for lossless, block-sorting data compression.
-
- Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. The origin of this software must not be misrepresented; you must
- not claim that you wrote the original software. If you use this
- software in a product, an acknowledgment in the product
- documentation would be appreciated but is not required.
-
- 3. Altered source versions must be plainly marked as such, and must
- not be misrepresented as being the original software.
-
- 4. The name of the author may not be used to endorse or promote
- products derived from this software without specific prior written
- permission.
-
- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- Julian Seward, Cambridge, UK.
- jseward@acm.org
- bzip2/libbzip2 version 1.0 of 21 March 2000
-
- This program is based on (at least) the work of:
- Mike Burrows
- David Wheeler
- Peter Fenwick
- Alistair Moffat
- Radford Neal
- Ian H. Witten
- Robert Sedgewick
- Jon L. Bentley
-
- For more information on these sources, see the manual.
---*/
-
-
-#include "bzlib_private.h"
-
-
-/*---------------------------------------------------*/
-static
-void makeMaps_d ( DState* s )
-{
- Int32 i;
- s->nInUse = 0;
- for (i = 0; i < 256; i++)
- if (s->inUse[i]) {
- s->seqToUnseq[s->nInUse] = i;
- s->nInUse++;
- }
-}
-
-
-/*---------------------------------------------------*/
-#define RETURN(rrr) \
- { retVal = rrr; goto save_state_and_return; };
-
-#define GET_BITS(lll,vvv,nnn) \
- case lll: s->state = lll; \
- while (True) { \
- if (s->bsLive >= nnn) { \
- UInt32 v; \
- v = (s->bsBuff >> \
- (s->bsLive-nnn)) & ((1 << nnn)-1); \
- s->bsLive -= nnn; \
- vvv = v; \
- break; \
- } \
- if (s->strm->avail_in == 0) RETURN(BZ_OK); \
- s->bsBuff \
- = (s->bsBuff << 8) | \
- ((UInt32) \
- (*((UChar*)(s->strm->next_in)))); \
- s->bsLive += 8; \
- s->strm->next_in++; \
- s->strm->avail_in--; \
- s->strm->total_in_lo32++; \
- if (s->strm->total_in_lo32 == 0) \
- s->strm->total_in_hi32++; \
- }
-
-#define GET_UCHAR(lll,uuu) \
- GET_BITS(lll,uuu,8)
-
-#define GET_BIT(lll,uuu) \
- GET_BITS(lll,uuu,1)
-
-/*---------------------------------------------------*/
-#define GET_MTF_VAL(label1,label2,lval) \
-{ \
- if (groupPos == 0) { \
- groupNo++; \
- if (groupNo >= nSelectors) \
- RETURN(BZ_DATA_ERROR); \
- groupPos = BZ_G_SIZE; \
- gSel = s->selector[groupNo]; \
- gMinlen = s->minLens[gSel]; \
- gLimit = &(s->limit[gSel][0]); \
- gPerm = &(s->perm[gSel][0]); \
- gBase = &(s->base[gSel][0]); \
- } \
- groupPos--; \
- zn = gMinlen; \
- GET_BITS(label1, zvec, zn); \
- while (1) { \
- if (zn > 20 /* the longest code */) \
- RETURN(BZ_DATA_ERROR); \
- if (zvec <= gLimit[zn]) break; \
- zn++; \
- GET_BIT(label2, zj); \
- zvec = (zvec << 1) | zj; \
- }; \
- if (zvec - gBase[zn] < 0 \
- || zvec - gBase[zn] >= BZ_MAX_ALPHA_SIZE) \
- RETURN(BZ_DATA_ERROR); \
- lval = gPerm[zvec - gBase[zn]]; \
-}
-
-
-/*---------------------------------------------------*/
-Int32 BZ2_decompress ( DState* s )
-{
- UChar uc;
- Int32 retVal;
- Int32 minLen, maxLen;
- bz_stream* strm = s->strm;
-
- /* stuff that needs to be saved/restored */
- Int32 i;
- Int32 j;
- Int32 t;
- Int32 alphaSize;
- Int32 nGroups;
- Int32 nSelectors;
- Int32 EOB;
- Int32 groupNo;
- Int32 groupPos;
- Int32 nextSym;
- Int32 nblockMAX;
- Int32 nblock;
- Int32 es;
- Int32 N;
- Int32 curr;
- Int32 zt;
- Int32 zn;
- Int32 zvec;
- Int32 zj;
- Int32 gSel;
- Int32 gMinlen;
- Int32* gLimit;
- Int32* gBase;
- Int32* gPerm;
-
- if (s->state == BZ_X_MAGIC_1) {
- /*initialise the save area*/
- s->save_i = 0;
- s->save_j = 0;
- s->save_t = 0;
- s->save_alphaSize = 0;
- s->save_nGroups = 0;
- s->save_nSelectors = 0;
- s->save_EOB = 0;
- s->save_groupNo = 0;
- s->save_groupPos = 0;
- s->save_nextSym = 0;
- s->save_nblockMAX = 0;
- s->save_nblock = 0;
- s->save_es = 0;
- s->save_N = 0;
- s->save_curr = 0;
- s->save_zt = 0;
- s->save_zn = 0;
- s->save_zvec = 0;
- s->save_zj = 0;
- s->save_gSel = 0;
- s->save_gMinlen = 0;
- s->save_gLimit = NULL;
- s->save_gBase = NULL;
- s->save_gPerm = NULL;
- }
-
- /*restore from the save area*/
- i = s->save_i;
- j = s->save_j;
- t = s->save_t;
- alphaSize = s->save_alphaSize;
- nGroups = s->save_nGroups;
- nSelectors = s->save_nSelectors;
- EOB = s->save_EOB;
- groupNo = s->save_groupNo;
- groupPos = s->save_groupPos;
- nextSym = s->save_nextSym;
- nblockMAX = s->save_nblockMAX;
- nblock = s->save_nblock;
- es = s->save_es;
- N = s->save_N;
- curr = s->save_curr;
- zt = s->save_zt;
- zn = s->save_zn;
- zvec = s->save_zvec;
- zj = s->save_zj;
- gSel = s->save_gSel;
- gMinlen = s->save_gMinlen;
- gLimit = s->save_gLimit;
- gBase = s->save_gBase;
- gPerm = s->save_gPerm;
-
- retVal = BZ_OK;
-
- switch (s->state) {
-
- GET_UCHAR(BZ_X_MAGIC_1, uc);
- if (uc != BZ_HDR_B) RETURN(BZ_DATA_ERROR_MAGIC);
-
- GET_UCHAR(BZ_X_MAGIC_2, uc);
- if (uc != BZ_HDR_Z) RETURN(BZ_DATA_ERROR_MAGIC);
-
- GET_UCHAR(BZ_X_MAGIC_3, uc)
- if (uc != BZ_HDR_h) RETURN(BZ_DATA_ERROR_MAGIC);
-
- GET_BITS(BZ_X_MAGIC_4, s->blockSize100k, 8)
- if (s->blockSize100k < (BZ_HDR_0 + 1) ||
- s->blockSize100k > (BZ_HDR_0 + 9)) RETURN(BZ_DATA_ERROR_MAGIC);
- s->blockSize100k -= BZ_HDR_0;
-
- if (s->smallDecompress) {
- s->ll16 = BZALLOC( s->blockSize100k * 100000 * sizeof(UInt16) );
- s->ll4 = BZALLOC(
- ((1 + s->blockSize100k * 100000) >> 1) * sizeof(UChar)
- );
- if (s->ll16 == NULL || s->ll4 == NULL) RETURN(BZ_MEM_ERROR);
- } else {
- s->tt = BZALLOC( s->blockSize100k * 100000 * sizeof(Int32) );
- if (s->tt == NULL) RETURN(BZ_MEM_ERROR);
- }
-
- GET_UCHAR(BZ_X_BLKHDR_1, uc);
-
- if (uc == 0x17) goto endhdr_2;
- if (uc != 0x31) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_BLKHDR_2, uc);
- if (uc != 0x41) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_BLKHDR_3, uc);
- if (uc != 0x59) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_BLKHDR_4, uc);
- if (uc != 0x26) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_BLKHDR_5, uc);
- if (uc != 0x53) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_BLKHDR_6, uc);
- if (uc != 0x59) RETURN(BZ_DATA_ERROR);
-
- s->currBlockNo++;
- if (s->verbosity >= 2)
- VPrintf1 ( "\n [%d: huff+mtf ", s->currBlockNo );
-
- s->storedBlockCRC = 0;
- GET_UCHAR(BZ_X_BCRC_1, uc);
- s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
- GET_UCHAR(BZ_X_BCRC_2, uc);
- s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
- GET_UCHAR(BZ_X_BCRC_3, uc);
- s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
- GET_UCHAR(BZ_X_BCRC_4, uc);
- s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
-
- GET_BITS(BZ_X_RANDBIT, s->blockRandomised, 1);
-
- s->origPtr = 0;
- GET_UCHAR(BZ_X_ORIGPTR_1, uc);
- s->origPtr = (s->origPtr << 8) | ((Int32)uc);
- GET_UCHAR(BZ_X_ORIGPTR_2, uc);
- s->origPtr = (s->origPtr << 8) | ((Int32)uc);
- GET_UCHAR(BZ_X_ORIGPTR_3, uc);
- s->origPtr = (s->origPtr << 8) | ((Int32)uc);
-
- if (s->origPtr < 0)
- RETURN(BZ_DATA_ERROR);
- if (s->origPtr > 10 + 100000*s->blockSize100k)
- RETURN(BZ_DATA_ERROR);
-
- /*--- Receive the mapping table ---*/
- for (i = 0; i < 16; i++) {
- GET_BIT(BZ_X_MAPPING_1, uc);
- if (uc == 1)
- s->inUse16[i] = True; else
- s->inUse16[i] = False;
- }
-
- for (i = 0; i < 256; i++) s->inUse[i] = False;
-
- for (i = 0; i < 16; i++)
- if (s->inUse16[i])
- for (j = 0; j < 16; j++) {
- GET_BIT(BZ_X_MAPPING_2, uc);
- if (uc == 1) s->inUse[i * 16 + j] = True;
- }
- makeMaps_d ( s );
- if (s->nInUse == 0) RETURN(BZ_DATA_ERROR);
- alphaSize = s->nInUse+2;
-
- /*--- Now the selectors ---*/
- GET_BITS(BZ_X_SELECTOR_1, nGroups, 3);
- if (nGroups < 2 || nGroups > 6) RETURN(BZ_DATA_ERROR);
- GET_BITS(BZ_X_SELECTOR_2, nSelectors, 15);
- if (nSelectors < 1) RETURN(BZ_DATA_ERROR);
- for (i = 0; i < nSelectors; i++) {
- j = 0;
- while (True) {
- GET_BIT(BZ_X_SELECTOR_3, uc);
- if (uc == 0) break;
- j++;
- if (j >= nGroups) RETURN(BZ_DATA_ERROR);
- }
- s->selectorMtf[i] = j;
- }
-
- /*--- Undo the MTF values for the selectors. ---*/
- {
- UChar pos[BZ_N_GROUPS], tmp, v;
- for (v = 0; v < nGroups; v++) pos[v] = v;
-
- for (i = 0; i < nSelectors; i++) {
- v = s->selectorMtf[i];
- tmp = pos[v];
- while (v > 0) { pos[v] = pos[v-1]; v--; }
- pos[0] = tmp;
- s->selector[i] = tmp;
- }
- }
-
- /*--- Now the coding tables ---*/
- for (t = 0; t < nGroups; t++) {
- GET_BITS(BZ_X_CODING_1, curr, 5);
- for (i = 0; i < alphaSize; i++) {
- while (True) {
- if (curr < 1 || curr > 20) RETURN(BZ_DATA_ERROR);
- GET_BIT(BZ_X_CODING_2, uc);
- if (uc == 0) break;
- GET_BIT(BZ_X_CODING_3, uc);
- if (uc == 0) curr++; else curr--;
- }
- s->len[t][i] = curr;
- }
- }
-
- /*--- Create the Huffman decoding tables ---*/
- for (t = 0; t < nGroups; t++) {
- minLen = 32;
- maxLen = 0;
- for (i = 0; i < alphaSize; i++) {
- if (s->len[t][i] > maxLen) maxLen = s->len[t][i];
- if (s->len[t][i] < minLen) minLen = s->len[t][i];
- }
- BZ2_hbCreateDecodeTables (
- &(s->limit[t][0]),
- &(s->base[t][0]),
- &(s->perm[t][0]),
- &(s->len[t][0]),
- minLen, maxLen, alphaSize
- );
- s->minLens[t] = minLen;
- }
-
- /*--- Now the MTF values ---*/
-
- EOB = s->nInUse+1;
- nblockMAX = 100000 * s->blockSize100k;
- groupNo = -1;
- groupPos = 0;
-
- for (i = 0; i <= 255; i++) s->unzftab[i] = 0;
-
- /*-- MTF init --*/
- {
- Int32 ii, jj, kk;
- kk = MTFA_SIZE-1;
- for (ii = 256 / MTFL_SIZE - 1; ii >= 0; ii--) {
- for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
- s->mtfa[kk] = (UChar)(ii * MTFL_SIZE + jj);
- kk--;
- }
- s->mtfbase[ii] = kk + 1;
- }
- }
- /*-- end MTF init --*/
-
- nblock = 0;
- GET_MTF_VAL(BZ_X_MTF_1, BZ_X_MTF_2, nextSym);
-
- while (True) {
-
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
-#endif
- if (nextSym == EOB) break;
-
- if (nextSym == BZ_RUNA || nextSym == BZ_RUNB) {
-
- es = -1;
- N = 1;
- do {
- if (nextSym == BZ_RUNA) es = es + (0+1) * N; else
- if (nextSym == BZ_RUNB) es = es + (1+1) * N;
- N = N * 2;
- GET_MTF_VAL(BZ_X_MTF_3, BZ_X_MTF_4, nextSym);
- }
- while (nextSym == BZ_RUNA || nextSym == BZ_RUNB);
-
- es++;
- uc = s->seqToUnseq[ s->mtfa[s->mtfbase[0]] ];
- s->unzftab[uc] += es;
-
- if (s->smallDecompress)
- while (es > 0) {
- if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
- s->ll16[nblock] = (UInt16)uc;
- nblock++;
- es--;
- }
- else
- while (es > 0) {
- if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
- s->tt[nblock] = (UInt32)uc;
- nblock++;
- es--;
- };
-
- continue;
-
- } else {
-
- if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
-
- /*-- uc = MTF ( nextSym-1 ) --*/
- {
- Int32 ii, jj, kk, pp, lno, off;
- UInt32 nn;
- nn = (UInt32)(nextSym - 1);
-
- if (nn < MTFL_SIZE) {
- /* avoid general-case expense */
- pp = s->mtfbase[0];
- uc = s->mtfa[pp+nn];
- while (nn > 3) {
- Int32 z = pp+nn;
- s->mtfa[(z) ] = s->mtfa[(z)-1];
- s->mtfa[(z)-1] = s->mtfa[(z)-2];
- s->mtfa[(z)-2] = s->mtfa[(z)-3];
- s->mtfa[(z)-3] = s->mtfa[(z)-4];
- nn -= 4;
- }
- while (nn > 0) {
- s->mtfa[(pp+nn)] = s->mtfa[(pp+nn)-1]; nn--;
- };
- s->mtfa[pp] = uc;
- } else {
- /* general case */
- lno = nn / MTFL_SIZE;
- off = nn % MTFL_SIZE;
- pp = s->mtfbase[lno] + off;
- uc = s->mtfa[pp];
- while (pp > s->mtfbase[lno]) {
- s->mtfa[pp] = s->mtfa[pp-1]; pp--;
- };
- s->mtfbase[lno]++;
- while (lno > 0) {
- s->mtfbase[lno]--;
- s->mtfa[s->mtfbase[lno]]
- = s->mtfa[s->mtfbase[lno-1] + MTFL_SIZE - 1];
- lno--;
- }
- s->mtfbase[0]--;
- s->mtfa[s->mtfbase[0]] = uc;
- if (s->mtfbase[0] == 0) {
- kk = MTFA_SIZE-1;
- for (ii = 256 / MTFL_SIZE-1; ii >= 0; ii--) {
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
-#endif
- for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
- s->mtfa[kk] = s->mtfa[s->mtfbase[ii] + jj];
- kk--;
- }
- s->mtfbase[ii] = kk + 1;
- }
- }
- }
- }
- /*-- end uc = MTF ( nextSym-1 ) --*/
-
- s->unzftab[s->seqToUnseq[uc]]++;
- if (s->smallDecompress)
- s->ll16[nblock] = (UInt16)(s->seqToUnseq[uc]); else
- s->tt[nblock] = (UInt32)(s->seqToUnseq[uc]);
- nblock++;
-
- GET_MTF_VAL(BZ_X_MTF_5, BZ_X_MTF_6, nextSym);
- continue;
- }
- }
-
- /* Now we know what nblock is, we can do a better sanity
- check on s->origPtr.
- */
- if (s->origPtr < 0 || s->origPtr >= nblock)
- RETURN(BZ_DATA_ERROR);
-
- s->state_out_len = 0;
- s->state_out_ch = 0;
- BZ_INITIALISE_CRC ( s->calculatedBlockCRC );
- s->state = BZ_X_OUTPUT;
- if (s->verbosity >= 2) VPrintf0 ( "rt+rld" );
-
- /*-- Set up cftab to facilitate generation of T^(-1) --*/
- s->cftab[0] = 0;
- for (i = 1; i <= 256; i++) s->cftab[i] = s->unzftab[i-1];
- for (i = 1; i <= 256; i++) s->cftab[i] += s->cftab[i-1];
-
- if (s->smallDecompress) {
-
- /*-- Make a copy of cftab, used in generation of T --*/
- for (i = 0; i <= 256; i++) s->cftabCopy[i] = s->cftab[i];
-
- /*-- compute the T vector --*/
- for (i = 0; i < nblock; i++) {
- uc = (UChar)(s->ll16[i]);
- SET_LL(i, s->cftabCopy[uc]);
- s->cftabCopy[uc]++;
- }
-
- /*-- Compute T^(-1) by pointer reversal on T --*/
- i = s->origPtr;
- j = GET_LL(i);
- do {
- Int32 tmp = GET_LL(j);
- SET_LL(j, i);
- i = j;
- j = tmp;
- }
- while (i != s->origPtr);
-
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
-#endif
- s->tPos = s->origPtr;
- s->nblock_used = 0;
- if (s->blockRandomised) {
- BZ_RAND_INIT_MASK;
- BZ_GET_SMALL(s->k0); s->nblock_used++;
- BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
- } else {
- BZ_GET_SMALL(s->k0); s->nblock_used++;
- }
-
- } else {
-
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
-#endif
- /*-- compute the T^(-1) vector --*/
- for (i = 0; i < nblock; i++) {
- uc = (UChar)(s->tt[i] & 0xff);
- s->tt[s->cftab[uc]] |= (i << 8);
- s->cftab[uc]++;
- }
-
- s->tPos = s->tt[s->origPtr] >> 8;
- s->nblock_used = 0;
- if (s->blockRandomised) {
- BZ_RAND_INIT_MASK;
- BZ_GET_FAST(s->k0); s->nblock_used++;
- BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
- } else {
- BZ_GET_FAST(s->k0); s->nblock_used++;
- }
-
- }
-
- RETURN(BZ_OK);
-
-
- endhdr_2:
-
- GET_UCHAR(BZ_X_ENDHDR_2, uc);
- if (uc != 0x72) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_ENDHDR_3, uc);
- if (uc != 0x45) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_ENDHDR_4, uc);
- if (uc != 0x38) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_ENDHDR_5, uc);
- if (uc != 0x50) RETURN(BZ_DATA_ERROR);
- GET_UCHAR(BZ_X_ENDHDR_6, uc);
- if (uc != 0x90) RETURN(BZ_DATA_ERROR);
-
- s->storedCombinedCRC = 0;
- GET_UCHAR(BZ_X_CCRC_1, uc);
- s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
- GET_UCHAR(BZ_X_CCRC_2, uc);
- s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
- GET_UCHAR(BZ_X_CCRC_3, uc);
- s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
- GET_UCHAR(BZ_X_CCRC_4, uc);
- s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
-
- s->state = BZ_X_IDLE;
- RETURN(BZ_STREAM_END);
-
- default: AssertH ( False, 4001 );
- }
-
- AssertH ( False, 4002 );
-
- save_state_and_return:
-
- s->save_i = i;
- s->save_j = j;
- s->save_t = t;
- s->save_alphaSize = alphaSize;
- s->save_nGroups = nGroups;
- s->save_nSelectors = nSelectors;
- s->save_EOB = EOB;
- s->save_groupNo = groupNo;
- s->save_groupPos = groupPos;
- s->save_nextSym = nextSym;
- s->save_nblockMAX = nblockMAX;
- s->save_nblock = nblock;
- s->save_es = es;
- s->save_N = N;
- s->save_curr = curr;
- s->save_zt = zt;
- s->save_zn = zn;
- s->save_zvec = zvec;
- s->save_zj = zj;
- s->save_gSel = gSel;
- s->save_gMinlen = gMinlen;
- s->save_gLimit = gLimit;
- s->save_gBase = gBase;
- s->save_gPerm = gPerm;
-
- return retVal;
-}
-
-
-/*-------------------------------------------------------------*/
-/*--- end decompress.c ---*/
-/*-------------------------------------------------------------*/
+++ /dev/null
-#include <config.h>
-
-/*-------------------------------------------------------------*/
-/*--- Huffman coding low-level stuff ---*/
-/*--- huffman.c ---*/
-/*-------------------------------------------------------------*/
-
-/*--
- This file is a part of bzip2 and/or libbzip2, a program and
- library for lossless, block-sorting data compression.
-
- Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. The origin of this software must not be misrepresented; you must
- not claim that you wrote the original software. If you use this
- software in a product, an acknowledgment in the product
- documentation would be appreciated but is not required.
-
- 3. Altered source versions must be plainly marked as such, and must
- not be misrepresented as being the original software.
-
- 4. The name of the author may not be used to endorse or promote
- products derived from this software without specific prior written
- permission.
-
- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- Julian Seward, Cambridge, UK.
- jseward@acm.org
- bzip2/libbzip2 version 1.0 of 21 March 2000
-
- This program is based on (at least) the work of:
- Mike Burrows
- David Wheeler
- Peter Fenwick
- Alistair Moffat
- Radford Neal
- Ian H. Witten
- Robert Sedgewick
- Jon L. Bentley
-
- For more information on these sources, see the manual.
---*/
-
-
-#include "bzlib_private.h"
-
-/*---------------------------------------------------*/
-#define WEIGHTOF(zz0) ((zz0) & 0xffffff00)
-#define DEPTHOF(zz1) ((zz1) & 0x000000ff)
-#define MYMAX(zz2,zz3) ((zz2) > (zz3) ? (zz2) : (zz3))
-
-#define ADDWEIGHTS(zw1,zw2) \
- (WEIGHTOF(zw1)+WEIGHTOF(zw2)) | \
- (1 + MYMAX(DEPTHOF(zw1),DEPTHOF(zw2)))
-
-#define UPHEAP(z) \
-{ \
- Int32 zz, tmp; \
- zz = z; tmp = heap[zz]; \
- while (weight[tmp] < weight[heap[zz >> 1]]) { \
- heap[zz] = heap[zz >> 1]; \
- zz >>= 1; \
- } \
- heap[zz] = tmp; \
-}
-
-#define DOWNHEAP(z) \
-{ \
- Int32 zz, yy, tmp; \
- zz = z; tmp = heap[zz]; \
- while (True) { \
- yy = zz << 1; \
- if (yy > nHeap) break; \
- if (yy < nHeap && \
- weight[heap[yy+1]] < weight[heap[yy]]) \
- yy++; \
- if (weight[tmp] < weight[heap[yy]]) break; \
- heap[zz] = heap[yy]; \
- zz = yy; \
- } \
- heap[zz] = tmp; \
-}
-
-
-/*---------------------------------------------------*/
-void BZ2_hbMakeCodeLengths ( UChar *len,
- Int32 *freq,
- Int32 alphaSize,
- Int32 maxLen )
-{
- /*--
- Nodes and heap entries run from 1. Entry 0
- for both the heap and nodes is a sentinel.
- --*/
- Int32 nNodes, nHeap, n1, n2, i, j, k;
- Bool tooLong;
-
- Int32 heap [ BZ_MAX_ALPHA_SIZE + 2 ];
- Int32 weight [ BZ_MAX_ALPHA_SIZE * 2 ];
- Int32 parent [ BZ_MAX_ALPHA_SIZE * 2 ];
-
- for (i = 0; i < alphaSize; i++)
- weight[i+1] = (freq[i] == 0 ? 1 : freq[i]) << 8;
-
- while (True) {
-
- nNodes = alphaSize;
- nHeap = 0;
-
- heap[0] = 0;
- weight[0] = 0;
- parent[0] = -2;
-
- for (i = 1; i <= alphaSize; i++) {
- parent[i] = -1;
- nHeap++;
- heap[nHeap] = i;
- UPHEAP(nHeap);
- }
-
- AssertH( nHeap < (BZ_MAX_ALPHA_SIZE+2), 2001 );
-
- while (nHeap > 1) {
- n1 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
- n2 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
- nNodes++;
- parent[n1] = parent[n2] = nNodes;
- weight[nNodes] = ADDWEIGHTS(weight[n1], weight[n2]);
- parent[nNodes] = -1;
- nHeap++;
- heap[nHeap] = nNodes;
- UPHEAP(nHeap);
- }
-
- AssertH( nNodes < (BZ_MAX_ALPHA_SIZE * 2), 2002 );
-
- tooLong = False;
- for (i = 1; i <= alphaSize; i++) {
- j = 0;
- k = i;
- while (parent[k] >= 0) { k = parent[k]; j++; }
- len[i-1] = j;
- if (j > maxLen) tooLong = True;
- }
-
- if (! tooLong) break;
-
- for (i = 1; i < alphaSize; i++) {
- j = weight[i] >> 8;
- j = 1 + (j / 2);
- weight[i] = j << 8;
- }
- }
-}
-
-
-/*---------------------------------------------------*/
-void BZ2_hbAssignCodes ( Int32 *code,
- UChar *length,
- Int32 minLen,
- Int32 maxLen,
- Int32 alphaSize )
-{
- Int32 n, vec, i;
-
- vec = 0;
- for (n = minLen; n <= maxLen; n++) {
- for (i = 0; i < alphaSize; i++)
- if (length[i] == n) { code[i] = vec; vec++; };
- vec <<= 1;
- }
-}
-
-
-/*---------------------------------------------------*/
-void BZ2_hbCreateDecodeTables ( Int32 *limit,
- Int32 *base,
- Int32 *perm,
- UChar *length,
- Int32 minLen,
- Int32 maxLen,
- Int32 alphaSize )
-{
- Int32 pp, i, j, vec;
-
- pp = 0;
- for (i = minLen; i <= maxLen; i++)
- for (j = 0; j < alphaSize; j++)
- if (length[j] == i) { perm[pp] = j; pp++; };
-
- for (i = 0; i < BZ_MAX_CODE_LEN; i++) base[i] = 0;
- for (i = 0; i < alphaSize; i++) base[length[i]+1]++;
-
- for (i = 1; i < BZ_MAX_CODE_LEN; i++) base[i] += base[i-1];
-
- for (i = 0; i < BZ_MAX_CODE_LEN; i++) limit[i] = 0;
- vec = 0;
-
- for (i = minLen; i <= maxLen; i++) {
- vec += (base[i+1] - base[i]);
- limit[i] = vec-1;
- vec <<= 1;
- }
- for (i = minLen + 1; i <= maxLen; i++)
- base[i] = ((limit[i-1] + 1) << 1) - base[i];
-}
-
-
-/*-------------------------------------------------------------*/
-/*--- end huffman.c ---*/
-/*-------------------------------------------------------------*/
+++ /dev/null
-/*
- * This file is a modified version of bzlib_private.h from the bzip2-1.0.2
- * distribution which can be found at http://sources.redhat.com/bzip2/
- */
-
-/*-------------------------------------------------------------*/
-/*--- Private header file for the library. ---*/
-/*--- bzlib_private.h ---*/
-/*-------------------------------------------------------------*/
-
-/*--
- This file is a part of bzip2 and/or libbzip2, a program and
- library for lossless, block-sorting data compression.
-
- Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. The origin of this software must not be misrepresented; you must
- not claim that you wrote the original software. If you use this
- software in a product, an acknowledgment in the product
- documentation would be appreciated but is not required.
-
- 3. Altered source versions must be plainly marked as such, and must
- not be misrepresented as being the original software.
-
- 4. The name of the author may not be used to endorse or promote
- products derived from this software without specific prior written
- permission.
-
- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- Julian Seward, Cambridge, UK.
- jseward@acm.org
- bzip2/libbzip2 version 1.0 of 21 March 2000
-
- This program is based on (at least) the work of:
- Mike Burrows
- David Wheeler
- Peter Fenwick
- Alistair Moffat
- Radford Neal
- Ian H. Witten
- Robert Sedgewick
- Jon L. Bentley
-
- For more information on these sources, see the manual.
---*/
-
-
-#ifndef _BZLIB_PRIVATE_H
-#define _BZLIB_PRIVATE_H
-
-#include <malloc.h>
-
-#include "bzlib.h"
-
-#ifndef BZ_NO_STDIO
-#include <stdio.h>
-#include <ctype.h>
-#include <string.h>
-#endif
-
-
-/*-- General stuff. --*/
-
-#define BZ_VERSION "1.0.2, 30-Dec-2001"
-
-typedef char Char;
-typedef unsigned char Bool;
-typedef unsigned char UChar;
-typedef int Int32;
-typedef unsigned int UInt32;
-typedef short Int16;
-typedef unsigned short UInt16;
-
-#define True ((Bool)1)
-#define False ((Bool)0)
-
-#ifndef __GNUC__
-#define __inline__ /* */
-#endif
-
-#ifndef BZ_NO_STDIO
-extern void BZ2_bz__AssertH__fail ( int errcode );
-#define AssertH(cond,errcode) \
- { if (!(cond)) BZ2_bz__AssertH__fail ( errcode ); }
-#if BZ_DEBUG
-#define AssertD(cond,msg) \
- { if (!(cond)) { \
- fprintf ( stderr, \
- "\n\nlibbzip2(debug build): internal error\n\t%s\n", msg );\
- exit(1); \
- }}
-#else
-#define AssertD(cond,msg) /* */
-#endif
-#define VPrintf0(zf) \
- fprintf(stderr,zf)
-#define VPrintf1(zf,za1) \
- fprintf(stderr,zf,za1)
-#define VPrintf2(zf,za1,za2) \
- fprintf(stderr,zf,za1,za2)
-#define VPrintf3(zf,za1,za2,za3) \
- fprintf(stderr,zf,za1,za2,za3)
-#define VPrintf4(zf,za1,za2,za3,za4) \
- fprintf(stderr,zf,za1,za2,za3,za4)
-#define VPrintf5(zf,za1,za2,za3,za4,za5) \
- fprintf(stderr,zf,za1,za2,za3,za4,za5)
-#else
-extern void bz_internal_error ( int errcode );
-#define AssertH(cond,errcode) \
- { if (!(cond)) bz_internal_error ( errcode ); }
-#define AssertD(cond,msg) /* */
-#define VPrintf0(zf) /* */
-#define VPrintf1(zf,za1) /* */
-#define VPrintf2(zf,za1,za2) /* */
-#define VPrintf3(zf,za1,za2,za3) /* */
-#define VPrintf4(zf,za1,za2,za3,za4) /* */
-#define VPrintf5(zf,za1,za2,za3,za4,za5) /* */
-#endif
-
-
-#define BZALLOC(nnn) (strm->bzalloc)(strm->opaque,(nnn),1)
-#define BZFREE(ppp) (strm->bzfree)(strm->opaque,(ppp))
-
-
-/*-- Header bytes. --*/
-
-#define BZ_HDR_B 0x42 /* 'B' */
-#define BZ_HDR_Z 0x5a /* 'Z' */
-#define BZ_HDR_h 0x68 /* 'h' */
-#define BZ_HDR_0 0x30 /* '0' */
-
-/*-- Constants for the back end. --*/
-
-#define BZ_MAX_ALPHA_SIZE 258
-#define BZ_MAX_CODE_LEN 23
-
-#define BZ_RUNA 0
-#define BZ_RUNB 1
-
-#define BZ_N_GROUPS 6
-#define BZ_G_SIZE 50
-#define BZ_N_ITERS 4
-
-#define BZ_MAX_SELECTORS (2 + (900000 / BZ_G_SIZE))
-
-
-/*-- Stuff for randomising repetitive blocks. --*/
-
-extern Int32 BZ2_rNums[512];
-
-#define BZ_RAND_DECLS \
- Int32 rNToGo; \
- Int32 rTPos \
-
-#define BZ_RAND_INIT_MASK \
- s->rNToGo = 0; \
- s->rTPos = 0 \
-
-#define BZ_RAND_MASK ((s->rNToGo == 1) ? 1 : 0)
-
-#define BZ_RAND_UPD_MASK \
- if (s->rNToGo == 0) { \
- s->rNToGo = BZ2_rNums[s->rTPos]; \
- s->rTPos++; \
- if (s->rTPos == 512) s->rTPos = 0; \
- } \
- s->rNToGo--;
-
-
-/*-- Stuff for doing CRCs. --*/
-
-extern UInt32 BZ2_crc32Table[256];
-
-#define BZ_INITIALISE_CRC(crcVar) \
-{ \
- crcVar = 0xffffffffL; \
-}
-
-#define BZ_FINALISE_CRC(crcVar) \
-{ \
- crcVar = ~(crcVar); \
-}
-
-#define BZ_UPDATE_CRC(crcVar,cha) \
-{ \
- crcVar = (crcVar << 8) ^ \
- BZ2_crc32Table[(crcVar >> 24) ^ \
- ((UChar)cha)]; \
-}
-
-
-/*-- States and modes for compression. --*/
-
-#define BZ_M_IDLE 1
-#define BZ_M_RUNNING 2
-#define BZ_M_FLUSHING 3
-#define BZ_M_FINISHING 4
-
-#define BZ_S_OUTPUT 1
-#define BZ_S_INPUT 2
-
-#define BZ_N_RADIX 2
-#define BZ_N_QSORT 12
-#define BZ_N_SHELL 18
-#define BZ_N_OVERSHOOT (BZ_N_RADIX + BZ_N_QSORT + BZ_N_SHELL + 2)
-
-
-/*-- Structure holding all the compression-side stuff. --*/
-
-typedef
- struct {
- /* pointer back to the struct bz_stream */
- bz_stream* strm;
-
- /* mode this stream is in, and whether inputting */
- /* or outputting data */
- Int32 mode;
- Int32 state;
-
- /* remembers avail_in when flush/finish requested */
- UInt32 avail_in_expect;
-
- /* for doing the block sorting */
- UInt32* arr1;
- UInt32* arr2;
- UInt32* ftab;
- Int32 origPtr;
-
- /* aliases for arr1 and arr2 */
- UInt32* ptr;
- UChar* block;
- UInt16* mtfv;
- UChar* zbits;
-
- /* for deciding when to use the fallback sorting algorithm */
- Int32 workFactor;
-
- /* run-length-encoding of the input */
- UInt32 state_in_ch;
- Int32 state_in_len;
- BZ_RAND_DECLS;
-
- /* input and output limits and current posns */
- Int32 nblock;
- Int32 nblockMAX;
- Int32 numZ;
- Int32 state_out_pos;
-
- /* map of bytes used in block */
- Int32 nInUse;
- Bool inUse[256];
- UChar unseqToSeq[256];
-
- /* the buffer for bit stream creation */
- UInt32 bsBuff;
- Int32 bsLive;
-
- /* block and combined CRCs */
- UInt32 blockCRC;
- UInt32 combinedCRC;
-
- /* misc administratium */
- Int32 verbosity;
- Int32 blockNo;
- Int32 blockSize100k;
-
- /* stuff for coding the MTF values */
- Int32 nMTF;
- Int32 mtfFreq [BZ_MAX_ALPHA_SIZE];
- UChar selector [BZ_MAX_SELECTORS];
- UChar selectorMtf[BZ_MAX_SELECTORS];
-
- UChar len [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
- Int32 code [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
- Int32 rfreq [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
- /* second dimension: only 3 needed; 4 makes index calculations faster */
- UInt32 len_pack[BZ_MAX_ALPHA_SIZE][4];
-
- }
- EState;
-
-
-/*-- externs for compression. --*/
-
-extern void
-BZ2_blockSort ( EState* );
-
-extern void
-BZ2_compressBlock ( EState*, Bool );
-
-extern void
-BZ2_bsInitWrite ( EState* );
-
-extern void
-BZ2_hbAssignCodes ( Int32*, UChar*, Int32, Int32, Int32 );
-
-extern void
-BZ2_hbMakeCodeLengths ( UChar*, Int32*, Int32, Int32 );
-
-
-/*-- states for decompression. --*/
-
-#define BZ_X_IDLE 1
-#define BZ_X_OUTPUT 2
-
-#define BZ_X_MAGIC_1 10
-#define BZ_X_MAGIC_2 11
-#define BZ_X_MAGIC_3 12
-#define BZ_X_MAGIC_4 13
-#define BZ_X_BLKHDR_1 14
-#define BZ_X_BLKHDR_2 15
-#define BZ_X_BLKHDR_3 16
-#define BZ_X_BLKHDR_4 17
-#define BZ_X_BLKHDR_5 18
-#define BZ_X_BLKHDR_6 19
-#define BZ_X_BCRC_1 20
-#define BZ_X_BCRC_2 21
-#define BZ_X_BCRC_3 22
-#define BZ_X_BCRC_4 23
-#define BZ_X_RANDBIT 24
-#define BZ_X_ORIGPTR_1 25
-#define BZ_X_ORIGPTR_2 26
-#define BZ_X_ORIGPTR_3 27
-#define BZ_X_MAPPING_1 28
-#define BZ_X_MAPPING_2 29
-#define BZ_X_SELECTOR_1 30
-#define BZ_X_SELECTOR_2 31
-#define BZ_X_SELECTOR_3 32
-#define BZ_X_CODING_1 33
-#define BZ_X_CODING_2 34
-#define BZ_X_CODING_3 35
-#define BZ_X_MTF_1 36
-#define BZ_X_MTF_2 37
-#define BZ_X_MTF_3 38
-#define BZ_X_MTF_4 39
-#define BZ_X_MTF_5 40
-#define BZ_X_MTF_6 41
-#define BZ_X_ENDHDR_2 42
-#define BZ_X_ENDHDR_3 43
-#define BZ_X_ENDHDR_4 44
-#define BZ_X_ENDHDR_5 45
-#define BZ_X_ENDHDR_6 46
-#define BZ_X_CCRC_1 47
-#define BZ_X_CCRC_2 48
-#define BZ_X_CCRC_3 49
-#define BZ_X_CCRC_4 50
-
-
-/*-- Constants for the fast MTF decoder. --*/
-
-#define MTFA_SIZE 4096
-#define MTFL_SIZE 16
-
-
-/*-- Structure holding all the decompression-side stuff. --*/
-
-typedef
- struct {
- /* pointer back to the struct bz_stream */
- bz_stream* strm;
-
- /* state indicator for this stream */
- Int32 state;
-
- /* for doing the final run-length decoding */
- UChar state_out_ch;
- Int32 state_out_len;
- Bool blockRandomised;
- BZ_RAND_DECLS;
-
- /* the buffer for bit stream reading */
- UInt32 bsBuff;
- Int32 bsLive;
-
- /* misc administratium */
- Int32 blockSize100k;
- Bool smallDecompress;
- Int32 currBlockNo;
- Int32 verbosity;
-
- /* for undoing the Burrows-Wheeler transform */
- Int32 origPtr;
- UInt32 tPos;
- Int32 k0;
- Int32 unzftab[256];
- Int32 nblock_used;
- Int32 cftab[257];
- Int32 cftabCopy[257];
-
- /* for undoing the Burrows-Wheeler transform (FAST) */
- UInt32 *tt;
-
- /* for undoing the Burrows-Wheeler transform (SMALL) */
- UInt16 *ll16;
- UChar *ll4;
-
- /* stored and calculated CRCs */
- UInt32 storedBlockCRC;
- UInt32 storedCombinedCRC;
- UInt32 calculatedBlockCRC;
- UInt32 calculatedCombinedCRC;
-
- /* map of bytes used in block */
- Int32 nInUse;
- Bool inUse[256];
- Bool inUse16[16];
- UChar seqToUnseq[256];
-
- /* for decoding the MTF values */
- UChar mtfa [MTFA_SIZE];
- Int32 mtfbase[256 / MTFL_SIZE];
- UChar selector [BZ_MAX_SELECTORS];
- UChar selectorMtf[BZ_MAX_SELECTORS];
- UChar len [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
-
- Int32 limit [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
- Int32 base [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
- Int32 perm [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
- Int32 minLens[BZ_N_GROUPS];
-
- /* save area for scalars in the main decompress code */
- Int32 save_i;
- Int32 save_j;
- Int32 save_t;
- Int32 save_alphaSize;
- Int32 save_nGroups;
- Int32 save_nSelectors;
- Int32 save_EOB;
- Int32 save_groupNo;
- Int32 save_groupPos;
- Int32 save_nextSym;
- Int32 save_nblockMAX;
- Int32 save_nblock;
- Int32 save_es;
- Int32 save_N;
- Int32 save_curr;
- Int32 save_zt;
- Int32 save_zn;
- Int32 save_zvec;
- Int32 save_zj;
- Int32 save_gSel;
- Int32 save_gMinlen;
- Int32* save_gLimit;
- Int32* save_gBase;
- Int32* save_gPerm;
-
- }
- DState;
-
-
-/*-- Macros for decompression. --*/
-
-#define BZ_GET_FAST(cccc) \
- s->tPos = s->tt[s->tPos]; \
- cccc = (UChar)(s->tPos & 0xff); \
- s->tPos >>= 8;
-
-#define BZ_GET_FAST_C(cccc) \
- c_tPos = c_tt[c_tPos]; \
- cccc = (UChar)(c_tPos & 0xff); \
- c_tPos >>= 8;
-
-#define SET_LL4(i,n) \
- { if (((i) & 0x1) == 0) \
- s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0xf0) | (n); else \
- s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0x0f) | ((n) << 4); \
- }
-
-#define GET_LL4(i) \
- ((((UInt32)(s->ll4[(i) >> 1])) >> (((i) << 2) & 0x4)) & 0xF)
-
-#define SET_LL(i,n) \
- { s->ll16[i] = (UInt16)(n & 0x0000ffff); \
- SET_LL4(i, n >> 16); \
- }
-
-#define GET_LL(i) \
- (((UInt32)s->ll16[i]) | (GET_LL4(i) << 16))
-
-#define BZ_GET_SMALL(cccc) \
- cccc = BZ2_indexIntoF ( s->tPos, s->cftab ); \
- s->tPos = GET_LL(s->tPos);
-
-
-/*-- externs for decompression. --*/
-
-extern Int32
-BZ2_indexIntoF ( Int32, Int32* );
-
-extern Int32
-BZ2_decompress ( DState* );
-
-extern void
-BZ2_hbCreateDecodeTables ( Int32*, Int32*, Int32*, UChar*,
- Int32, Int32, Int32 );
-
-
-#endif
-
-
-/*-- BZ_NO_STDIO seems to make NULL disappear on some platforms. --*/
-
-#ifdef BZ_NO_STDIO
-#ifndef NULL
-#define NULL 0
-#endif
-#endif
-
-
-/*-------------------------------------------------------------*/
-/*--- end bzlib_private.h ---*/
-/*-------------------------------------------------------------*/
+++ /dev/null
-#include <config.h>
-
-/*-------------------------------------------------------------*/
-/*--- Table for randomising repetitive blocks ---*/
-/*--- randtable.c ---*/
-/*-------------------------------------------------------------*/
-
-/*--
- This file is a part of bzip2 and/or libbzip2, a program and
- library for lossless, block-sorting data compression.
-
- Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. The origin of this software must not be misrepresented; you must
- not claim that you wrote the original software. If you use this
- software in a product, an acknowledgment in the product
- documentation would be appreciated but is not required.
-
- 3. Altered source versions must be plainly marked as such, and must
- not be misrepresented as being the original software.
-
- 4. The name of the author may not be used to endorse or promote
- products derived from this software without specific prior written
- permission.
-
- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- Julian Seward, Cambridge, UK.
- jseward@acm.org
- bzip2/libbzip2 version 1.0 of 21 March 2000
-
- This program is based on (at least) the work of:
- Mike Burrows
- David Wheeler
- Peter Fenwick
- Alistair Moffat
- Radford Neal
- Ian H. Witten
- Robert Sedgewick
- Jon L. Bentley
-
- For more information on these sources, see the manual.
---*/
-
-
-#include "bzlib_private.h"
-
-
-/*---------------------------------------------*/
-Int32 BZ2_rNums[512] = {
- 619, 720, 127, 481, 931, 816, 813, 233, 566, 247,
- 985, 724, 205, 454, 863, 491, 741, 242, 949, 214,
- 733, 859, 335, 708, 621, 574, 73, 654, 730, 472,
- 419, 436, 278, 496, 867, 210, 399, 680, 480, 51,
- 878, 465, 811, 169, 869, 675, 611, 697, 867, 561,
- 862, 687, 507, 283, 482, 129, 807, 591, 733, 623,
- 150, 238, 59, 379, 684, 877, 625, 169, 643, 105,
- 170, 607, 520, 932, 727, 476, 693, 425, 174, 647,
- 73, 122, 335, 530, 442, 853, 695, 249, 445, 515,
- 909, 545, 703, 919, 874, 474, 882, 500, 594, 612,
- 641, 801, 220, 162, 819, 984, 589, 513, 495, 799,
- 161, 604, 958, 533, 221, 400, 386, 867, 600, 782,
- 382, 596, 414, 171, 516, 375, 682, 485, 911, 276,
- 98, 553, 163, 354, 666, 933, 424, 341, 533, 870,
- 227, 730, 475, 186, 263, 647, 537, 686, 600, 224,
- 469, 68, 770, 919, 190, 373, 294, 822, 808, 206,
- 184, 943, 795, 384, 383, 461, 404, 758, 839, 887,
- 715, 67, 618, 276, 204, 918, 873, 777, 604, 560,
- 951, 160, 578, 722, 79, 804, 96, 409, 713, 940,
- 652, 934, 970, 447, 318, 353, 859, 672, 112, 785,
- 645, 863, 803, 350, 139, 93, 354, 99, 820, 908,
- 609, 772, 154, 274, 580, 184, 79, 626, 630, 742,
- 653, 282, 762, 623, 680, 81, 927, 626, 789, 125,
- 411, 521, 938, 300, 821, 78, 343, 175, 128, 250,
- 170, 774, 972, 275, 999, 639, 495, 78, 352, 126,
- 857, 956, 358, 619, 580, 124, 737, 594, 701, 612,
- 669, 112, 134, 694, 363, 992, 809, 743, 168, 974,
- 944, 375, 748, 52, 600, 747, 642, 182, 862, 81,
- 344, 805, 988, 739, 511, 655, 814, 334, 249, 515,
- 897, 955, 664, 981, 649, 113, 974, 459, 893, 228,
- 433, 837, 553, 268, 926, 240, 102, 654, 459, 51,
- 686, 754, 806, 760, 493, 403, 415, 394, 687, 700,
- 946, 670, 656, 610, 738, 392, 760, 799, 887, 653,
- 978, 321, 576, 617, 626, 502, 894, 679, 243, 440,
- 680, 879, 194, 572, 640, 724, 926, 56, 204, 700,
- 707, 151, 457, 449, 797, 195, 791, 558, 945, 679,
- 297, 59, 87, 824, 713, 663, 412, 693, 342, 606,
- 134, 108, 571, 364, 631, 212, 174, 643, 304, 329,
- 343, 97, 430, 751, 497, 314, 983, 374, 822, 928,
- 140, 206, 73, 263, 980, 736, 876, 478, 430, 305,
- 170, 514, 364, 692, 829, 82, 855, 953, 676, 246,
- 369, 970, 294, 750, 807, 827, 150, 790, 288, 923,
- 804, 378, 215, 828, 592, 281, 565, 555, 710, 82,
- 896, 831, 547, 261, 524, 462, 293, 465, 502, 56,
- 661, 821, 976, 991, 658, 869, 905, 758, 745, 193,
- 768, 550, 608, 933, 378, 286, 215, 979, 792, 961,
- 61, 688, 793, 644, 986, 403, 106, 366, 905, 644,
- 372, 567, 466, 434, 645, 210, 389, 550, 919, 135,
- 780, 773, 635, 389, 707, 100, 626, 958, 165, 504,
- 920, 176, 193, 713, 857, 265, 203, 50, 668, 108,
- 645, 990, 626, 197, 510, 357, 358, 850, 858, 364,
- 936, 638
-};
-
-
-/*-------------------------------------------------------------*/
-/*--- end randtable.c ---*/
-/*-------------------------------------------------------------*/
COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
COMPAT(INTEL_MICROCODE, "intel,microcode"),
COMPAT(MEMORY_SPD, "memory-spd"),
+ COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
+ COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
+ COMPAT(INTEL_GMA, "intel,gma"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
return -ENOENT;
}
-int fdtdec_get_alias_node(const void *blob, const char *name)
-{
- const char *prop;
- int alias_node;
- int len;
-
- if (!blob)
- return -FDT_ERR_NOTFOUND;
- alias_node = fdt_path_offset(blob, "/aliases");
- prop = fdt_getprop(blob, alias_node, name, &len);
- if (!prop)
- return -FDT_ERR_NOTFOUND;
- return fdt_path_offset(blob, prop);
-}
-
int fdtdec_get_chosen_node(const void *blob, const char *name)
{
const char *prop;
# SPDX-License-Identifier: GPL-2.0+
#
-COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \
+obj-y += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \
fdt_empty_tree.o fdt_addresses.o
-
-obj-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
-obj-$(CONFIG_FIT) += $(COBJS-libfdt)
#define __GLUE_ZLIB_H__
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <asm/unaligned.h>
#include <watchdog.h>
#include "u-boot/zlib.h"
if (tmp_ip != 0)
NetCopyIP(&NetServerIP, &bp->bp_siaddr);
memcpy(NetServerEther, ((struct ethernet_hdr *)NetRxPacket)->et_src, 6);
-#endif
- NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
if (strlen(bp->bp_file) > 0)
copy_filename(BootFile, bp->bp_file, sizeof(BootFile));
*/
if (*BootFile)
setenv("bootfile", BootFile);
+#endif
+ NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
}
static int truncate_sz(const char *name, int maxlen, int curlen)
cmd_dt_S_dtb= \
( \
echo '.section .dtb.init.rodata,"a"'; \
+ echo '.balign 16'; \
echo '.global __dtb_$(*F)_begin'; \
echo '__dtb_$(*F)_begin:'; \
echo '.incbin "$<" '; \
echo '__dtb_$(*F)_end:'; \
echo '.global __dtb_$(*F)_end'; \
+ echo '.balign 16'; \
) > $@
$(obj)/%.dtb.S: $(obj)/%.dtb
endif
include $(srctree)/config.mk
+include $(srctree)/arch/$(ARCH)/Makefile
# Enable garbage collection of un-used sections for SPL
KBUILD_CFLAGS += -ffunction-sections -fdata-sections
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
-ifdef CONFIG_SPL_START_S_PATH
-START_PATH := $(CONFIG_SPL_START_S_PATH:"%"=%)
-else
-START_PATH := $(CPUDIR)
-endif
-
-head-y := $(START_PATH)/start.o
-head-$(CONFIG_X86) += $(START_PATH)/start16.o $(START_PATH)/resetvec.o
-head-$(CONFIG_4xx) += $(START_PATH)/resetvec.o
-head-$(CONFIG_MPC85xx) += $(START_PATH)/resetvec.o
-
-libs-y += arch/$(ARCH)/lib/
-
-libs-y += $(CPUDIR)/
-
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/
libs-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
-libs-y += arch/$(ARCH)/imx-common/
-endif
-
-libs-$(CONFIG_ARM) += arch/arm/cpu/
-libs-$(CONFIG_PPC) += arch/powerpc/cpu/
-
head-y := $(addprefix $(obj)/,$(head-y))
libs-y := $(addprefix $(obj)/,$(libs-y))
u-boot-spl-dirs := $(patsubst %/,%,$(filter %/, $(libs-y)))
if ($lk_path ne "" && substr($lk_path,length($lk_path)-1,1) ne "/") {
$lk_path .= "/";
}
- if ( (-f "${lk_path}CREDITS")
- && (-f "${lk_path}Kbuild")
+ if ( (-f "${lk_path}Kbuild")
&& (-f "${lk_path}MAINTAINERS")
&& (-f "${lk_path}Makefile")
&& (-f "${lk_path}README")
{
int i, j;
struct menu *submenu[8], *menu, *location = NULL;
- struct jump_key *jump;
+ struct jump_key *jump = NULL;
str_printf(r, _("Prompt: %s\n"), _(prop->text));
menu = prop->menu->parent;
str_printf(r, _(" Location:\n"));
for (j = 4; --i >= 0; j += 2) {
menu = submenu[i];
- if (head && location && menu == location)
+ if (jump && menu == location)
jump->offset = strlen(r->s);
str_printf(r, "%*c-> %s", j, ' ',
_(menu_get_prompt(menu)));
/fit_check_sign
/fit_info
/gen_eth_addr
+/ifdtool
/img2srec
/kwboot
/dumpimage
valid value, and all will be well. Otherwise buildman will perform random
actions. Use -n to check what the random actions might be.
-If you just want to build the current source tree, leave off the -b flag.
-This will display results and errors as they happen. You can still look
-at them later using -s. Note that buildman will assume that the source
-has changed, and will build all specified boards in this case.
+If you just want to build the current source tree, leave off the -b flag
+and add -e. This will display results and errors as they happen. You can
+still look at them later using -se. Note that buildman will assume that the
+source has changed, and will build all specified boards in this case.
Buildman is optimised for building many commits at once, for many boards.
On multi-core machines, Buildman is fast because it uses most of the
==================
If you have made changes and want to do a quick sanity check of the
-currently-checked-out source, run buildman without the -b flag. This will
-build the selected boards and display build status and errors as it runs
-(i.e. -v amd -e are enabled automatically).
+currently checked-out source, run buildman without the -b flag. This will
+build the selected boards and display build status as it runs (i.e. -v is
+enabled automatically). Use -e to see errors/warnings as well.
Other options
flag to see the full errors and -l to see which boards caused which errors.
If you really want to see build results as they happen, use -v when doing a
-build (-e will be enabled automatically).
+build (and -e to see the errors/warnings too).
You don't need to stick around on that branch while buildman is running. It
checks out its own copy of the source code, so you can change branches,
This has mostly be written in my spare time as a response to my difficulties
in testing large series of patches. Apart from tidying up there is quite a
-bit of scope for improvement. Things like better error diffs, easier access
-to log files, error display while building. Also it would be nice it buildman
-could 'hunt' for problems, perhaps by building a few boards for each arch,
-or checking commits for changed files and building only boards which use
-those files.
+bit of scope for improvement. Things like better error diffs and easier
+access to log files. Also it would be nice it buildman could 'hunt' for
+problems, perhaps by building a few boards for each arch, or checking
+commits for changed files and building only boards which use those files.
Credits
if self._list_error_boards:
names = []
for board in line_boards[line]:
- names.append(board.target)
+ if not board.target in names:
+ names.append(board.target)
names_str = '(%s) ' % ','.join(names)
else:
names_str = ''
# Now write the actual build output
if keep_outputs:
- patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map',
+ patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', '*.img',
'include/autoconf.mk', 'spl/u-boot-spl',
'spl/u-boot-spl.bin']
for pattern in patterns:
if commits:
for upto in range(0, len(series.commits), options.step):
commit = series.commits[upto]
- print ' ', col.Color(col.YELLOW, commit.hash, bright=False),
+ print ' ', col.Color(col.YELLOW, commit.hash[:8], bright=False),
print commit.subject
print
for arg in why_selected:
else:
series = None
options.verbose = True
- options.show_errors = True
# By default we have one thread per CPU. But if there are not enough jobs
# we can have fewer threads and use a high '-j' value for make.
# Detect the start of a new commit
elif commit_match:
self.CloseCommit()
- # TODO: We should store the whole hash, and just display a subset
- self.commit = commit.Commit(commit_match.group(1)[:8])
+ self.commit = commit.Commit(commit_match.group(1))
# Detect tags in the commit message
elif tag_match:
projects / oweals / u-boot.git / commitdiff