return(0);
}
#endif
+
+/*
+ * Returns a string with memory type preceded by a space sign
+ */
+const char* print_mem_type(void){
+ unsigned int reg_val;
+
+ reg_val = (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & HORNET_BOOTSTRAP_MEM_TYPE_MASK) >> HORNET_BOOTSTRAP_MEM_TYPE_SHIFT;
+
+ switch(reg_val){
+ case 0:
+ return " SDRAM";
+ break;
+
+ case 1:
+ return " DDR";
+ break;
+
+ case 2:
+ return " DDR2";
+ break;
+
+ default:
+ return "";
+ break;
+ }
+}
// get flash id
info->flash_id = read_id();
- puts("FLASH: ");
+ puts("FLASH: ");
// fill flash info based on JEDEC ID
switch(info->flash_id){
flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES);
puts("Unknown type (using only 16 MB)\n");
#endif
- printf("\nPlease, send request to add support\nfor your flash - JEDEC ID: 0x%06lX", info->flash_id);
+ printf("\nPlease, send request to add support\nfor your flash - JEDEC ID: 0x%06lX\n", info->flash_id);
info->flash_id = FLASH_CUSTOM;
break;
}
+ puts("\n");
+
return(info->size);
}
long int initdram(){\r
return((long int)wasp_mem_config());\r
}\r
+\r
+/*\r
+ * TODO: Returns a string with memory type preceded by a space sign\r
+ */\r
+const char* print_mem_type(void){\r
+ return "";\r
+}\r
uart_reg_write(UARTDATA_ADDRESS, rdata);
}
+/*
+ * Get CPU, RAM and AHB clocks
+ * Based on: Linux/arch/mips/ath79/clock.c
+ */
void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq) {
- // TODO: check the following code
- u32 ref_clock_rate, pll_freq;
- u32 pllreg, clockreg;
- u32 nint, refdiv, outdiv;
- u32 cpu_div, ahb_div, ddr_div;
+ u32 ref_rate, clock_ctrl, cpu_config, freq, t;
+
+ // determine reference clock (25 or 40 MHz)
+ t = ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS);
- if (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & HORNET_BOOTSTRAP_SEL_25M_40M_MASK) {
- ref_clock_rate = 40 * 1000000;
+ if(t & HORNET_BOOTSTRAP_SEL_25M_40M_MASK){
+ ref_rate = 40000000;
} else {
- ref_clock_rate = 25 * 1000000;
+ ref_rate = 25000000;
}
- pllreg = ar7240_reg_rd(AR7240_CPU_PLL_CONFIG);
- clockreg = ar7240_reg_rd(AR7240_CPU_CLOCK_CONTROL);
+ // read CPU CLock Control Register (CLOCK_CONTROL) value
+ clock_ctrl = ar7240_reg_rd(AR7240_CPU_CLOCK_CONTROL);
- if (clockreg & HORNET_CLOCK_CONTROL_BYPASS_MASK) {
- /* Bypass PLL */
- pll_freq = ref_clock_rate;
- cpu_div = ahb_div = ddr_div = 1;
+ if(clock_ctrl & HORNET_CLOCK_CONTROL_BYPASS_MASK){
+ // PLL is bypassed, so all clocks are == reference clock
+ *cpu_freq = ref_rate;
+ *ddr_freq = ref_rate;
+ *ahb_freq = ref_rate;
} else {
- nint = (pllreg & HORNET_PLL_CONFIG_NINT_MASK) >> HORNET_PLL_CONFIG_NINT_SHIFT;
- refdiv = (pllreg & HORNET_PLL_CONFIG_REFDIV_MASK) >> HORNET_PLL_CONFIG_REFDIV_SHIFT;
- outdiv = (pllreg & HORNET_PLL_CONFIG_OUTDIV_MASK) >> HORNET_PLL_CONFIG_OUTDIV_SHIFT;
-
- pll_freq = (ref_clock_rate / refdiv) * nint;
-
- if (outdiv == 1)
- pll_freq /= 2;
- else if (outdiv == 2)
- pll_freq /= 4;
- else if (outdiv == 3)
- pll_freq /= 8;
- else if (outdiv == 4)
- pll_freq /= 16;
- else if (outdiv == 5)
- pll_freq /= 32;
- else if (outdiv == 6)
- pll_freq /= 64;
- else if (outdiv == 7)
- pll_freq /= 128;
- else
- /* outdiv == 0 --> illegal value */
- pll_freq /= 2;
-
- cpu_div = (clockreg & HORNET_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_CPU_POST_DIV_SHIFT;
- ddr_div = (clockreg & HORNET_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_DDR_POST_DIV_SFIFT;
- ahb_div = (clockreg & HORNET_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_AHB_POST_DIV_SFIFT;
-
- /*
- * b00 : div by 1, b01 : div by 2, b10 : div by 3, b11 : div by 4
- */
- cpu_div++;
- ddr_div++;
- ahb_div++;
- }
+ // read CPU PLL Configuration register (CPU_PLL_CONFIG) value
+ cpu_config = ar7240_reg_rd(AR7240_CPU_PLL_CONFIG);
+
+ // REFDIV
+ t = (cpu_config & HORNET_PLL_CONFIG_REFDIV_MASK) >> HORNET_PLL_CONFIG_REFDIV_SHIFT;
+ freq = ref_rate / t;
+
+ // DIV_INT (multiplier)
+ t = (cpu_config & HORNET_PLL_CONFIG_NINT_MASK) >> HORNET_PLL_CONFIG_NINT_SHIFT;
+ freq *= t;
+
+ // OUTDIV
+ t = (cpu_config & HORNET_PLL_CONFIG_OUTDIV_MASK) >> HORNET_PLL_CONFIG_OUTDIV_SHIFT;
+ if(t == 0){ // value 0 is not allowed
+ t = 1;
+ }
- *cpu_freq = pll_freq / cpu_div;
- *ddr_freq = pll_freq / ddr_div;
- *ahb_freq = pll_freq / ahb_div;
+ freq >>= t;
+
+ // CPU clock divider
+ t = ((clock_ctrl & HORNET_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_CPU_POST_DIV_SHIFT) + 1;
+ *cpu_freq = freq / t;
+
+ // DDR clock divider
+ t = ((clock_ctrl & HORNET_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_DDR_POST_DIV_SFIFT) + 1;
+ *ddr_freq = freq / t;
+
+ // AHB clock divider
+ t = ((clock_ctrl & HORNET_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_AHB_POST_DIV_SFIFT) + 1;
+ *ahb_freq = freq / t;
+ }
}
int serial_init(void) {
u32 rdata;
u32 baudRateDivisor, clock_step;
u32 fcEnable = 0;
- u32 ahb_freq, ddr_freq, cpu_freq;
-
- ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
/* GPIO Configuration */
ar7240_reg_wr(AR7240_GPIO_OE, 0xcff);
#define HORNET_REV_ID_MASK 0xfff
#define AR9344_REV_ID_MASK 0xfff0 /* Ignore minor id */
#define HORNET_BOOTSTRAP_SEL_25M_40M_MASK 0x00000001 /* Hornet's bootstrap register */
-#define HORNET_BOOTSTRAP_MEM_TYPE_MASK 0x00003000 /* Hornet's bootstrap register */
+#define HORNET_BOOTSTRAP_MEM_TYPE_SHIFT 12
+#define HORNET_BOOTSTRAP_MEM_TYPE_MASK (0x3 << HORNET_BOOTSTRAP_MEM_TYPE_SHIFT) /* Hornet's bootstrap register */
#define HORNET_BOOTSTRAP_MDIO_SLAVE_MASK 0x00020000 /* Hornet's bootstrap register */
// WASP BootStrap Register
* Values written into CPU Phase Lock Loop Configuration (CPU_PLL_CONFIG)
*
* bits 10..15 (6bit) DIV_INT (The integer part of the DIV to CPU PLL) => 32 (0x20)
- * bits 16..20 (5bit) REFDIV (Reference clock divider) => 1 (0x1) [doesn't start at values different than 1 (maybe need to change other dividers?)]
- * bits 21 (1bit) RANGE (Determine the VCO frequency range of the CPU PLL) => 0 (0x0) [doesn't have impact on clock values]
- * bits 23..25 (3bit) OUTDIV (Define the ratio between VCO output and PLL output => 1 (0x1)
+ * bits 16..20 (5bit) REFDIV (Reference clock divider) => 1 (0x1) [doesn't start at values different than 1 (maybe need to change other dividers?)]
+ * bits 21 (1bit) RANGE (Determine the VCO frequency range of the CPU PLL) => 0 (0x0) [doesn't have impact on clock values]
+ * bits 23..25 (3bit) OUTDIV (Define the ratio between VCO output and PLL output => 1 (0x1) [value == 0 is illegal!]
* VCOOUT * (1/2^OUTDIV) = PLLOUT)
*/
/*
- * = PLL CALCULATION (guess) =============
- * PLL = (25 MHz * DIV_INT) / (2 ^ OUTDIV) // XTAL=25 MHz
+ * = PLL CALCULATION =============
+ * PLL = ((25 MHz / REFDIV) * DIV_INT) / (2 ^ OUTDIV) // XTAL=25 MHz
* OR
- * PLL = (40 MHz * DIV_INT) / (2 ^ OUTDIV) // XTAL=40 MHz
+ * PLL = ((40 MHz / REFDIV) * DIV_INT) / (2 ^ OUTDIV) // XTAL=40 MHz
*
* CPU = PLL / CPU_POST_DIV
* DDR = PLL / DDR_POST_DIV
extern void all_led_on(void);
extern void all_led_off(void);
+extern const char* print_mem_type(void);
+
+#if (BOARD == AP121)
+extern void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq);
+#endif
ulong monitor_flash_len;
#ifndef COMPRESSED_UBOOT
static int init_func_ram(void){
- puts("DRAM: ");
+ puts("DRAM: ");
if((gd->ram_size = initdram()) > 0){
- print_size (gd->ram_size, "\n");
-
+ print_size(gd->ram_size, print_mem_type());
+ puts("\n");
return(0);
}
// count ram size and print it
gd->ram_size = bootflag;
- puts("DRAM: ");
- print_size(gd->ram_size, "\n");
+ puts("DRAM: ");
+ print_size(gd->ram_size, print_mem_type());
+ puts("\n");
#endif
/*
int i;
char *s;
unsigned char buffer[6];
+#if (BOARD == AP121)
+ unsigned int ahb_freq, ddr_freq, cpu_freq;
+#endif
gd = id;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
/* configure available FLASH banks */
size = flash_init();
- puts("\n\n");
+#if (BOARD == AP121)
+ /* display clocks */
+ ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
+
+ // make MHz from Hz
+ cpu_freq /= 1000000;
+ ddr_freq /= 1000000;
+ ahb_freq /= 1000000;
+
+ printf("CLOCKS: %d/%d/%d MHz (CPU/RAM/AHB)\n", cpu_freq, ddr_freq, ahb_freq);
+#endif
+
+ puts("\n");
bd = gd->bd;
bd->bi_flashstart = CFG_FLASH_BASE;
projects / oweals / u-boot_mod.git / commitdiff