int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
- unsigned long reg1, unsigned long reg2);
+ unsigned long reg1, unsigned long reg2,
+ unsigned long reg3);
unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
unsigned long *reg1, unsigned long reg2,
unsigned long reg3);
/* Enable M4 */
#ifdef CONFIG_IMX8M
- call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
+ call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0);
#else
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
int arch_auxiliary_core_check_up(u32 core_id)
{
#ifdef CONFIG_IMX8M
- return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
+ return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0);
#else
unsigned int val;
#include <asm/arch/sys_proto.h>
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
- unsigned long reg1, unsigned long reg2)
+ unsigned long reg1, unsigned long reg2,
+ unsigned long reg3)
{
struct pt_regs regs;
regs.regs[1] = reg0;
regs.regs[2] = reg1;
regs.regs[3] = reg2;
+ regs.regs[4] = reg3;
smc_call(®s);
}
return call_imx_sip(FSL_SIP_OTP_WRITE, (unsigned long)word,
- (unsigned long)val, 0);
+ (unsigned long)val, 0, 0);
}
int fuse_override(u32 bank, u32 word, u32 val)
if (pdata->has_pd)
power_domain_on(&pdata->pd);
- call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 1);
+ call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+ pdata->resource_id, 1, 0);
return 0;
}
if (pdata->resource_id < 0)
return -EINVAL;
- call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 0);
+ call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+ pdata->resource_id, 0, 0);
if (pdata->has_pd)
power_domain_off(&pdata->pd);