sunxi: Fix PLL1 running at half speed on sun8i

PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index ad50dd90f3f62d8a526f22f9029bb5157484108f..d7a7040b72c70a27948841c038d4312b0cda46d2 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -97,6 +97,7 @@ void clock_set_pll1(unsigned int clk)
 {
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       const int p = 0;
        int k = 1;
        int m = 1;
 
@@ -113,8 +114,11 @@ void clock_set_pll1(unsigned int clk)
               CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
               &ccm->cpu_axi_cfg);
 
-       /* PLL1 rate = 24000000 * n * k / m */
-       writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
+       /*
+        * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
+        * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
+        */
+       writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
               CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
               CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
        sdelay(200);

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index f2119f30d108b353698b2b37aee7188ac7dd07e5..1beeff34ab2d340e921bec5d03f58b09cf25c9bf 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -173,7 +173,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL1_CTRL_M(n)             ((((n) - 1) & 0x3) << 0)
 #define CCM_PLL1_CTRL_K(n)             ((((n) - 1) & 0x3) << 4)
 #define CCM_PLL1_CTRL_N(n)             ((((n) - 1) & 0x1f) << 8)
-#define CCM_PLL1_CTRL_MAGIC            (0x1 << 16)
+#define CCM_PLL1_CTRL_P(n)             (((n) & 0x3) << 16)
 #define CCM_PLL1_CTRL_EN               (0x1 << 31)
 
 #define CCM_PLL3_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)