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powerpc/t2080: add serdes2 protocol 0x2e
author
Shengzhou Liu
<Shengzhou.Liu@freescale.com>
Mon, 27 Oct 2014 02:08:16 +0000
(10:08 +0800)
committer
York Sun
<yorksun@freescale.com>
Fri, 5 Dec 2014 16:06:07 +0000
(08:06 -0800)
Add serdes2 protocol 0x2e.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
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diff --git
a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index 7138bb4ef61cc92d6699d4335cac4ce2af3b37cd..c65f41d0f8e2accf79f3d0f528a0f5923d802948 100644
(file)
--- a/
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@
-169,6
+169,7
@@
static const struct serdes_config serdes2_cfg_tbl[] = {
{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
{0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} },
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },