config TARGET_MPC8536DS
bool "Support MPC8536DS"
+ select ARCH_MPC8536
config TARGET_MPC8540ADS
bool "Support MPC8540ADS"
config ARCH_C29X
bool
+config ARCH_MPC8536
+ bool
+
config ARCH_MPC8544
bool
# SoC specific SERDES support
obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
-obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
+obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
#define CONFIG_SYS_NUM_TLBCAMS 16
#endif
-#if defined(CONFIG_MPC8536)
+#if defined(CONFIG_ARCH_MPC8536)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#else
typedef struct ccsr_gur {
u32 porpllsr; /* POR PLL ratio status */
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
#elif defined(CONFIG_ARCH_C29X)
u8 res1[8];
u32 gpporcr; /* General-purpose POR configuration */
u8 res2[12];
-#if defined(CONFIG_MPC8536)
+#if defined(CONFIG_ARCH_MPC8536)
u32 gencfgr; /* General Configuration Register */
#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
#else
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
#define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
#else
#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8536 1
#define CONFIG_MPC8536DS 1
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
CONFIG_MPC83XX_GPIO_1_INIT_VALUE
CONFIG_MPC83XX_PCI2
CONFIG_MPC850
-CONFIG_MPC8536
CONFIG_MPC8536DS
CONFIG_MPC8540
CONFIG_MPC8540ADS