armv8/vexpress64: make multientry conditional

While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.

The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.

Make the single entry default and add a special
ARMV8_MULTIENTRY KConfig option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.

This makes the Juno platform start U-Boot properly.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 72e7981bbecb529fced91242c956bf6b67ce1921..b9ebee1046288e817034f0d30fbdc7e2ff1853ce 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -641,10 +641,12 @@ config TARGET_VEXPRESS64_JUNO
 config TARGET_LS2085A_EMU
        bool "Support ls2085a_emu"
        select ARM64
+       select ARMV8_MULTIENTRY
 
 config TARGET_LS2085A_SIMU
        bool "Support ls2085a_simu"
        select ARM64
+       select ARMV8_MULTIENTRY
 
 config TARGET_LS1021AQDS
        bool "Support ls1021aqds"
@@ -757,6 +759,8 @@ source "arch/arm/cpu/armv7/zynq/Kconfig"
 
 source "arch/arm/cpu/armv7/Kconfig"
 
+source "arch/arm/cpu/armv8/Kconfig"
+
 source "board/aristainetos/Kconfig"
 source "board/BuR/kwb/Kconfig"
 source "board/BuR/tseries/Kconfig"

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
new file mode 100644 (file)
index 0000000..4cd84b0
--- /dev/null
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -0,0 +1,6 @@
+if ARM64
+
+config ARMV8_MULTIENTRY
+        boolean "Enable multiple CPUs to enter into U-boot"
+
+endif

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4f22272cfa1766b0482ff8b1797e15db6e..df80a4e5fd9467cfd2224c5f9199db10bb2b6915 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -77,6 +77,7 @@ reset:
        /* Processor specific initialization */
        bl      lowlevel_init
 
+#ifdef CONFIG_ARMV8_MULTIENTRY
        branch_if_master x0, x1, master_cpu
 
        /*
@@ -88,11 +89,10 @@ slave_cpu:
        ldr     x0, [x1]
        cbz     x0, slave_cpu
        br      x0                      /* branch to the given address */
-
-       /*
-        * Master CPU
-        */
 master_cpu:
+       /* On the master CPU */
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
        bl      _main
 
 /*-----------------------------------------------------------------------*/
@@ -100,6 +100,15 @@ master_cpu:
 WEAK(lowlevel_init)
        mov     x29, lr                 /* Save LR */
 
+#ifndef CONFIG_ARMV8_MULTIENTRY
+       /*
+        * For single-entry systems the lowlevel init is very simple.
+        */
+       ldr     x0, =GICD_BASE
+       bl      gic_init_secure
+
+#else /* CONFIG_ARMV8_MULTIENTRY is set */
+
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
        branch_if_slave x0, 1f
        ldr     x0, =GICD_BASE
@@ -137,6 +146,8 @@ WEAK(lowlevel_init)
        bl      armv8_switch_to_el1
 #endif
 
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
 2:
        mov     lr, x29                 /* Restore LR */
        ret

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1c8c4251ee0cedde2a24d459be2109b9a1df749f..3b3146ab2239929544784c8bf3944ab0d8d60ba8 100644 (file)
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -78,6 +78,8 @@ lr    .req    x30
  * choose processor with all zero affinity value as the master.
  */
 .macro branch_if_slave, xreg, slave_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+       /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
        mrs     \xreg, mpidr_el1
        tst     \xreg, #0xff            /* Test Affinity 0 */
        b.ne    \slave_label
@@ -90,6 +92,7 @@ lr    .req    x30
        lsr     \xreg, \xreg, #16
        tst     \xreg, #0xff            /* Test Affinity 3 */
        b.ne    \slave_label
+#endif
 .endm
 
 /*
@@ -97,12 +100,17 @@ lr .req    x30
  * choose processor with all zero affinity value as the master.
  */
 .macro branch_if_master, xreg1, xreg2, master_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+       /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
        mrs     \xreg1, mpidr_el1
        lsr     \xreg2, \xreg1, #32
        lsl     \xreg1, \xreg1, #40
        lsr     \xreg1, \xreg1, #40
        orr     \xreg1, \xreg1, \xreg2
        cbz     \xreg1, \master_label
+#else
+       b       \master_label
+#endif
 .endm
 
 .macro armv8_switch_to_el2_m, xreg1

diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 20db81222e796b80ca2d988b377457807b05ced1..de6286435d97096e064c6220546046ff31c6b77c 100644 (file)
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -22,12 +22,6 @@ int board_init(void)
 
 int dram_init(void)
 {
-       /*
-        * Clear spin table so that secondary processors
-        * observe the correct value after waken up from wfe.
-        */
-       *(unsigned long *)CPU_RELEASE_ADDR = 0;
-
        gd->ram_size = PHYS_SDRAM_1_SIZE;
        return 0;
 }

diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index e6cd8819dd40a64c34b6bbc9b3a3afaf497f975e..810eef12deb107740463733f99b344c2edbc3480 100644 (file)
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -54,13 +54,6 @@
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_LIBFDT
 
-/* SMP Spin Table Definitions */
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
-#define CPU_RELEASE_ADDR               (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
-#else
-#define CPU_RELEASE_ADDR               (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#endif
-
 /* CS register bases for the original memory map. */
 #define V2M_PA_CS0                     0x00000000
 #define V2M_PA_CS1                     0x14000000