ddr: marvell: a38x: Allow boards to specify CK_DELAY parameter
authorChris Packham <judge.packham@gmail.com>
Wed, 29 Jan 2020 23:50:44 +0000 (12:50 +1300)
committerStefan Roese <sr@denx.de>
Tue, 14 Apr 2020 06:59:44 +0000 (08:59 +0200)
For some layouts it is necessary to adjust the CK_DELAY parameter to
successfully complete DDR training. Add the ability to specify the
CK_DELAY in the mv_ddr_topology_map.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
board/alliedtelesis/x530/x530.c
drivers/ddr/marvell/a38x/ddr3_init.c
drivers/ddr/marvell/a38x/ddr_topology_def.h
drivers/ddr/marvell/a38x/mv_ddr_topology.c
drivers/ddr/marvell/a38x/mv_ddr_topology.h

index e0fa8067c1c58f80bb4bc0f3bf09d8de2f8cb7d9..04b053dc20e4d7f7d105cd62d3646805f5be995c 100644 (file)
@@ -66,7 +66,11 @@ static struct mv_ddr_topology_map board_topology_map = {
        BUS_MASK_32BIT_ECC,             /* subphys mask */
        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
        { {0} },                        /* raw spd data */
-       {0}                             /* timing parameters */
+       {0},                            /* timing parameters */
+       { {0} },                        /* electrical configuration */
+       {0},                            /* electrical parameters */
+       0,                              /* Clock enable mask */
+       160                             /* Clock delay */
 };
 
 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
index 22c8f9ca54e589bd0cf2e4ccbcfa8355b0bfd183..a971cc155a01cf52fd48260b4267701038a19b6f 100644 (file)
@@ -106,8 +106,10 @@ static int mv_ddr_training_params_set(u8 dev_num)
        struct tune_train_params params;
        int status;
        u32 cs_num;
+       int ck_delay;
 
        cs_num = mv_ddr_cs_num_get();
+       ck_delay = mv_ddr_ck_delay_get();
 
        /* NOTE: do not remove any field initilization */
        params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
@@ -131,6 +133,9 @@ static int mv_ddr_training_params_set(u8 dev_num)
                params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
        }
 
+       if (ck_delay > 0)
+               params.ck_delay = ck_delay;
+
        status = ddr3_tip_tune_training_params(dev_num, &params);
        if (MV_OK != status) {
                printf("%s Training Sequence - FAILED\n", ddr_type);
index 950f296ff9841236a3ac788e1ea0ac2df1003803..34196b16628750c750b97723e2616ed4bff7fafc 100644 (file)
@@ -127,6 +127,9 @@ struct mv_ddr_topology_map {
 
        /* Clock enable mask */
        u32 clk_enable;
+
+       /* Clock delay */
+       int ck_delay;
 };
 
 enum mv_ddr_iface_mode {
index ef3b658a7899d59e9063676d95dd2d564dc69f75..09840b1e70f147125a1e9f9f869a3072537f0324 100644 (file)
@@ -229,6 +229,16 @@ int mv_ddr_is_ecc_ena(void)
                return 0;
 }
 
+int mv_ddr_ck_delay_get(void)
+{
+       struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+       if (tm->ck_delay)
+               return tm->ck_delay;
+
+       return -1;
+}
+
 /* translate topology map definition to real memory size in bits */
 static unsigned int mem_size[] = {
        ADDR_SIZE_512MB,
index 766f25db5733019850ce074fb3443dac699b1b90..4fca47689f1103d4bb8ed25d4cf5b713dac64d83 100644 (file)
@@ -319,6 +319,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void);
 unsigned int mv_ddr_if_bus_width_get(void);
 unsigned int mv_ddr_cs_num_get(void);
 int mv_ddr_is_ecc_ena(void);
+int mv_ddr_ck_delay_get(void);
 unsigned long long mv_ddr_mem_sz_per_cs_get(void);
 unsigned long long mv_ddr_mem_sz_get(void);
 unsigned int mv_ddr_rtt_nom_get(void);