BUS_MASK_32BIT_ECC, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { {0} }, /* electrical configuration */
+ {0}, /* electrical parameters */
+ 0, /* Clock enable mask */
+ 160 /* Clock delay */
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
struct tune_train_params params;
int status;
u32 cs_num;
+ int ck_delay;
cs_num = mv_ddr_cs_num_get();
+ ck_delay = mv_ddr_ck_delay_get();
/* NOTE: do not remove any field initilization */
params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
}
+ if (ck_delay > 0)
+ params.ck_delay = ck_delay;
+
status = ddr3_tip_tune_training_params(dev_num, ¶ms);
if (MV_OK != status) {
printf("%s Training Sequence - FAILED\n", ddr_type);
/* Clock enable mask */
u32 clk_enable;
+
+ /* Clock delay */
+ int ck_delay;
};
enum mv_ddr_iface_mode {
return 0;
}
+int mv_ddr_ck_delay_get(void)
+{
+ struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+ if (tm->ck_delay)
+ return tm->ck_delay;
+
+ return -1;
+}
+
/* translate topology map definition to real memory size in bits */
static unsigned int mem_size[] = {
ADDR_SIZE_512MB,
unsigned int mv_ddr_if_bus_width_get(void);
unsigned int mv_ddr_cs_num_get(void);
int mv_ddr_is_ecc_ena(void);
+int mv_ddr_ck_delay_get(void);
unsigned long long mv_ddr_mem_sz_per_cs_get(void);
unsigned long long mv_ddr_mem_sz_get(void);
unsigned int mv_ddr_rtt_nom_get(void);