mpc83xx: MVBLM7: minor build fixups

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/board/mvblm7/pci.c b/board/mvblm7/pci.c
index 49fe921dcc9bb3506e35b058b85bce694b56d65a..ef34a6b453e292a99a6ca4d3332a99985fba2b6d 100644 (file)
--- a/board/mvblm7/pci.c
+++ b/board/mvblm7/pci.c
@@ -29,44 +29,12 @@
 #endif
 #include <pci.h>
 #include <mpc83xx.h>
+#include <fpga.h>
 #include "mvblm7.h"
+#include "fpga.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS        CFG_SDRAM_BASE
-
-#define SLOT0_IRQ      3
-#define SLOT1_IRQ      4
-void pci_mvblm7_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-       unsigned char line = 0xff;
-
-       if (PCI_BUS(dev) == 0) {
-               switch (PCI_DEV(dev)) {
-               case 0x0:
-                       return;
-               case 0xb:
-                       line = 0;
-                       break;
-               case 0xc:
-                       line = 1;
-                       break;
-               default:
-                       printf("***pci_scan: illegal dev = 0x%08x\n",
-                               PCI_DEV(dev));
-                       line = 0xff;
-                       break;
-               }
-               pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
-       }
-}
-
-static struct pci_controller pci_hose = {
-       fixup_irq:pci_mvblm7_fixup_irq
-};
-
 int mvblm7_load_fpga(void)
 {
        size_t data_size = 0;

diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 658433f906bae7eaef7471fceea80ad53f061f8f..349ca14bbaf869953a0ed546cd3b292ceaea8035 100644 (file)
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -118,7 +118,7 @@
 
 #define CFG_BR0_PRELIM         (CFG_FLASH_BASE | BR_PS_16 | BR_V)
 #define CFG_OR0_PRELIM         ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM |  \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS|\
+                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
                                OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
                                OR_GPCM_EAD)
 #define CFG_LBLAWBAR0_PRELIM   CFG_FLASH_BASE