ppc4xx: Flush dcache after DDR2 autocalibration with caches on
authorStefan Roese <sr@denx.de>
Fri, 16 Sep 2011 10:54:58 +0000 (12:54 +0200)
committerStefan Roese <sr@denx.de>
Mon, 19 Sep 2011 09:51:21 +0000 (11:51 +0200)
Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux (as seen on ICON-440SPe).

Signed-off-by: Stefan Roese <sr@denx.de>
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

index 95df1d94c4713c8878eb3a8f504da665a6dfc2c4..4a2f33744d4eb4d799c214f33931e67429b5060c 100644 (file)
@@ -656,6 +656,13 @@ phys_size_t initdram(int board_type)
        program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 #endif
 
+       /*
+        * Flush the dcache before removing the TLB with caches
+        * enabled. Otherwise this might lead to problems later on,
+        * e.g. while booting Linux (as seen on ICON-440SPe).
+        */
+       flush_dcache();
+
        /*
         * Now after initialization (auto-calibration and ECC generation)
         * remove the TLB entries with caches enabled and program again with