arm64: zynqmp: Sync zynqmp fpga manager with mainline

Sync zynqmp fpga manager with mainline.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 1098e890192c8855a0a5a7beffc3b9d2099f9f2d..0b0fb6e9878880c3d2fe5093054a76e965a67561 100644 (file)
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -291,3 +291,7 @@
 &xlnx_dp_snd_codec0 {
        clocks = <&zynqmp_clk DP_AUDIO_REF>;
 };
+
+&zynqmp_pcap {
+       clocks = <&zynqmp_clk PCAP>;
+};

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index ec0dd73e1504a6158546645ca99e61999c43c928..58ac62c4f851fc8097b104c9f43286f03dcf4895 100644 (file)
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -149,6 +149,11 @@
                        #power-domain-cells = <0x1>;
                        u-boot,dm-pre-reloc;
 
+                       zynqmp_pcap: pcap {
+                               compatible = "xlnx,zynqmp-pcap-fpga";
+                               clock-names = "ref_clk";
+                       };
+
                        zynqmp_power: zynqmp-power {
                                u-boot,dm-pre-reloc;
                                compatible = "xlnx,zynqmp-power";
@@ -180,9 +185,10 @@
 
        fpga_full: fpga-full {
                compatible = "fpga-region";
-               fpga-mgr = <&pcap>;
+               fpga-mgr = <&zynqmp_pcap>;
                #address-cells = <2>;
                #size-cells = <2>;
+               ranges;
        };
 
        nvmem_firmware {
@@ -195,10 +201,6 @@
                };
        };
 
-       pcap: pcap {
-               compatible = "xlnx,zynqmp-pcap-fpga";
-       };
-
        rst: reset-controller {
                compatible = "xlnx,zynqmp-reset";
                #reset-cells = <1>;