sunxi: Group cpu core related controls together

Instead of listing individual registers for controls to each processor
core, list them as an array of registers. This makes accessing controls
by core index easier.

Also rename "cpucfg_sun6i.h" (which was unused anyway) to the more generic
"cpucfg.h", and add packed attribute to struct sunxi_cpucfg.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h
new file mode 100644 (file)
index 0000000..f6d2f21
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -0,0 +1,63 @@
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPUCFG_H
+#define _SUNXI_CPUCFG_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#ifndef __ASSEMBLY__
+
+struct __packed sunxi_cpucfg_cpu {
+       u32 rst;                /* base + 0x0 */
+       u32 ctrl;               /* base + 0x4 */
+       u32 status;             /* base + 0x8 */
+       u8 res[0x34];           /* base + 0xc */
+};
+
+struct __packed sunxi_cpucfg_reg {
+       u8 res0[0x40];          /* 0x000 */
+       struct sunxi_cpucfg_cpu cpu[4];         /* 0x040 */
+       u8 res1[0x44];          /* 0x140 */
+       u32 gen_ctrl;           /* 0x184 */
+       u32 l2_status;          /* 0x188 */
+       u8 res2[0x4];           /* 0x18c */
+       u32 event_in;           /* 0x190 */
+       u8 res3[0xc];           /* 0x194 */
+       u32 super_standy_flag;  /* 0x1a0 */
+       u32 priv0;              /* 0x1a4 */
+       u32 priv1;              /* 0x1a8 */
+       u8 res4[0x54];          /* 0x1ac */
+       u32 idle_cnt0_low;      /* 0x200 */
+       u32 idle_cnt0_high;     /* 0x204 */
+       u32 idle_cnt0_ctrl;     /* 0x208 */
+       u8 res8[0x4];           /* 0x20c */
+       u32 idle_cnt1_low;      /* 0x210 */
+       u32 idle_cnt1_high;     /* 0x214 */
+       u32 idle_cnt1_ctrl;     /* 0x218 */
+       u8 res9[0x4];           /* 0x21c */
+       u32 idle_cnt2_low;      /* 0x220 */
+       u32 idle_cnt2_high;     /* 0x224 */
+       u32 idle_cnt2_ctrl;     /* 0x228 */
+       u8 res10[0x4];          /* 0x22c */
+       u32 idle_cnt3_low;      /* 0x230 */
+       u32 idle_cnt3_high;     /* 0x234 */
+       u32 idle_cnt3_ctrl;     /* 0x238 */
+       u8 res11[0x4];          /* 0x23c */
+       u32 idle_cnt4_low;      /* 0x240 */
+       u32 idle_cnt4_high;     /* 0x244 */
+       u32 idle_cnt4_ctrl;     /* 0x248 */
+       u8 res12[0x34];         /* 0x24c */
+       u32 cnt64_ctrl;         /* 0x280 */
+       u32 cnt64_low;          /* 0x284 */
+       u32 cnt64_high;         /* 0x288 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_H */

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
deleted file mode 100644 (file)
index 6885a97..0000000
--- a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Sunxi A31 CPUCFG register definition.
- *
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef _SUNXI_CPUCFG_H
-#define _SUNXI_CPUCFG_H
-
-#include <linux/types.h>
-
-#ifndef __ASSEMBLY__
-
-struct sunxi_cpucfg_reg {
-       u8 res0[0x40];          /* 0x000 */
-       u32 cpu0_rst;           /* 0x040 */
-       u32 cpu0_ctrl;          /* 0x044 */
-       u32 cpu0_status;        /* 0x048 */
-       u8 res1[0x34];          /* 0x04c */
-       u32 cpu1_rst;           /* 0x080 */
-       u32 cpu1_ctrl;          /* 0x084 */
-       u32 cpu1_status;        /* 0x088 */
-       u8 res2[0x34];          /* 0x08c */
-       u32 cpu2_rst;           /* 0x0c0 */
-       u32 cpu2_ctrl;          /* 0x0c4 */
-       u32 cpu2_status;        /* 0x0c8 */
-       u8 res3[0x34];          /* 0x0cc */
-       u32 cpu3_rst;           /* 0x100 */
-       u32 cpu3_ctrl;          /* 0x104 */
-       u32 cpu3_status;        /* 0x108 */
-       u8 res4[0x78];          /* 0x10c */
-       u32 gen_ctrl;           /* 0x184 */
-       u32 l2_status;          /* 0x188 */
-       u8 res5[0x4];           /* 0x18c */
-       u32 event_in;           /* 0x190 */
-       u8 res6[0xc];           /* 0x194 */
-       u32 super_standy_flag;  /* 0x1a0 */
-       u32 priv0;              /* 0x1a4 */
-       u32 priv1;              /* 0x1a8 */
-       u8 res7[0x54];          /* 0x1ac */
-       u32 idle_cnt0_low;      /* 0x200 */
-       u32 idle_cnt0_high;     /* 0x204 */
-       u32 idle_cnt0_ctrl;     /* 0x208 */
-       u8 res8[0x4];           /* 0x20c */
-       u32 idle_cnt1_low;      /* 0x210 */
-       u32 idle_cnt1_high;     /* 0x214 */
-       u32 idle_cnt1_ctrl;     /* 0x218 */
-       u8 res9[0x4];           /* 0x21c */
-       u32 idle_cnt2_low;      /* 0x220 */
-       u32 idle_cnt2_high;     /* 0x224 */
-       u32 idle_cnt2_ctrl;     /* 0x228 */
-       u8 res10[0x4];          /* 0x22c */
-       u32 idle_cnt3_low;      /* 0x230 */
-       u32 idle_cnt3_high;     /* 0x234 */
-       u32 idle_cnt3_ctrl;     /* 0x238 */
-       u8 res11[0x4];          /* 0x23c */
-       u32 idle_cnt4_low;      /* 0x240 */
-       u32 idle_cnt4_high;     /* 0x244 */
-       u32 idle_cnt4_ctrl;     /* 0x248 */
-       u8 res12[0x34];         /* 0x24c */
-       u32 cnt64_ctrl;         /* 0x280 */
-       u32 cnt64_low;          /* 0x284 */
-       u32 cnt64_high;         /* 0x288 */
-};
-
-#endif /* __ASSEMBLY__ */
-#endif /* _SUNXI_CPUCFG_H */

diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 34e01e825df2ce7174b75272227de81a3cd687ba..ae3880b13bdfed19a1a3b0a700ddc76b6b31cfd3 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -227,10 +227,8 @@ struct __packed sunxi_prcm_reg {
        u32 gpu_pwroff;         /* 0x118 */
        u8 res9[0x4];           /* 0x11c */
        u32 vdd_pwr_reset;      /* 0x120 */
-       u8 res10[0x20];         /* 0x124 */
-       u32 cpu1_pwr_clamp;     /* 0x144 */
-       u32 cpu2_pwr_clamp;     /* 0x148 */
-       u32 cpu3_pwr_clamp;     /* 0x14c */
+       u8 res10[0x1c];         /* 0x124 */
+       u32 cpu_pwr_clamp[4];   /* 0x140 but first one is actually unused */
        u8 res11[0x30];         /* 0x150 */
        u32 dram_pwr;           /* 0x180 */
        u8 res12[0xc];          /* 0x184 */