am33xx:ddr:Fix config_sdram to work for all DDR

The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.

Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
           Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 448cc4015766215ca9aeee645db332aacb668cde..7932a39e7c2da2906f44f7f6b405b962be4914d0 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -54,10 +54,13 @@ void config_sdram(const struct emif_regs *regs)
                writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
                writel(regs->zq_config, &emif_reg->emif_zq_config);
                writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+               writel(regs->sdram_config, &emif_reg->emif_sdram_config);
+               writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+               writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
        }
-       writel(regs->sdram_config, &emif_reg->emif_sdram_config);
        writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
        writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+       writel(regs->sdram_config, &emif_reg->emif_sdram_config);
 }
 
 /**