Initial revision

diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c
new file mode 100644 (file)
index 0000000..8a6915f
--- /dev/null
+++ b/cpu/74xx_7xx/cpu.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * cpu.c
+ *
+ * CPU specific code
+ *
+ * written or collected and sometimes rewritten by
+ * Magnus Damm <damm@bitsmart.com>
+ *
+ * minor modifications by
+ * Wolfgang Denk <wd@denx.de>
+ *
+ * more modifications by
+ * Josh Huber <huber@mclx.com>
+ * added support for the 74xx series of cpus
+ * added support for the 7xx series of cpus
+ * made the code a little less hard-coded, and more auto-detectish
+ */
+
+#include <common.h>
+#include <command.h>
+#include <74xx_7xx.h>
+#include <asm/cache.h>
+
+cpu_t
+get_cpu_type(void)
+{
+       uint pvr = get_pvr();
+       cpu_t type;
+
+       type = CPU_UNKNOWN;
+
+       switch (PVR_VER(pvr)) {
+       case 0x000c:
+               type = CPU_7400;
+               break;
+       case 0x0008:
+               type = CPU_750;
+
+                if (((pvr >> 8) & 0xff) == 0x01) {
+                       type = CPU_750CX;       /* old CX (80100 and 8010x?)*/
+               } else if (((pvr >> 8) & 0xff) == 0x22) {
+                       type = CPU_750CX;       /* CX (82201,82202) and CXe (82214) */
+               } else if (((pvr >> 8) & 0xff) == 0x33) {
+                       type = CPU_750CX;       /* CXe (83311) */
+               } else if (((pvr >> 12) & 0xF) == 0x3) {
+                       type = CPU_755;
+                }
+               break;
+
+       case 0x800C:
+               type = CPU_7410;
+               break;
+
+        case 0x8000:
+               type = CPU_7450;
+               break;
+
+       default:
+               break;
+       }
+
+       return type;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if !defined(CONFIG_BAB7xx)
+int checkcpu (void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       uint type   = get_cpu_type();
+       uint pvr    = get_pvr();
+       ulong clock = gd->cpu_clk;
+       char buf[32];
+       char *str;
+
+       puts ("CPU:   ");
+
+       switch (type) {
+       case CPU_750CX:
+               printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"",
+                       (pvr>>8) & 0xf,
+                       pvr & 0xf);
+               goto    PR_CLK;
+
+       case CPU_750:
+               str = "750";
+               break;
+
+       case CPU_755:
+               str = "755";
+               break;
+
+       case CPU_7400:
+               str = "MPC7400";
+               break;
+
+        case CPU_7410:
+                str = "MPC7410";
+               break;
+
+        case CPU_7450:
+                str = "MPC7450";
+               break;
+
+       default:
+                printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
+               return -1;
+       }
+
+       printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF);
+PR_CLK:
+       printf (" @ %s MHz\n", strmhz(buf, clock));
+
+       return (0);
+}
+#endif
+/* these two functions are unimplemented currently [josh] */
+
+/* ------------------------------------------------------------------------- */
+/* L1 i-cache                                                                */
+
+int
+checkicache(void)
+{
+       return 0; /* XXX */
+}
+
+/* ------------------------------------------------------------------------- */
+/* L1 d-cache                                                                */
+
+int
+checkdcache(void)
+{
+       return 0; /* XXX */
+}
+
+/* ------------------------------------------------------------------------- */
+
+static inline void
+soft_restart(unsigned long addr)
+{
+       /* SRR0 has system reset vector, SRR1 has default MSR value */
+       /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
+
+       __asm__ __volatile__ ("mtspr    26, %0"         :: "r" (addr));
+       __asm__ __volatile__ ("li       4, (1 << 6)"    ::: "r4");
+       __asm__ __volatile__ ("mtspr    27, 4");
+       __asm__ __volatile__ ("rfi");
+
+       while(1);       /* not reached */
+}
+
+
+#if !defined(CONFIG_PCIPPC2) && \
+    !defined(CONFIG_BAB7xx)  && \
+    !defined(CONFIG_ELPPC)
+/* no generic way to do board reset. simply call soft_reset. */
+void
+do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+       ulong addr;
+       /* flush and disable I/D cache */
+       __asm__ __volatile__ ("mfspr    3, 1008"        ::: "r3");
+       __asm__ __volatile__ ("ori      5, 5, 0xcc00"   ::: "r5");
+       __asm__ __volatile__ ("ori      4, 3, 0xc00"    ::: "r4");
+       __asm__ __volatile__ ("andc     5, 3, 5"        ::: "r5");
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("mtspr    1008, 4");
+       __asm__ __volatile__ ("isync");
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("mtspr    1008, 5");
+       __asm__ __volatile__ ("isync");
+       __asm__ __volatile__ ("sync");
+
+#ifdef CFG_RESET_ADDRESS
+       addr = CFG_RESET_ADDRESS;
+#else
+       /*
+        * note: when CFG_MONITOR_BASE points to a RAM address,
+        * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+        * address. Better pick an address known to be invalid on your
+        * system and assign it to CFG_RESET_ADDRESS.
+        */
+       addr = CFG_MONITOR_BASE - sizeof (ulong);
+#endif
+       soft_restart(addr);
+       while(1);       /* not reached */
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
+ */
+unsigned long
+get_tbclk (void)
+{
+       return CFG_BUS_HZ / 4;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
+void
+watchdog_reset(void)
+{
+
+}
+#endif  /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
+#endif /* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */

diff --git a/drivers/eepro100.c b/drivers/eepro100.c
new file mode 100644 (file)
index 0000000..c8d07de
--- /dev/null
+++ b/drivers/eepro100.c
@@ -0,0 +1,820 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#undef DEBUG
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
+       defined(CONFIG_EEPRO100)
+
+       /* Ethernet chip registers.
+        */
+#define SCBStatus              0       /* Rx/Command Unit Status *Word* */
+#define SCBIntAckByte          1       /* Rx/Command Unit STAT/ACK byte */
+#define SCBCmd                 2       /* Rx/Command Unit Command *Word* */
+#define SCBIntrCtlByte         3       /* Rx/Command Unit Intr.Control Byte */
+#define SCBPointer             4       /* General purpose pointer. */
+#define SCBPort                8       /* Misc. commands and operands. */
+#define SCBflash               12      /* Flash memory control. */
+#define SCBeeprom              14      /* EEPROM memory control. */
+#define SCBCtrlMDI             16      /* MDI interface control. */
+#define SCBEarlyRx             20      /* Early receive byte count. */
+#define SCBGenControl          28      /* 82559 General Control Register */
+#define SCBGenStatus           29      /* 82559 General Status register */
+
+       /* 82559 SCB status word defnitions
+        */
+#define SCB_STATUS_CX          0x8000  /* CU finished command (transmit) */
+#define SCB_STATUS_FR          0x4000  /* frame received */
+#define SCB_STATUS_CNA         0x2000  /* CU left active state */
+#define SCB_STATUS_RNR         0x1000  /* receiver left ready state */
+#define SCB_STATUS_MDI         0x0800  /* MDI read/write cycle done */
+#define SCB_STATUS_SWI         0x0400  /* software generated interrupt */
+#define SCB_STATUS_FCP         0x0100  /* flow control pause interrupt */
+
+#define SCB_INTACK_MASK        0xFD00  /* all the above */
+
+#define SCB_INTACK_TX          (SCB_STATUS_CX | SCB_STATUS_CNA)
+#define SCB_INTACK_RX          (SCB_STATUS_FR | SCB_STATUS_RNR)
+
+       /* System control block commands
+        */
+/* CU Commands */
+#define CU_NOP                 0x0000
+#define        CU_START                0x0010
+#define        CU_RESUME               0x0020
+#define        CU_STATSADDR            0x0040  /* Load Dump Statistics ctrs addr */
+#define        CU_SHOWSTATS            0x0050  /* Dump statistics counters. */
+#define        CU_ADDR_LOAD            0x0060  /* Base address to add to CU commands */
+#define        CU_DUMPSTATS            0x0070  /* Dump then reset stats counters. */
+
+/* RUC Commands */
+#define RUC_NOP                0x0000
+#define        RUC_START               0x0001
+#define        RUC_RESUME              0x0002
+#define RUC_ABORT              0x0004
+#define        RUC_ADDR_LOAD           0x0006  /* (seems not to clear on acceptance) */
+#define RUC_RESUMENR           0x0007
+
+#define CU_CMD_MASK            0x00f0
+#define RU_CMD_MASK            0x0007
+
+#define SCB_M                  0x0100  /* 0 = enable interrupt, 1 = disable */
+#define SCB_SWI                0x0200  /* 1 - cause device to interrupt */
+
+#define CU_STATUS_MASK         0x00C0
+#define RU_STATUS_MASK         0x003C
+
+#define RU_STATUS_IDLE         (0<<2)
+#define RU_STATUS_SUS          (1<<2)
+#define RU_STATUS_NORES        (2<<2)
+#define RU_STATUS_READY        (4<<2)
+#define RU_STATUS_NO_RBDS_SUS   ((1<<2)|(8<<2))
+#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
+#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
+
+       /* 82559 Port interface commands.
+        */
+#define I82559_RESET           0x00000000      /* Software reset */
+#define I82559_SELFTEST                0x00000001      /* 82559 Selftest command */
+#define I82559_SELECTIVE_RESET 0x00000002
+#define I82559_DUMP            0x00000003
+#define I82559_DUMP_WAKEUP     0x00000007
+
+       /* 82559 Eeprom interface.
+        */
+#define EE_SHIFT_CLK           0x01    /* EEPROM shift clock. */
+#define EE_CS                  0x02    /* EEPROM chip select. */
+#define EE_DATA_WRITE          0x04    /* EEPROM chip data in. */
+#define EE_WRITE_0             0x01
+#define EE_WRITE_1             0x05
+#define EE_DATA_READ           0x08    /* EEPROM chip data out. */
+#define EE_ENB                 (0x4800 | EE_CS)
+#define EE_CMD_BITS            3
+#define EE_DATA_BITS           16
+
+       /* The EEPROM commands include the alway-set leading bit.
+        */
+#define EE_EWENB_CMD           (4 << addr_len)
+#define EE_WRITE_CMD           (5 << addr_len)
+#define EE_READ_CMD            (6 << addr_len)
+#define EE_ERASE_CMD           (7 << addr_len)
+
+       /* Receive frame descriptors.
+        */
+struct RxFD {
+       volatile u16 status;
+       volatile u16 control;
+       volatile u32 link;              /* struct RxFD * */
+       volatile u32 rx_buf_addr;       /* void * */
+       volatile u32 count;
+
+       volatile u8 data[PKTSIZE_ALIGN];
+};
+
+#define RFD_STATUS_C           0x8000  /* completion of received frame */
+#define RFD_STATUS_OK          0x2000  /* frame received with no errors */
+
+#define RFD_CONTROL_EL         0x8000  /* 1=last RFD in RFA */
+#define RFD_CONTROL_S          0x4000  /* 1=suspend RU after receiving frame */
+#define RFD_CONTROL_H          0x0010  /* 1=RFD is a header RFD */
+#define RFD_CONTROL_SF         0x0008  /* 0=simplified, 1=flexible mode */
+
+#define RFD_COUNT_MASK         0x3fff
+#define RFD_COUNT_F            0x4000
+#define RFD_COUNT_EOF          0x8000
+
+#define RFD_RX_CRC             0x0800  /* crc error */
+#define RFD_RX_ALIGNMENT       0x0400  /* alignment error */
+#define RFD_RX_RESOURCE        0x0200  /* out of space, no resources */
+#define RFD_RX_DMA_OVER        0x0100  /* DMA overrun */
+#define RFD_RX_SHORT           0x0080  /* short frame error */
+#define RFD_RX_LENGTH          0x0020
+#define RFD_RX_ERROR           0x0010  /* receive error */
+#define RFD_RX_NO_ADR_MATCH    0x0004  /* no address match */
+#define RFD_RX_IA_MATCH        0x0002  /* individual address does not match */
+#define RFD_RX_TCO             0x0001  /* TCO indication */
+
+       /* Transmit frame descriptors
+        */
+struct TxFD {                          /* Transmit frame descriptor set. */
+       volatile u16 status;
+       volatile u16 command;
+       volatile u32 link;              /* void * */
+       volatile u32 tx_desc_addr;      /* Always points to the tx_buf_addr element. */
+       volatile s32 count;
+
+       volatile u32 tx_buf_addr0;      /* void *, frame to be transmitted.  */
+       volatile s32 tx_buf_size0;      /* Length of Tx frame. */
+       volatile u32 tx_buf_addr1;      /* void *, frame to be transmitted.  */
+       volatile s32 tx_buf_size1;      /* Length of Tx frame. */
+};
+
+#define TxCB_CMD_TRANSMIT      0x0004  /* transmit command */
+#define TxCB_CMD_SF            0x0008  /* 0=simplified, 1=flexible mode */
+#define TxCB_CMD_NC            0x0010  /* 0=CRC insert by controller */
+#define TxCB_CMD_I             0x2000  /* generate interrupt on completion */
+#define TxCB_CMD_S             0x4000  /* suspend on completion */
+#define TxCB_CMD_EL            0x8000  /* last command block in CBL */
+
+#define TxCB_COUNT_MASK        0x3fff
+#define TxCB_COUNT_EOF         0x8000
+
+       /* The Speedo3 Rx and Tx frame/buffer descriptors.
+        */
+struct descriptor {                    /* A generic descriptor. */
+       volatile u16 status;
+       volatile u16 command;
+       volatile u32 link;              /* struct descriptor *  */
+
+       unsigned char params[0];
+};
+
+#define CFG_CMD_EL             0x8000
+#define CFG_CMD_SUSPEND        0x4000
+#define CFG_CMD_INT            0x2000
+#define CFG_CMD_IAS            0x0001  /* individual address setup */
+#define CFG_CMD_CONFIGURE      0x0002  /* configure */
+
+#define CFG_STATUS_C           0x8000
+#define CFG_STATUS_OK          0x2000
+
+       /* Misc.
+        */
+#define NUM_RX_DESC            PKTBUFSRX
+#define NUM_TX_DESC            1       /* Number of TX descriptors   */
+
+#define TOUT_LOOP              1000000
+
+#define ETH_ALEN               6
+
+static struct RxFD rx_ring[NUM_RX_DESC];       /* RX descriptor ring         */
+static struct TxFD tx_ring[NUM_TX_DESC];       /* TX descriptor ring         */
+static int rx_next;                    /* RX descriptor ring pointer */
+static int tx_next;                    /* TX descriptor ring pointer */
+static int tx_threshold;
+
+/*
+ * The parameters for a CmdConfigure operation.
+ * There are so many options that it would be difficult to document
+ * each bit. We mostly use the default or recommended settings.
+ */
+static const char i82557_config_cmd[] = {
+       22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1,    /* 1=Use MII  0=Use AUI */
+       0, 0x2E, 0, 0x60, 0,
+       0xf2, 0x48, 0, 0x40, 0xf2, 0x80,        /* 0x40=Force full-duplex */
+       0x3f, 0x05,
+};
+static const char i82558_config_cmd[] = {
+       22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1,    /* 1=Use MII  0=Use AUI */
+       0, 0x2E, 0, 0x60, 0x08, 0x88,
+       0x68, 0, 0x40, 0xf2, 0x84,              /* Disable FC */
+       0x31, 0x05,
+};
+
+static void init_rx_ring (struct eth_device *dev);
+static void purge_tx_ring (struct eth_device *dev);
+
+static void read_hw_addr (struct eth_device *dev, bd_t * bis);
+
+static int eepro100_init (struct eth_device *dev, bd_t * bis);
+static int eepro100_send (struct eth_device *dev, volatile void *packet,
+                                                 int length);
+static int eepro100_recv (struct eth_device *dev);
+static void eepro100_halt (struct eth_device *dev);
+
+#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
+#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
+
+static inline int INW (struct eth_device *dev, u_long addr)
+{
+       return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
+}
+
+static inline void OUTW (struct eth_device *dev, int command, u_long addr)
+{
+       *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
+}
+
+static inline void OUTL (struct eth_device *dev, int command, u_long addr)
+{
+       *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
+}
+
+       /* Wait for the chip get the command.
+        */
+static int wait_for_eepro100 (struct eth_device *dev)
+{
+       int i;
+
+       for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
+               if (i >= TOUT_LOOP) {
+                       return 0;
+               }
+       }
+
+       return 1;
+}
+
+static struct pci_device_id supported[] = {
+       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
+       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
+       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
+       {}
+};
+
+int eepro100_initialize (bd_t * bis)
+{
+       pci_dev_t devno;
+       int card_number = 0;
+       struct eth_device *dev;
+       u32 iobase, status;
+       int idx = 0;
+
+       while (1) {
+               /* Find PCI device
+                */
+               if ((devno = pci_find_devices (supported, idx++)) < 0) {
+                       break;
+               }
+
+               pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
+               iobase &= ~0xf;
+
+#ifdef DEBUG
+               printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
+                               iobase);
+#endif
+
+               pci_write_config_dword (devno,
+                                       PCI_COMMAND,
+                                       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+               /* Check if I/O accesses and Bus Mastering are enabled.
+                */
+               pci_read_config_dword (devno, PCI_COMMAND, &status);
+               if (!(status & PCI_COMMAND_MEMORY)) {
+                       printf ("Error: Can not enable MEM access.\n");
+                       continue;
+               }
+
+               if (!(status & PCI_COMMAND_MASTER)) {
+                       printf ("Error: Can not enable Bus Mastering.\n");
+                       continue;
+               }
+
+               dev = (struct eth_device *) malloc (sizeof *dev);
+
+               sprintf (dev->name, "i82559#%d", card_number);
+               dev->iobase = bus_to_phys (iobase);
+               dev->priv = (void *) devno;
+               dev->init = eepro100_init;
+               dev->halt = eepro100_halt;
+               dev->send = eepro100_send;
+               dev->recv = eepro100_recv;
+
+               eth_register (dev);
+
+               card_number++;
+
+               /* Set the latency timer for value.
+                */
+               pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
+
+               udelay (10 * 1000);
+
+               read_hw_addr (dev, bis);
+       }
+
+       return card_number;
+}
+
+
+static int eepro100_init (struct eth_device *dev, bd_t * bis)
+{
+       int i, status = 0;
+       int tx_cur;
+       struct descriptor *ias_cmd, *cfg_cmd;
+
+       /* Reset the ethernet controller
+        */
+       OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
+       udelay (20);
+
+       OUTL (dev, I82559_RESET, SCBPort);
+       udelay (20);
+
+       if (!wait_for_eepro100 (dev)) {
+               printf ("Error: Can not reset ethernet controller.\n");
+               goto Done;
+       }
+       OUTL (dev, 0, SCBPointer);
+       OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
+
+       if (!wait_for_eepro100 (dev)) {
+               printf ("Error: Can not reset ethernet controller.\n");
+               goto Done;
+       }
+       OUTL (dev, 0, SCBPointer);
+       OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
+
+       /* Initialize Rx and Tx rings.
+        */
+       init_rx_ring (dev);
+       purge_tx_ring (dev);
+
+       /* Tell the adapter where the RX ring is located.
+        */
+       if (!wait_for_eepro100 (dev)) {
+               printf ("Error: Can not reset ethernet controller.\n");
+               goto Done;
+       }
+
+       OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
+       OUTW (dev, SCB_M | RUC_START, SCBCmd);
+
+       /* Send the Configure frame */
+       tx_cur = tx_next;
+       tx_next = ((tx_next + 1) % NUM_TX_DESC);
+
+       cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
+       cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
+       cfg_cmd->status = 0;
+       cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
+
+       memcpy (cfg_cmd->params, i82558_config_cmd,
+                       sizeof (i82558_config_cmd));
+
+       if (!wait_for_eepro100 (dev)) {
+               printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n");
+               goto Done;
+       }
+
+       OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
+       OUTW (dev, SCB_M | CU_START, SCBCmd);
+
+       for (i = 0;
+            !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+            i++) {
+               if (i >= TOUT_LOOP) {
+                       printf ("%s: Tx error buffer not ready\n", dev->name);
+                       goto Done;
+               }
+       }
+
+       if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+               printf ("TX error status = 0x%08X\n",
+                       le16_to_cpu (tx_ring[tx_cur].status));
+               goto Done;
+       }
+
+       /* Send the Individual Address Setup frame
+        */
+       tx_cur = tx_next;
+       tx_next = ((tx_next + 1) % NUM_TX_DESC);
+
+       ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
+       ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS));
+       ias_cmd->status = 0;
+       ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
+
+       memcpy (ias_cmd->params, dev->enetaddr, 6);
+
+       /* Tell the adapter where the TX ring is located.
+        */
+       if (!wait_for_eepro100 (dev)) {
+               printf ("Error: Can not reset ethernet controller.\n");
+               goto Done;
+       }
+
+       OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
+       OUTW (dev, SCB_M | CU_START, SCBCmd);
+
+       for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+                i++) {
+               if (i >= TOUT_LOOP) {
+                       printf ("%s: Tx error buffer not ready\n",
+                               dev->name);
+                       goto Done;
+               }
+       }
+
+       if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+               printf ("TX error status = 0x%08X\n",
+                       le16_to_cpu (tx_ring[tx_cur].status));
+               goto Done;
+       }
+
+       status = 1;
+
+  Done:
+       return status;
+}
+
+static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
+{
+       int i, status = -1;
+       int tx_cur;
+
+       if (length <= 0) {
+               printf ("%s: bad packet size: %d\n", dev->name, length);
+               goto Done;
+       }
+
+       tx_cur = tx_next;
+       tx_next = (tx_next + 1) % NUM_TX_DESC;
+
+       tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
+                                               TxCB_CMD_SF     |
+                                               TxCB_CMD_S      |
+                                               TxCB_CMD_EL );
+       tx_ring[tx_cur].status = 0;
+       tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
+       tx_ring[tx_cur].link =
+               cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
+       tx_ring[tx_cur].tx_desc_addr =
+               cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
+       tx_ring[tx_cur].tx_buf_addr0 =
+               cpu_to_le32 (phys_to_bus ((u_long) packet));
+       tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
+
+       if (!wait_for_eepro100 (dev)) {
+               printf ("%s: Tx error ethernet controller not ready.\n",
+                               dev->name);
+               goto Done;
+       }
+
+       /* Send the packet.
+        */
+       OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
+       OUTW (dev, SCB_M | CU_START, SCBCmd);
+
+       for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+                i++) {
+               if (i >= TOUT_LOOP) {
+                       printf ("%s: Tx error buffer not ready\n", dev->name);
+                       goto Done;
+               }
+       }
+
+       if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+               printf ("TX error status = 0x%08X\n",
+                       le16_to_cpu (tx_ring[tx_cur].status));
+               goto Done;
+       }
+
+       status = length;
+
+  Done:
+       return status;
+}
+
+static int eepro100_recv (struct eth_device *dev)
+{
+       u16 status, stat;
+       int rx_prev, length = 0;
+
+       stat = INW (dev, SCBStatus);
+       OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
+
+       for (;;) {
+               status = le16_to_cpu (rx_ring[rx_next].status);
+
+               if (!(status & RFD_STATUS_C)) {
+                       break;
+               }
+
+               /* Valid frame status.
+                */
+               if ((status & RFD_STATUS_OK)) {
+                       /* A valid frame received.
+                        */
+                       length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
+
+                       /* Pass the packet up to the protocol
+                        * layers.
+                        */
+                       NetReceive (rx_ring[rx_next].data, length);
+               } else {
+                       /* There was an error.
+                        */
+                       printf ("RX error status = 0x%08X\n", status);
+               }
+
+               rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
+               rx_ring[rx_next].status = 0;
+               rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
+
+               rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
+               rx_ring[rx_prev].control = 0;
+
+               /* Update entry information.
+                */
+               rx_next = (rx_next + 1) % NUM_RX_DESC;
+       }
+
+       if (stat & SCB_STATUS_RNR) {
+
+               printf ("%s: Receiver is not ready, restart it !\n", dev->name);
+
+               /* Reinitialize Rx ring.
+                */
+               init_rx_ring (dev);
+
+               if (!wait_for_eepro100 (dev)) {
+                       printf ("Error: Can not restart ethernet controller.\n");
+                       goto Done;
+               }
+
+               OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
+               OUTW (dev, SCB_M | RUC_START, SCBCmd);
+       }
+
+  Done:
+       return length;
+}
+
+static void eepro100_halt (struct eth_device *dev)
+{
+       /* Reset the ethernet controller
+        */
+       OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
+       udelay (20);
+
+       OUTL (dev, I82559_RESET, SCBPort);
+       udelay (20);
+
+       if (!wait_for_eepro100 (dev)) {
+               printf ("Error: Can not reset ethernet controller.\n");
+               goto Done;
+       }
+       OUTL (dev, 0, SCBPointer);
+       OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
+
+       if (!wait_for_eepro100 (dev)) {
+               printf ("Error: Can not reset ethernet controller.\n");
+               goto Done;
+       }
+       OUTL (dev, 0, SCBPointer);
+       OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
+
+  Done:
+       return;
+}
+
+       /* SROM Read.
+        */
+static int read_eeprom (struct eth_device *dev, int location, int addr_len)
+{
+       unsigned short retval = 0;
+       int read_cmd = location | EE_READ_CMD;
+       int i;
+
+       OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
+       OUTW (dev, EE_ENB, SCBeeprom);
+
+       /* Shift the read command bits out. */
+       for (i = 12; i >= 0; i--) {
+               short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+
+               OUTW (dev, EE_ENB | dataval, SCBeeprom);
+               udelay (1);
+               OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+               udelay (1);
+       }
+       OUTW (dev, EE_ENB, SCBeeprom);
+
+       for (i = 15; i >= 0; i--) {
+               OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
+               udelay (1);
+               retval = (retval << 1) |
+                               ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
+               OUTW (dev, EE_ENB, SCBeeprom);
+               udelay (1);
+       }
+
+       /* Terminate the EEPROM access. */
+       OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
+       return retval;
+}
+
+#ifdef CONFIG_EEPRO100_SROM_WRITE
+int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
+{
+    unsigned short dataval;
+    int enable_cmd = 0x3f | EE_EWENB_CMD;
+    int write_cmd  = location | EE_WRITE_CMD;
+    int i;
+    unsigned long datalong, tmplong;
+
+    OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB, SCBeeprom);
+
+    /* Shift the enable command bits out. */
+    for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
+    {
+        dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+        OUTW(dev, EE_ENB | dataval, SCBeeprom);
+        udelay(1);
+        OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+        udelay(1);
+    }
+
+    OUTW(dev, EE_ENB, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB, SCBeeprom);
+
+
+    /* Shift the write command bits out. */
+    for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
+    {
+        dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+        OUTW(dev, EE_ENB | dataval, SCBeeprom);
+        udelay(1);
+        OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+        udelay(1);
+    }
+
+    /* Write the data */
+    datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
+
+    for (i = 0; i< EE_DATA_BITS; i++)
+    {
+    /* Extract and move data bit to bit DI */
+    dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
+
+    OUTW(dev, EE_ENB | dataval, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB | dataval, SCBeeprom);
+    udelay(1);
+
+    datalong = datalong << 1; /* Adjust significant data bit*/
+    }
+
+    /* Finish up command  (toggle CS) */
+    OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
+    udelay(1);                /* delay for more than 250 ns */
+    OUTW(dev, EE_ENB, SCBeeprom);
+
+    /* Wait for programming ready (D0 = 1) */
+    tmplong = 10;
+    do
+    {
+        dataval = INW(dev, SCBeeprom);
+        if (dataval & EE_DATA_READ)
+            break;
+        udelay(10000);
+    }
+    while (-- tmplong);
+
+    if (tmplong == 0)
+    {
+        printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
+        return -1;
+    }
+
+    /* Terminate the EEPROM access. */
+    OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
+
+    return 0;
+}
+#endif
+
+static void init_rx_ring (struct eth_device *dev)
+{
+       int i;
+
+       for (i = 0; i < NUM_RX_DESC; i++) {
+               rx_ring[i].status = 0;
+               rx_ring[i].control =
+                               (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
+               rx_ring[i].link =
+                               cpu_to_le32 (phys_to_bus
+                                                        ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
+               rx_ring[i].rx_buf_addr = 0xffffffff;
+               rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
+       }
+
+       rx_next = 0;
+}
+
+static void purge_tx_ring (struct eth_device *dev)
+{
+       int i;
+
+       tx_next = 0;
+       tx_threshold = 0x01208000;
+
+       for (i = 0; i < NUM_TX_DESC; i++) {
+               tx_ring[i].status = 0;
+               tx_ring[i].command = 0;
+               tx_ring[i].link = 0;
+               tx_ring[i].tx_desc_addr = 0;
+               tx_ring[i].count = 0;
+
+               tx_ring[i].tx_buf_addr0 = 0;
+               tx_ring[i].tx_buf_size0 = 0;
+               tx_ring[i].tx_buf_addr1 = 0;
+               tx_ring[i].tx_buf_size1 = 0;
+       }
+}
+
+static void read_hw_addr (struct eth_device *dev, bd_t * bis)
+{
+       u16 eeprom[0x40];
+       u16 sum = 0;
+       int i, j;
+       int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
+
+       for (j = 0, i = 0; i < 0x40; i++) {
+               u16 value = read_eeprom (dev, i, addr_len);
+
+               eeprom[i] = value;
+               sum += value;
+               if (i < 3) {
+                       dev->enetaddr[j++] = value;
+                       dev->enetaddr[j++] = value >> 8;
+               }
+       }
+
+       if (sum != 0xBABA) {
+               memset (dev->enetaddr, 0, ETH_ALEN);
+#ifdef DEBUG
+               printf ("%s: Invalid EEPROM checksum %#4.4x, "
+                       "check settings before activating this device!\n",
+                       dev->name, sum);
+#endif
+       }
+}
+
+#endif

diff --git a/drivers/sym53c8xx.c b/drivers/sym53c8xx.c
new file mode 100644 (file)
index 0000000..e03a049
--- /dev/null
+++ b/drivers/sym53c8xx.c
@@ -0,0 +1,799 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ * partly derived from
+ * linux/drivers/scsi/sym53c8xx.c
+ *
+ */
+
+/*
+ * SCSI support based on the chip sym53C810.
+ *
+ * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>
+ *             The local version of this driver for the BAB750 board does not
+ *             use interrupts but polls the chip instead (see the call of
+ *             'handle_scsi_int()' in 'scsi_issue()'.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_SCSI_SYM53C8XX
+
+#include <command.h>
+#include <cmd_boot.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <sym53c8xx.h>
+#include <scsi.h>
+
+#undef SYM53C8XX_DEBUG
+
+#ifdef SYM53C8XX_DEBUG
+#define        PRINTF(fmt,args...)     printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
+
+#undef SCSI_SINGLE_STEP
+/*
+ * Single Step is only used for debug purposes
+ */
+#ifdef SCSI_SINGLE_STEP
+static unsigned long start_script_select;
+static unsigned long start_script_msgout;
+static unsigned long start_script_msgin;
+static unsigned long start_script_msg_ext;
+static unsigned long start_script_cmd;
+static unsigned long start_script_data_in;
+static unsigned long start_script_data_out;
+static unsigned long start_script_status;
+static unsigned long start_script_complete;
+static unsigned long start_script_error;
+static unsigned long start_script_reselection;
+static unsigned int len_script_select;
+static unsigned int len_script_msgout;
+static unsigned int len_script_msgin;
+static unsigned int len_script_msg_ext;
+static unsigned int len_script_cmd;
+static unsigned int len_script_data_in;
+static unsigned int len_script_data_out;
+static unsigned int len_script_status;
+static unsigned int len_script_complete;
+static unsigned int len_script_error;
+static unsigned int len_script_reselection;
+#endif
+
+
+static unsigned short scsi_int_mask;           /* shadow register for SCSI related interrupts */
+static unsigned char  script_int_mask; /* shadow register for SCRIPT related interrupts */
+static unsigned long script_select[8]; /* script for selection */
+static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */
+static unsigned long script_msgin[14]; /* script for message in phase */
+static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */
+static unsigned long script_cmd[18];    /* script for command phase */
+static unsigned long script_data_in[8]; /* script for data in phase */
+static unsigned long script_data_out[8]; /* script for data out phase */
+static unsigned long script_status[6]; /* script for status phase */
+static unsigned long script_complete[10]; /* script for complete */
+static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */
+static unsigned long script_error[2]; /* script for error handling */
+
+static unsigned long int_stat[3]; /* interrupt status */
+static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */
+
+#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a))
+#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a))
+
+#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */
+
+#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */
+#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */
+
+/*********************************************************************************
+ * forward declerations
+ */
+
+void scsi_chip_init(void);
+void handle_scsi_int(void);
+
+
+/********************************************************************************
+ * reports SCSI errors to the user
+ */
+void scsi_print_error(ccb *pccb)
+{
+       int i;
+       printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]);
+       printf("       CCB: ");
+       for(i=0;i<pccb->cmdlen;i++)
+               printf("%02X ",pccb->cmd[i]);
+       printf("(len=%d)\n",pccb->cmdlen);
+       printf("     Cntrl: ");
+       switch(pccb->contr_stat) {
+               case SIR_COMPLETE:                                              printf("Complete (no Error)\n"); break;
+               case SIR_SEL_ATN_NO_MSG_OUT:    printf("Selected with ATN no MSG out phase\n"); break;
+               case SIR_CMD_OUT_ILL_PH:                        printf("Command out illegal phase\n"); break;
+               case SIR_MSG_RECEIVED:                          printf("MSG received Error\n"); break;
+               case SIR_DATA_IN_ERR:                           printf("Data in Error\n"); break;
+               case SIR_DATA_OUT_ERR:                          printf("Data out Error\n"); break;
+               case SIR_SCRIPT_ERROR:                          printf("Script Error\n"); break;
+               case SIR_MSG_OUT_NO_CMD:                        printf("MSG out no Command phase\n"); break;
+               case SIR_MSG_OVER7:                                     printf("MSG in over 7 bytes\n"); break;
+               case INT_ON_FY:                                                         printf("Interrupt on fly\n"); break;
+               case SCSI_SEL_TIME_OUT:                         printf("SCSI Selection Timeout\n"); break;
+               case SCSI_HNS_TIME_OUT:                         printf("SCSI Handshake Timeout\n"); break;
+               case SCSI_MA_TIME_OUT:                          printf("SCSI Phase Error\n"); break;
+               case SCSI_UNEXP_DIS:                                    printf("SCSI unexpected disconnect\n"); break;
+               default:                                                                                        printf("unknown status %lx\n",pccb->contr_stat); break;
+       }
+       printf("     Sense: SK %x (",pccb->sense_buf[2]&0x0f);
+       switch(pccb->sense_buf[2]&0xf) {
+               case SENSE_NO_SENSE: printf("No Sense)"); break;
+               case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break;
+               case SENSE_NOT_READY:   printf("Not Ready)"); break;
+               case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break;
+               case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break;
+               case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break;
+               case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break;
+               case SENSE_DATA_PROTECT: printf("Data Protect)"); break;
+               case SENSE_BLANK_CHECK: printf("Blank check)"); break;
+               case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break;
+               case SENSE_COPY_ABORTED: printf("Copy aborted)"); break;
+               case SENSE_ABORTED_COMMAND:     printf("Aborted Command)"); break;
+               case SENSE_VOLUME_OVERFLOW:     printf("Volume overflow)"); break;
+               case SENSE_MISCOMPARE: printf("Misscompare\n"); break;
+               default: printf("Illegal Sensecode\n"); break;
+       }
+       printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]);
+       printf("    Status: ");
+       switch(pccb->status) {
+               case S_GOOD :   printf("Good\n"); break;
+               case S_CHECK_COND: printf("Check condition\n"); break;
+               case S_COND_MET: printf("Condition Met\n"); break;
+               case S_BUSY: printf("Busy\n"); break;
+               case S_INT: printf("Intermediate\n"); break;
+               case S_INT_COND_MET: printf("Intermediate condition met\n"); break;
+               case S_CONFLICT: printf("Reservation conflict\n"); break;
+               case S_TERMINATED: printf("Command terminated\n"); break;
+               case S_QUEUE_FULL: printf("Task set full\n"); break;
+               default: printf("unknown: %02X\n",pccb->status); break;
+       }
+
+}
+
+
+
+/******************************************************************************
+ * sets-up the SCSI controller
+ * the base memory address is retrived via the pci_read_config_dword
+ */
+void scsi_low_level_init(int busdevfunc)
+{
+       unsigned int cmd;
+       unsigned int addr;
+       unsigned char vec;
+
+       pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec);
+       pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr);
+
+       addr = bus_to_phys(addr & ~0xf);
+
+       /*
+        * Enable bus mastering in case this has not been done, yet.
+        */
+       pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd);
+       cmd |= PCI_COMMAND_MASTER;
+       pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd);
+
+       scsi_mem_addr = addr;
+
+       scsi_chip_init();
+       scsi_bus_reset();
+}
+
+
+/************************************************************************************
+ * Low level Part of SCSI Driver
+ */
+
+/*
+ * big-endian -> little endian conversion for the script
+ */
+unsigned long swap_script(unsigned long val)
+{
+       unsigned long tmp;
+       tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000);
+       return tmp;
+}
+
+
+void scsi_write_byte(ulong offset,unsigned char val)
+{
+       out8(scsi_mem_addr+offset,val);
+}
+
+
+unsigned char scsi_read_byte(ulong offset)
+{
+       return(in8(scsi_mem_addr+offset));
+}
+
+
+/********************************************************************************
+ * interrupt handler
+ */
+void handle_scsi_int(void)
+{
+       unsigned char stat,stat1,stat2;
+       unsigned short sstat;
+       int i;
+#ifdef SCSI_SINGLE_STEP
+       unsigned long tt;
+#endif
+       stat=scsi_read_byte(ISTAT);
+       if((stat & DIP)==DIP) { /* DMA Interrupt pending */
+               stat1=scsi_read_byte(DSTAT);
+#ifdef SCSI_SINGLE_STEP
+               if((stat1 & SSI)==SSI)
+               {
+                       tt=in32r(scsi_mem_addr+DSP);
+                       if(((tt)>=start_script_select) && ((tt)<start_script_select+len_script_select)) {
+                               printf("select %d\n",(tt-start_script_select)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_msgout) && ((tt)<start_script_msgout+len_script_msgout)) {
+                               printf("msgout %d\n",(tt-start_script_msgout)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_msgin) && ((tt)<start_script_msgin+len_script_msgin)) {
+                               printf("msgin %d\n",(tt-start_script_msgin)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_msg_ext) && ((tt)<start_script_msg_ext+len_script_msg_ext)) {
+                               printf("msgin_ext %d\n",(tt-start_script_msg_ext)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_cmd) && ((tt)<start_script_cmd+len_script_cmd)) {
+                               printf("cmd %d\n",(tt-start_script_cmd)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_data_in) && ((tt)<start_script_data_in+len_script_data_in)) {
+                               printf("data_in %d\n",(tt-start_script_data_in)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_data_out) && ((tt)<start_script_data_out+len_script_data_out)) {
+                               printf("data_out %d\n",(tt-start_script_data_out)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_status) && ((tt)<start_script_status+len_script_status)) {
+                               printf("status %d\n",(tt-start_script_status)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_complete) && ((tt)<start_script_complete+len_script_complete)) {
+                               printf("complete %d\n",(tt-start_script_complete)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_error) && ((tt)<start_script_error+len_script_error)) {
+                               printf("error %d\n",(tt-start_script_error)>>2);
+                               goto end_single;
+                       }
+                       if(((tt)>=start_script_reselection) && ((tt)<start_script_reselection+len_script_reselection)) {
+                               printf("reselection %d\n",(tt-start_script_reselection)>>2);
+                               goto end_single;
+                       }
+                       printf("sc: %lx\n",tt);
+end_single:
+                       stat2=scsi_read_byte(DCNTL);
+                       stat2|=STD;
+                       scsi_write_byte(DCNTL,stat2);
+               }
+#endif
+               if((stat1 & SIR)==SIR) /* script interrupt */
+               {
+                       int_stat[0]=in32(scsi_mem_addr+DSPS);
+               }
+               if((stat1 & DFE)==0) { /* fifo not epmty */
+                       scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
+                       stat2=scsi_read_byte(STEST3);
+                       scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
+               }
+       }
+       if((stat & SIP)==SIP) {  /* scsi interrupt */
+               sstat = (unsigned short)scsi_read_byte(SIST+1);
+               sstat <<=8;
+               sstat |= (unsigned short)scsi_read_byte(SIST);
+               for(i=0;i<3;i++) {
+                       if(int_stat[i]==0)
+                               break; /* found an empty int status */
+               }
+               int_stat[i]=SCSI_INT_STATE | sstat;
+               stat1=scsi_read_byte(DSTAT);
+               if((stat1 & DFE)==0) { /* fifo not epmty */
+                       scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
+                       stat2=scsi_read_byte(STEST3);
+                       scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
+               }
+       }
+       if((stat & INTF)==INTF) { /* interrupt on Fly */
+               scsi_write_byte(ISTAT,stat); /* clear it */
+               for(i=0;i<3;i++) {
+                       if(int_stat[i]==0)
+                               break; /* found an empty int status */
+               }
+               int_stat[i]=INT_ON_FY;
+       }
+}
+
+void scsi_bus_reset(void)
+{
+       unsigned char t;
+       int i;
+       int end = CFG_SCSI_SPIN_UP_TIME*1000;
+
+       t=scsi_read_byte(SCNTL1);
+       scsi_write_byte(SCNTL1,(t | CRST));
+       udelay(50);
+       scsi_write_byte(SCNTL1,t);
+
+       puts("waiting for devices to spin up");
+       for(i=0;i<end;i++) {
+               udelay(1000); /* give the devices time to spin up */
+               if (i % 1000 == 0)
+                       putc('.');
+       }
+       putc('\n');
+       scsi_chip_init(); /* reinit the chip ...*/
+
+}
+
+void scsi_int_enable(void)
+{
+       scsi_write_byte(SIEN,(unsigned char)scsi_int_mask);
+       scsi_write_byte(SIEN+1,(unsigned char)(scsi_int_mask>>8));
+       scsi_write_byte(DIEN,script_int_mask);
+}
+
+void scsi_write_dsp(unsigned long start)
+{
+       unsigned long val;
+#ifdef SCSI_SINGLE_STEP
+       unsigned char t;
+#endif
+       val = start;
+       out32r(scsi_mem_addr + DSP,start);
+#ifdef SCSI_SINGLE_STEP
+       t=scsi_read_byte(DCNTL);
+  t|=STD;
+       scsi_write_byte(DCNTL,t);
+#endif
+}
+
+/* only used for debug purposes */
+void scsi_print_script(void)
+{
+       printf("script_select @         0x%08lX\n",(unsigned long)&script_select[0]);
+       printf("script_msgout @         0x%08lX\n",(unsigned long)&script_msgout[0]);
+       printf("script_msgin @          0x%08lX\n",(unsigned long)&script_msgin[0]);
+       printf("script_msgext @         0x%08lX\n",(unsigned long)&script_msg_ext[0]);
+       printf("script_cmd @            0x%08lX\n",(unsigned long)&script_cmd[0]);
+       printf("script_data_in @        0x%08lX\n",(unsigned long)&script_data_in[0]);
+       printf("script_data_out @       0x%08lX\n",(unsigned long)&script_data_out[0]);
+       printf("script_status @         0x%08lX\n",(unsigned long)&script_status[0]);
+       printf("script_complete @       0x%08lX\n",(unsigned long)&script_complete[0]);
+       printf("script_error @          0x%08lX\n",(unsigned long)&script_error[0]);
+}
+
+
+
+void scsi_set_script(ccb *pccb)
+{
+       int busdevfunc = pccb->priv;
+       int i;
+       i=0;
+       script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe));
+       script_select[i++]=0; /* LED ON */
+       script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */
+       script_select[i++]=0;
+       /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */
+       script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16);
+       script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */
+       script_select[i++]=swap_script(SCR_JUMP); /* next section */
+       /*      script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */
+       script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */
+
+#ifdef SCSI_SINGLE_STEP
+       start_script_select=(unsigned long)&script_select[0];
+       len_script_select=i*4;
+#endif
+
+       i=0;
+       script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)));
+       script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT;
+       script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT);
+       script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0]));
+       script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */
+       script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */
+       script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */
+       script_msgout[i++]=SIR_MSG_OUT_NO_CMD;
+
+#ifdef SCSI_SINGLE_STEP
+       start_script_msgout=(unsigned long)&script_msgout[0];
+       len_script_msgout=i*4;
+#endif
+       i=0;
+       script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND);
+       script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0]));
+       script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */
+       script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
+       script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */
+       script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0]));
+       script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */
+       script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0]));
+       script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)));  /* status ? */
+       script_cmd[i++]=swap_script(phys_to_bus(&script_status[0]));
+       script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)));  /* command ? */
+       script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0]));
+       script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)));  /* message out ? */
+       script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0]));
+       script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */
+       script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
+       script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */
+       script_cmd[i++]=SIR_CMD_OUT_ILL_PH;
+#ifdef SCSI_SINGLE_STEP
+       start_script_cmd=(unsigned long)&script_cmd[0];
+       len_script_cmd=i*4;
+#endif
+       i=0;
+       script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */
+       script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
+       script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
+       script_data_out[i++]=swap_script(phys_to_bus(&script_status[0]));
+       script_data_out[i++]=swap_script(SCR_INT);
+       script_data_out[i++]=SIR_DATA_OUT_ERR;
+
+#ifdef SCSI_SINGLE_STEP
+       start_script_data_out=(unsigned long)&script_data_out[0];
+       len_script_data_out=i*4;
+#endif
+       i=0;
+       script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move  */
+       script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
+       script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
+       script_data_in[i++]=swap_script(phys_to_bus(&script_status[0]));
+       script_data_in[i++]=swap_script(SCR_INT);
+       script_data_in[i++]=SIR_DATA_IN_ERR;
+#ifdef SCSI_SINGLE_STEP
+       start_script_data_in=(unsigned long)&script_data_in[0];
+       len_script_data_in=i*4;
+#endif
+       i=0;
+       script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN);
+       script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0]));
+       script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)));
+       script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
+       script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)));
+       script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
+       script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)));
+       script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
+       script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)));
+       script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
+       script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)));
+       script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0]));
+       script_msgin[i++]=swap_script(SCR_INT);
+       script_msgin[i++]=SIR_MSG_RECEIVED;
+#ifdef SCSI_SINGLE_STEP
+       start_script_msgin=(unsigned long)&script_msgin[0];
+       len_script_msgin=i*4;
+#endif
+       i=0;
+       script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */
+       script_msg_ext[i++]=0;
+       script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */
+       script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1]));
+       script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+       script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+       script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+       script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2]));
+       script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+       script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+       script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+       script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3]));
+       script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+       script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+       script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+       script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4]));
+       script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+       script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+       script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+       script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5]));
+       script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+       script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+       script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+       script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6]));
+       script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+       script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+       script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+       script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7]));
+       script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+       script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+       script_msg_ext[i++]=swap_script(SCR_INT);
+       script_msg_ext[i++]=SIR_MSG_OVER7;
+#ifdef SCSI_SINGLE_STEP
+       start_script_msg_ext=(unsigned long)&script_msg_ext[0];
+       len_script_msg_ext=i*4;
+#endif
+       i=0;
+       script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS);
+       script_status[i++]=swap_script(phys_to_bus(&pccb->status));
+       script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)));
+       script_status[i++]=swap_script(phys_to_bus(&script_msgin[0]));
+       script_status[i++]=swap_script(SCR_INT);
+       script_status[i++]=SIR_STATUS_ILL_PH;
+#ifdef SCSI_SINGLE_STEP
+       start_script_status=(unsigned long)&script_status[0];
+       len_script_status=i*4;
+#endif
+       i=0;
+       script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f));
+       script_complete[i++]=0;
+       script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN));
+       script_complete[i++]=0;
+       script_complete[i++]=swap_script(SCR_WAIT_DISC);
+       script_complete[i++]=0;
+       script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01));
+       script_complete[i++]=0; /* LED OFF */
+       script_complete[i++]=swap_script(SCR_INT);
+       script_complete[i++]=SIR_COMPLETE;
+#ifdef SCSI_SINGLE_STEP
+       start_script_complete=(unsigned long)&script_complete[0];
+       len_script_complete=i*4;
+#endif
+       i=0;
+       script_error[i++]=swap_script(SCR_INT); /* interrupt if error */
+       script_error[i++]=SIR_SCRIPT_ERROR;
+#ifdef SCSI_SINGLE_STEP
+       start_script_error=(unsigned long)&script_error[0];
+       len_script_error=i*4;
+#endif
+       i=0;
+       script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */
+       script_reselection[i++]=0;
+       script_reselection[i++]=swap_script(SCR_WAIT_RESEL);
+       script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */
+#ifdef SCSI_SINGLE_STEP
+       start_script_reselection=(unsigned long)&script_reselection[0];
+       len_script_reselection=i*4;
+#endif
+}
+
+
+
+void scsi_issue(ccb *pccb)
+{
+       int busdevfunc = pccb->priv;
+       int i;
+       unsigned short sstat;
+       int retrycnt;  /* retry counter */
+       for(i=0;i<3;i++)
+               int_stat[i]=0; /* delete all int status */
+       /* struct pccb must be set-up correctly */
+       retrycnt=0;
+       PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]);
+       pccb->trans_bytes=0; /* no bytes transfered yet */
+       scsi_set_script(pccb); /* fill in SCRIPT                */
+       scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */
+       script_int_mask=0xff; /* enable all Ints */
+       scsi_int_enable();
+       scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */
+       /* now we have to wait for IRQs */
+retry:
+       /*
+        * This version of the driver is _not_ interrupt driven,
+        * but polls the chip's interrupt registers (ISTAT, DSTAT).
+        */
+       while(int_stat[0]==0)
+               handle_scsi_int();
+
+       if(int_stat[0]==SIR_COMPLETE) {
+               if(pccb->msgin[0]==M_DISCONNECT) {
+                       PRINTF("Wait for reselection\n");
+                       for(i=0;i<3;i++)
+                               int_stat[i]=0; /* delete all int status */
+                       scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */
+                       goto retry;
+               }
+               pccb->contr_stat=SIR_COMPLETE;
+               return;
+       }
+       if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */
+               sstat=(unsigned short)int_stat[0];
+               if((sstat & STO)==STO) { /* selection timeout */
+                       pccb->contr_stat=SCSI_SEL_TIME_OUT;
+                       scsi_write_byte(GPREG,0x01);
+                       PRINTF("ID: %X Selection Timeout\n",pccb->target);
+                       return;
+               }
+               if((sstat & UDC)==UDC) { /* unexpected disconnect */
+                       pccb->contr_stat=SCSI_UNEXP_DIS;
+                       scsi_write_byte(GPREG,0x01);
+                       PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
+                       return;
+               }
+               if((sstat & RSL)==RSL) { /* reselection */
+                       pccb->contr_stat=SCSI_UNEXP_DIS;
+                       scsi_write_byte(GPREG,0x01);
+                       PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
+                       return;
+               }
+               if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */
+                       if(retrycnt<SCSI_MAX_RETRY) {
+                               pccb->trans_bytes=pccb->datalen -
+                                       ((unsigned long)scsi_read_byte(DBC) |
+                                       ((unsigned long)scsi_read_byte(DBC+1)<<8) |
+                                       ((unsigned long)scsi_read_byte(DBC+2)<<16));
+                               for(i=0;i<3;i++)
+                                       int_stat[i]=0; /* delete all int status */
+                               retrycnt++;
+                               PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n",
+                                               pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes);
+                               scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */
+                               goto retry;
+                       }
+                       if((sstat & MA)==MA)
+                               pccb->contr_stat=SCSI_MA_TIME_OUT;
+                       else
+                               pccb->contr_stat=SCSI_HNS_TIME_OUT;
+                       PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat);
+                       return;
+               } /* no phase int */
+/*             if((sstat & CMP)==CMP) {
+                       pccb->contr_stat=SIR_COMPLETE;
+                       return;
+               }
+*/
+               PRINTF("SCSI INT %lX\n",int_stat[0]);
+               pccb->contr_stat=int_stat[0];
+               return;
+       } /* end scsi int */
+       PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL));
+       pccb->contr_stat=int_stat[0];
+       return;
+}
+
+int scsi_exec(ccb *pccb)
+{
+       unsigned char tmpcmd[16],tmpstat;
+       int i,retrycnt,t;
+       unsigned long transbytes,datalen;
+       unsigned char *tmpptr;
+       retrycnt=0;
+retry:
+       scsi_issue(pccb);
+       if(pccb->contr_stat!=SIR_COMPLETE)
+               return FALSE;
+       if(pccb->status==S_GOOD)
+               return TRUE;
+       if(pccb->status==S_CHECK_COND) { /* check condition */
+               for(i=0;i<16;i++)
+                       tmpcmd[i]=pccb->cmd[i];
+               pccb->cmd[0]=SCSI_REQ_SENSE;
+               pccb->cmd[1]=pccb->lun<<5;
+               pccb->cmd[2]=0;
+               pccb->cmd[3]=0;
+               pccb->cmd[4]=14;
+               pccb->cmd[5]=0;
+               pccb->cmdlen=6;
+               pccb->msgout[0]=SCSI_IDENTIFY;
+               transbytes=pccb->trans_bytes;
+               tmpptr=pccb->pdata;
+               pccb->pdata=&pccb->sense_buf[0];
+               datalen=pccb->datalen;
+               pccb->datalen=14;
+               tmpstat=pccb->status;
+               scsi_issue(pccb);
+               for(i=0;i<16;i++)
+                       pccb->cmd[i]=tmpcmd[i];
+               pccb->trans_bytes=transbytes;
+               pccb->pdata=tmpptr;
+               pccb->datalen=datalen;
+               pccb->status=tmpstat;
+               PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f,
+                       pccb->sense_buf[12],pccb->sense_buf[13]);
+               switch(pccb->sense_buf[2]&0xf) {
+                       case SENSE_NO_SENSE:
+                       case SENSE_RECOVERED_ERROR:
+                               /* seems to be ok */
+                               return TRUE;
+                               break;
+                       case SENSE_NOT_READY:
+                               if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) {
+                                       /* if device is not in process of becoming ready */
+                                       return FALSE;
+                                       break;
+                               } /* else fall through */
+                       case SENSE_UNIT_ATTENTION:
+                               if(retrycnt<SCSI_MAX_RETRY_NOT_READY) {
+                                       PRINTF("Target %d not ready, retry %d\n",pccb->target,retrycnt);
+                                       for(t=0;t<SCSI_NOT_READY_TIME_OUT;t++)
+                                               udelay(1000); /* 1sec wait */
+                                       retrycnt++;
+                                       goto retry;
+                               }
+                               PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt);
+                               return FALSE;
+                       default:
+                               return FALSE;
+               }
+       }
+       PRINTF("Status = %X\n",pccb->status);
+       return FALSE;
+}
+
+
+
+
+void scsi_chip_init(void)
+{
+       /* first we issue a soft reset */
+       scsi_write_byte(ISTAT,SRST);
+       udelay(1000);
+       scsi_write_byte(ISTAT,0);
+       /* setup chip */
+       scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */
+       scsi_write_byte(SCNTL1,0x00);
+       scsi_write_byte(SCNTL2,0x00);
+#ifndef CFG_SCSI_SYM53C8XX_CCF    /* config value for none 40 mhz clocks */
+       scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */
+#else
+       scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */
+#endif
+       scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */
+       scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */
+       scsi_write_byte(SDID,0x00);  /* targed SCSI ID = 0 */
+       scsi_int_mask=0x0000; /* no Interrupt is enabled */
+       script_int_mask=0x00;
+       scsi_int_enable();
+       scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */
+       scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */
+       scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */
+       scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */
+       scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */
+       scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */
+       scsi_write_byte(STEST3,0x80); /* enable tolerANT */
+       scsi_write_byte(CTEST3,0x04); /* clear FIFO */
+       scsi_write_byte(CTEST4,0x00);
+       scsi_write_byte(CTEST5,0x00);
+#ifdef SCSI_SINGLE_STEP
+/*     scsi_write_byte(DCNTL,IRQM | SSM);      */
+       scsi_write_byte(DCNTL,IRQD | SSM);
+       scsi_write_byte(DMODE,MAN);
+#else
+/*     scsi_write_byte(DCNTL,IRQM);    */
+       scsi_write_byte(DCNTL,IRQD);
+       scsi_write_byte(DMODE,0x00);
+#endif
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */
+
+
+#endif /* CONFIG_SCSI_SYM53C8XX */

diff --git a/drivers/w83c553f.c b/drivers/w83c553f.c
new file mode 100644 (file)
index 0000000..5d82ed4
--- /dev/null
+++ b/drivers/w83c553f.c
@@ -0,0 +1,226 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
+ * write protection (for flash) in function 0 of the chip.
+ * Enabling function 1 (IDE controller of the chip.
+ */
+
+#include <common.h>
+#include <config.h>
+
+#ifdef CFG_WINBOND_83C553
+
+#include <asm/io.h>
+#include <pci.h>
+
+#include <w83c553f.h>
+
+#define out8(addr,val) do { \
+                       out_8((u8*) (addr),(val)); udelay(1); \
+                       } while (0)
+#define out16(addr,val)        do { \
+                       out_be16((u16*) (addr),(val)); udelay(1); \
+                       } while (0)
+
+extern uint ide_bus_offset[CFG_IDE_MAXBUS];
+
+void initialise_pic(void);
+void initialise_dma(void);
+
+void initialise_w83c553f(void)
+{
+       pci_dev_t devbusfn;
+       unsigned char reg8;
+       unsigned short reg16;
+       unsigned int reg32;
+
+       devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
+       if (devbusfn == -1)
+       {
+               printf("Error: Cannot find W83C553F controller on any PCI bus.");
+               return;
+       }
+
+       pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
+       reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+       pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
+
+       pci_read_config_byte(devbusfn, WINBOND_IPADCR, &reg8);
+       /* 16 MB ISA memory space */
+       reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
+       reg8 &= ~IPADCR_MBE512;
+       pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
+
+       pci_read_config_byte(devbusfn, WINBOND_CSCR, &reg8);
+       /* switch off BIOS write protection */
+       reg8 |= CSCR_UBIOSCSE;
+       reg8 &= ~CSCR_BIOSWP;
+       pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
+
+       /*
+        * Interrupt routing:
+        *  - IDE  -> IRQ 9/0
+        *  - INTA -> IRQ 10
+        *  - INTB -> IRQ 11
+        *  - INTC -> IRQ 14
+        *  - INTD -> IRQ 15
+        */
+       pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
+       pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
+
+       /*
+        * Read IDE bus offsets from function 1 device.
+        * We must unmask the LSB indicating that ist is an IO address.
+        */
+       devbusfn |= PCI_BDF(0,0,1);
+
+       /*
+        * Switch off legacy IRQ for IDE and IDE port 1.
+        */
+       pci_write_config_byte(devbusfn, 0x09, 0x8F);
+
+       pci_read_config_dword(devbusfn, WINDOND_IDECSR, &reg32);
+       reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
+       pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
+
+       pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
+       ide_bus_offset[0] &= ~1;
+#if CFG_IDE_MAXBUS > 1
+       pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
+       ide_bus_offset[1] &= ~1;
+#endif
+
+       /*
+        * Enable function 1, IDE -> busmastering and IO space access
+        */
+       pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
+       reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+       pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
+
+       /*
+        * Initialise ISA interrupt controller
+        */
+       initialise_pic();
+
+       /*
+        * Initialise DMA controller
+        */
+       initialise_dma();
+}
+
+void initialise_pic(void)
+{
+       out8(W83C553F_PIC1_ICW1, 0x11);
+       out8(W83C553F_PIC1_ICW2, 0x08);
+       out8(W83C553F_PIC1_ICW3, 0x04);
+       out8(W83C553F_PIC1_ICW4, 0x01);
+       out8(W83C553F_PIC1_OCW1, 0xfb);
+       out8(W83C553F_PIC1_ELC, 0x20);
+
+       out8(W83C553F_PIC2_ICW1, 0x11);
+       out8(W83C553F_PIC2_ICW2, 0x08);
+       out8(W83C553F_PIC2_ICW3, 0x02);
+       out8(W83C553F_PIC2_ICW4, 0x01);
+       out8(W83C553F_PIC2_OCW1, 0xff);
+       out8(W83C553F_PIC2_ELC, 0xce);
+
+       out8(W83C553F_TMR1_CMOD, 0x74);
+
+       out8(W83C553F_PIC2_OCW1, 0x20);
+       out8(W83C553F_PIC1_OCW1, 0x20);
+
+       out8(W83C553F_PIC2_OCW1, 0x2b);
+       out8(W83C553F_PIC1_OCW1, 0x2b);
+}
+
+void initialise_dma(void)
+{
+       unsigned int channel;
+       unsigned int rvalue1, rvalue2;
+
+       /* perform a H/W reset of the devices */
+
+       out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
+       out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
+
+       /* initialise all channels to a sane state */
+
+       for (channel = 0; channel < 4; channel++) {
+               /*
+                * dependent upon the channel, setup the specifics:
+                *
+                * demand
+                * address-increment
+                * autoinitialize-disable
+                * verify-transfer
+                */
+
+               switch (channel) {
+               case 0:
+                       rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
+                       rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
+                       break;
+               case 1:
+                       rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
+                       rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
+                       break;
+               case 2:
+                       rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
+                       rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
+                       break;
+               case 3:
+                       rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
+                       rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
+                       break;
+               default:
+                       rvalue1 = 0x00;
+                       rvalue2 = 0x00;
+                       break;
+               }
+
+               /* write to write mode registers */
+
+               out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
+               out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
+       }
+
+       /* enable all channels */
+
+       out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
+       out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
+       /*
+        * initialize the global DMA configuration
+        *
+        * DACK# active low
+        * DREQ active high
+        * fixed priority
+        * channel group enable
+        */
+
+       out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
+       out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
+}
+
+#endif /* CFG_WINBOND_83C553 */

diff --git a/include/i8042.h b/include/i8042.h
new file mode 100644 (file)
index 0000000..61c9da2
--- /dev/null
+++ b/include/i8042.h
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* i8042.h - Intel 8042 keyboard driver header */
+
+#ifndef _I8042_H_
+#define _I8042_H_
+
+/* defines */
+
+#define I8042_DATA_REG      (CFG_ISA_IO + 0x0060)    /* keyboard i/o buffer */
+#define I8042_STATUS_REG    (CFG_ISA_IO + 0x0064)    /* keyboard status read */
+#define I8042_COMMAND_REG   (CFG_ISA_IO + 0x0064)    /* keyboard ctrl write */
+
+#define KBD_US              0        /* default US layout */
+#define KBD_GER             1        /* german layout */
+
+#define KBD_TIMEOUT         1000     /* 1 sec */
+#define KBD_RESET_TRIES     3
+
+#define AS                  0        /* normal character index */
+#define SH                  1        /* shift index */
+#define CN                  2        /* control index */
+#define NM                  3        /* numeric lock index */
+#define AK                  4        /* right alt key */
+#define CP                  5        /* capslock index */
+#define ST                  6        /* stop output index */
+#define EX                  7        /* extended code index */
+#define ES                  8        /* escape and extended code index */
+
+#define NORMAL              0x0000    /* normal key */
+#define STP                 0x0001    /* scroll lock stop output*/
+#define NUM                 0x0002    /* numeric lock */
+#define CAPS                0x0004    /* capslock */
+#define SHIFT               0x0008    /* shift */
+#define CTRL                0x0010    /* control*/
+#define EXT                 0x0020    /* extended scan code 0xe0 */
+#define ESC                 0x0040    /* escape key press */
+#define E1                  0x0080    /* extended scan code 0xe1 */
+#define BRK                 0x0100    /* make break flag for keyboard */
+#define ALT                 0x0200    /* right alt */
+
+/* exports */
+
+int i8042_kbd_init(void);
+int i8042_tstc(void);
+int i8042_getc(void);
+
+#endif /* _I8042_H_ */

diff --git a/include/linux_logo.h b/include/linux_logo.h
new file mode 100644 (file)
index 0000000..9aa712e
--- /dev/null
+++ b/include/linux_logo.h
@@ -0,0 +1,1445 @@
+/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $
+ * include/linux/linux_logo.h: This is a linux logo
+ *                             to be displayed on boot.
+ *
+ * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
+ * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ *
+ * You can put anything here, but:
+ * LINUX_LOGO_COLORS has to be less than 224
+ * image size has to be 80x80
+ * values have to start from 0x20
+ * (i.e. RGB(linux_logo_red[0],
+ *           linux_logo_green[0],
+ *           linux_logo_blue[0]) is color 0x20)
+ * BW image has to be 80x80 as well, with MS bit
+ * on the left
+ * Serial_console ascii image can be any size,
+ * but should contain %s to display the version
+ */
+
+#if LINUX_LOGO_COLORS == 214
+
+unsigned char linux_logo_red[] __initdata = {
+  0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9,
+  0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6,
+  0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2,
+  0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54,
+  0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74,
+  0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E,
+  0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38,
+  0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3,
+  0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA,
+  0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC,
+  0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B,
+  0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52,
+  0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2,
+  0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6,
+  0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF,
+  0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46,
+  0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6,
+  0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA,
+  0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E,
+  0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7,
+  0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4,
+  0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA,
+  0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59,
+  0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB,
+  0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6,
+  0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72,
+  0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4
+};
+
+unsigned char linux_logo_green[] __initdata = {
+  0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5,
+  0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86,
+  0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96,
+  0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54,
+  0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74,
+  0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42,
+  0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24,
+  0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C,
+  0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2,
+  0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D,
+  0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E,
+  0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A,
+  0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE,
+  0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE,
+  0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB,
+  0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E,
+  0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E,
+  0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A,
+  0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62,
+  0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6,
+  0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA,
+  0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6,
+  0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45,
+  0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92,
+  0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA,
+  0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56,
+  0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE
+};
+
+unsigned char linux_logo_blue[] __initdata = {
+  0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7,
+  0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20,
+  0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40,
+  0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56,
+  0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74,
+  0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11,
+  0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A,
+  0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11,
+  0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C,
+  0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C,
+  0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E,
+  0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C,
+  0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94,
+  0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC,
+  0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91,
+  0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C,
+  0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C,
+  0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74,
+  0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04,
+  0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2,
+  0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10,
+  0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C,
+  0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E,
+  0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C,
+  0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C,
+  0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24,
+  0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7
+};
+
+unsigned char linux_logo[] __initdata = {
+  0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C,
+  0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95,
+  0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C,
+  0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6,
+  0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55,
+  0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A,
+  0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1,
+  0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95,
+  0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6,
+  0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A,
+  0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB,
+  0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C,
+  0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C,
+  0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6,
+  0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C,
+  0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55,
+  0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6,
+  0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70,
+  0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
+  0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95,
+  0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1,
+  0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1,
+  0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55,
+  0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
+  0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
+  0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
+  0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x55, 0x2C, 0x3F, 0x80, 0x20, 0x88, 0x88,
+  0x88, 0x20, 0x88, 0xB1, 0x2C, 0xA1, 0x2C, 0x2C,
+  0x95, 0xCB, 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6,
+  0xA1, 0x95, 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55,
+  0xCB, 0xCB, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
+  0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
+  0x2C, 0x94, 0x80, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x88, 0x92, 0xA1, 0x95,
+  0x55, 0x90, 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6,
+  0xA1, 0x2C, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1,
+  0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95,
+  0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
+  0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
+  0xA1, 0xD6, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x55,
+  0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, 0x95, 0xD6,
+  0xB1, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x80, 0x34, 0x88, 0x43, 0x47,
+  0x95, 0xCB, 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
+  0xA1, 0x95, 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55,
+  0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
+  0x55, 0x55, 0x55, 0x55, 0x2C, 0x95, 0x2C, 0x2C,
+  0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
+  0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0xA1, 0xA1,
+  0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD5,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0x7D, 0x3F, 0xB1, 0x80, 0x20,
+  0x99, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1,
+  0x2C, 0x55, 0x90, 0x70, 0x90, 0x55, 0x95, 0x95,
+  0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
+  0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0xCB,
+  0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x88,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0xB1, 0x47, 0xD5, 0x7D, 0x43,
+  0x20, 0x70, 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
+  0x95, 0xCB, 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1,
+  0xA1, 0xA1, 0x2C, 0x95, 0x2C, 0x2C, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x90, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0x90,
+  0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
+  0x95, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x55,
+  0xCB, 0xCB, 0xCB, 0x55, 0xCB, 0x55, 0x47, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0xB1, 0x3F, 0x92, 0x2B, 0x80,
+  0x20, 0x80, 0xD6, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
+  0x2C, 0x90, 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6,
+  0xD6, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x95,
+  0x95, 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
+  0xD6, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x70,
+  0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x95,
+  0x55, 0x55, 0x55, 0x95, 0x55, 0x55, 0xCB, 0x90,
+  0x70, 0x90, 0xCB, 0x55, 0x55, 0xA1, 0xD8, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0xD8, 0xE1, 0x88, 0x20, 0x20,
+  0x88, 0x88, 0xE6, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
+  0x55, 0x70, 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
+  0xA1, 0x95, 0x55, 0x55, 0x95, 0x95, 0x55, 0x55,
+  0x90, 0x90, 0x90, 0x90, 0xCB, 0x55, 0x55, 0x55,
+  0xD6, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0xCB, 0x70,
+  0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x55,
+  0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x95, 0x2C, 0x95, 0x2C, 0xD6, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x80, 0xD6, 0xA1, 0xD6, 0xD6, 0xA1,
+  0xCB, 0x70, 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C,
+  0x2C, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x94,
+  0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, 0xCB, 0x55,
+  0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x95, 0xA1,
+  0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0x95, 0xA1, 0xA1, 0xA1, 0x55,
+  0x70, 0x94, 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95,
+  0xCB, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55,
+  0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
+  0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x70, 0x90, 0xCB,
+  0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x2C, 0xD6,
+  0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x70, 0x20, 0x20,
+  0x88, 0x43, 0xD8, 0x43, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x88, 0x88, 0x43, 0x2B, 0xD8, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x3F, 0x2C, 0x95, 0x95, 0xCB,
+  0x70, 0x70, 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90,
+  0x90, 0xCB, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x95,
+  0x2C, 0xD6, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x90, 0x55,
+  0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70, 0x55, 0x95,
+  0x95, 0xCB, 0x90, 0x90, 0x90, 0x95, 0x2C, 0xA1,
+  0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x70, 0x20, 0x20,
+  0x80, 0x2B, 0x34, 0x2B, 0x88, 0x20, 0x20, 0x20,
+  0x88, 0xB1, 0x28, 0x28, 0x2B, 0x7D, 0x80, 0x20,
+  0x20, 0x20, 0x20, 0x92, 0x95, 0x55, 0xCB, 0x70,
+  0x90, 0x55, 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70,
+  0x55, 0x95, 0x55, 0x55, 0x90, 0x90, 0x90, 0x55,
+  0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
+  0xA1, 0x95, 0x55, 0xCB, 0x90, 0x70, 0xCB, 0x95,
+  0xA1, 0x95, 0x95, 0xCB, 0x90, 0xCB, 0x95, 0x2C,
+  0x95, 0x70, 0x70, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x55, 0xCB, 0x55, 0x90, 0x20, 0x34,
+  0x90, 0x6D, 0x70, 0xD8, 0x43, 0x20, 0x20, 0x88,
+  0x3F, 0x55, 0xA1, 0x2A, 0xD6, 0x7D, 0x43, 0x20,
+  0x20, 0x20, 0x88, 0x7D, 0x55, 0xCB, 0x90, 0x70,
+  0xCB, 0x95, 0xA1, 0x95, 0x95, 0xCB, 0x70, 0xCB,
+  0x95, 0xA1, 0x95, 0x70, 0x70, 0xCB, 0x55, 0x2C,
+  0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
+  0x2C, 0x55, 0x90, 0x70, 0x94, 0x90, 0x95, 0x2C,
+  0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95, 0xA1, 0xA1,
+  0x95, 0x90, 0x90, 0x95, 0xA1, 0xD6, 0xD6, 0x6D,
+  0xA1, 0x95, 0x55, 0xCB, 0x55, 0xCB, 0x20, 0x99,
+  0xBF, 0xA3, 0xA3, 0x90, 0x20, 0x20, 0x20, 0x92,
+  0x83, 0x6B, 0x6B, 0x6B, 0xA3, 0x70, 0x88, 0x20,
+  0x20, 0x20, 0x20, 0x2B, 0x90, 0x70, 0x94, 0x90,
+  0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95,
+  0xA1, 0x2C, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xD6,
+  0xD6, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
+  0x2C, 0x55, 0x70, 0x70, 0x94, 0x90, 0x95, 0x2C,
+  0x2C, 0x55, 0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x2C,
+  0x55, 0x55, 0x95, 0xA1, 0x6D, 0xBF, 0x6D, 0xD6,
+  0x95, 0x55, 0x90, 0xCB, 0x55, 0x95, 0x88, 0x95,
+  0x2C, 0x3F, 0x6D, 0x6B, 0x34, 0x20, 0x20, 0x47,
+  0x65, 0xD6, 0xE1, 0x3F, 0x2A, 0x6B, 0x2B, 0x20,
+  0x20, 0x20, 0x20, 0x43, 0x70, 0x70, 0x94, 0x90,
+  0x95, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x95, 0x2C,
+  0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xBF,
+  0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
+  0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
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+  0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55,
+  0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x2C,
+  0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95,
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+  0x89, 0x69, 0x4F, 0x20, 0x20, 0x20, 0x8A, 0x42,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x83, 0x4A, 0x3A, 0x50, 0x62, 0x23,
+  0x81, 0xB8, 0xB8, 0xE9, 0x5F, 0x29, 0x33, 0x5D,
+  0x5D, 0x73, 0xE8, 0xCB, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x70,
+  0xCB, 0x68, 0x75, 0x50, 0x82, 0x49, 0x49, 0x49,
+  0x5D, 0x49, 0x49, 0x5D, 0x49, 0x49, 0x5D, 0x82,
+  0x69, 0x5D, 0x25, 0xF0, 0x20, 0x20, 0x20, 0xE1,
+  0x2A, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0x4B, 0xF4, 0xDF, 0x50, 0x73, 0x76, 0x48,
+  0x75, 0xDF, 0x75, 0x62, 0xC4, 0x33, 0x82, 0x49,
+  0x5D, 0x5D, 0xA8, 0xF5, 0x55, 0x55, 0x55, 0x55,
+  0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
+  0x95, 0x83, 0x5F, 0xEA, 0x2D, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x5D, 0x49, 0x22, 0x5A, 0x79, 0x20, 0x20, 0x20,
+  0x80, 0xD2, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x65, 0xD0, 0x63, 0x5F, 0x29, 0x2D, 0x2D, 0xEA,
+  0x29, 0x29, 0x76, 0x50, 0x2D, 0x82, 0x49, 0x49,
+  0x3E, 0x49, 0x5C, 0xB0, 0xBA, 0x95, 0x55, 0x55,
+  0x2C, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x70, 0x55,
+  0x2C, 0x83, 0x60, 0x76, 0x5D, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x5D, 0x89, 0xDC, 0x8B, 0x20, 0x20, 0x20,
+  0x20, 0x95, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE2, 0x32, 0x85, 0xE3, 0x29, 0x2D, 0x33, 0x2D,
+  0x2D, 0x2D, 0x6A, 0x2D, 0x33, 0x5D, 0x49, 0x82,
+  0x49, 0x49, 0x82, 0x73, 0x5C, 0x9E, 0x2C, 0x55,
+  0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
+  0x2C, 0x95, 0x55, 0xCB, 0x90, 0x90, 0xCB, 0x95,
+  0x2C, 0x6D, 0x41, 0x6F, 0x3E, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x82, 0x3E, 0x4E, 0x38, 0xCA, 0x20, 0x20,
+  0x20, 0x55, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65,
+  0x42, 0xA0, 0xD4, 0xE3, 0x29, 0x2D, 0x82, 0x5D,
+  0x5D, 0x82, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x3E, 0x49, 0x49, 0x49, 0x5C, 0x56, 0xD6,
+  0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
+  0xA1, 0x55, 0x90, 0x70, 0x94, 0x70, 0x95, 0x2C,
+  0x2C, 0xD6, 0xDD, 0x6F, 0x33, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x5D, 0x5D, 0x82, 0x69, 0x22, 0x62, 0x80, 0x34,
+  0x94, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0x65, 0x6B,
+  0xD5, 0x88, 0x5B, 0xE3, 0x29, 0x5D, 0x5D, 0x5D,
+  0x5D, 0x5D, 0x5D, 0x5D, 0x49, 0x49, 0x49, 0x82,
+  0x49, 0x49, 0x89, 0x49, 0x82, 0x49, 0x71, 0xBA,
+  0x6D, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
+  0x2C, 0x55, 0x70, 0x70, 0x70, 0x90, 0x95, 0xA1,
+  0x2C, 0xA1, 0x41, 0x76, 0x5D, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x5D, 0x82, 0x5D, 0x89, 0x5E, 0x96, 0x65,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xEC, 0xB1,
+  0x20, 0x20, 0xCA, 0x23, 0x29, 0x33, 0x49, 0x5D,
+  0x49, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49, 0x82,
+  0x49, 0x82, 0x5D, 0x5D, 0x5D, 0x2D, 0x5C, 0x8F,
+  0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
+  0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
+  0x95, 0xE8, 0x5F, 0x76, 0x33, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x3E, 0x9C, 0x2F, 0x68,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x65, 0xE5, 0x65, 0xE5, 0x6B, 0x90, 0x80, 0x20,
+  0x20, 0x20, 0x4F, 0x81, 0x50, 0x3E, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x69, 0x69, 0x49, 0x5D, 0x2D, 0xC4, 0x46, 0xA3,
+  0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
+  0x55, 0xCB, 0x70, 0x47, 0x70, 0x95, 0xA1, 0xA1,
+  0x95, 0xBD, 0x75, 0x2D, 0x33, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x5D, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x5D, 0x2D, 0xB5, 0xDB,
+  0xD6, 0x65, 0xE5, 0x65, 0xE5, 0xE5, 0x65, 0xE5,
+  0x65, 0x65, 0x6B, 0x95, 0x2B, 0x88, 0x20, 0x20,
+  0x20, 0x20, 0x8B, 0x81, 0x29, 0x33, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x3E, 0x3E, 0x5E, 0x41, 0x97, 0x27, 0xD6,
+  0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
+  0x94, 0x70, 0x94, 0x94, 0x70, 0x55, 0xA1, 0x2C,
+  0x6D, 0xC5, 0x39, 0x6A, 0x5D, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x3E, 0xEA, 0x30, 0x77,
+  0xE1, 0xC9, 0x94, 0x2C, 0xD6, 0xD6, 0xA1, 0x55,
+  0x47, 0x9F, 0x43, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x80, 0x91, 0x81, 0x6A, 0x2D, 0x49, 0x49,
+  0x49, 0x5D, 0x5D, 0x49, 0x49, 0x5D, 0x5D, 0x82,
+  0xEB, 0x4A, 0x41, 0xC2, 0x8F, 0xF5, 0xA1, 0x55,
+  0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
+  0x47, 0x70, 0x70, 0x94, 0x90, 0x95, 0xA1, 0x2C,
+  0xE8, 0xA6, 0x39, 0x76, 0x50, 0x50, 0x2D, 0x2D,
+  0x3E, 0x3E, 0x5D, 0x3E, 0x5D, 0x5D, 0x49, 0x82,
+  0x49, 0x49, 0x49, 0x82, 0x82, 0x50, 0x75, 0xE0,
+  0x57, 0x20, 0x88, 0x88, 0x20, 0x20, 0x88, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x79, 0x91, 0x81, 0x76, 0x33, 0x49, 0x49,
+  0x5D, 0x82, 0x49, 0x49, 0x3E, 0x6A, 0xEA, 0x29,
+  0xDF, 0x97, 0xBF, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
+  0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
+  0x95, 0x95, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xA1,
+  0xD6, 0x26, 0x45, 0x81, 0x5F, 0x30, 0x48, 0x6F,
+  0x6F, 0x29, 0x29, 0x6A, 0x2D, 0x2D, 0x5D, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x2D, 0x76, 0x6E, 0x77,
+  0x5B, 0x66, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x79, 0xA9, 0xB8, 0x39, 0x50, 0x5D, 0x5D,
+  0x5D, 0x5D, 0x3E, 0x2D, 0x29, 0x76, 0xCD, 0x37,
+  0xB9, 0xA1, 0xA1, 0x6D, 0x6D, 0x2C, 0x94, 0x28,
+  0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
+  0xBF, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0xA1, 0x2C,
+  0x95, 0x83, 0xDE, 0x87, 0xB6, 0xBE, 0x40, 0x6E,
+  0x81, 0x81, 0x78, 0x78, 0x39, 0x6F, 0xEA, 0x2D,
+  0x2D, 0x33, 0x33, 0x33, 0x76, 0x30, 0x64, 0x54,
+  0x5B, 0x66, 0x20, 0x20, 0x66, 0x20, 0x88, 0x20,
+  0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0x34, 0x8B, 0xF1, 0x23, 0x6F, 0x50, 0x2D,
+  0x2D, 0x6A, 0x29, 0x6F, 0x78, 0x84, 0x9B, 0xD2,
+  0x2C, 0x2C, 0xD6, 0x6D, 0x6D, 0x2C, 0x47, 0xA0,
+  0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
+  0xD2, 0x95, 0x55, 0xCB, 0x55, 0x2C, 0xD6, 0xA1,
+  0x95, 0x95, 0xA1, 0xD6, 0x6D, 0x6D, 0xBA, 0xF3,
+  0x8D, 0x36, 0x74, 0x36, 0xF1, 0xB8, 0x23, 0x78,
+  0x62, 0x4A, 0x29, 0x62, 0x23, 0xF1, 0x54, 0x31,
+  0x57, 0x2B, 0x90, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, 0xCB,
+  0xE6, 0x7D, 0xCA, 0xB7, 0xB8, 0x75, 0x6F, 0x6F,
+  0x76, 0x6F, 0x78, 0x81, 0x53, 0xBD, 0x6D, 0x2C,
+  0x95, 0x95, 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
+  0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
+  0xD0, 0x94, 0x94, 0x90, 0x95, 0x2C, 0xD6, 0xA1,
+  0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x2C,
+  0xD6, 0x68, 0xAB, 0x6C, 0xA4, 0x77, 0x77, 0xAD,
+  0x40, 0x53, 0x6E, 0x40, 0xB7, 0x54, 0x31, 0xD7,
+  0xAC, 0xD6, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
+  0x95, 0x2C, 0x2C, 0xA1, 0x95, 0x95, 0x2C, 0xA1,
+  0x6D, 0xD2, 0x7C, 0x54, 0xAD, 0x40, 0x6E, 0x81,
+  0x81, 0x6E, 0x36, 0xDA, 0xE8, 0xD6, 0xD6, 0x2C,
+  0x2C, 0x2C, 0xA1, 0xD6, 0x95, 0x90, 0x94, 0x47,
+  0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
+  0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
+  0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x55, 0x70, 0x95, 0x2C, 0xB2, 0xB4,
+  0xC3, 0xC3, 0x54, 0x54, 0xA9, 0x31, 0xCA, 0x2A,
+  0x95, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD6,
+  0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD,
+  0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1,
+  0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94,
+  0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
+  0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1,
+  0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95,
+  0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C,
+  0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C,
+  0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF,
+  0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1,
+  0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70,
+  0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
+  0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55,
+  0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95,
+  0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95,
+  0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95,
+  0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1,
+  0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D,
+  0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
+  0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
+  0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
+  0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95,
+  0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95,
+  0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C,
+  0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
+  0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
+  0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55,
+  0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95,
+  0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1,
+  0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C,
+  0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
+  0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55
+};
+
+#endif
+
+#ifdef INCLUDE_LINUX_LOGOBW
+
+unsigned char linux_logo_bw[] __initdata = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F,
+  0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
+  0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF,
+  0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7,
+  0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0,
+  0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80,
+  0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4,
+  0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C,
+  0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29,
+  0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F,
+  0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00,
+  0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF,
+  0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF,
+  0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19,
+  0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E,
+  0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00,
+  0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC,
+  0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF,
+  0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11,
+  0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06,
+  0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00,
+  0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1,
+  0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF,
+  0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10,
+  0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00,
+  0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00,
+  0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7,
+  0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8,
+  0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01,
+  0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00,
+  0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F,
+  0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
+  0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18,
+  0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03,
+  0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00,
+  0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99,
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF,
+  0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01,
+  0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00,
+  0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00,
+  0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40,
+  0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF,
+  0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23,
+  0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00,
+  0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80,
+  0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00,
+  0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF,
+  0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04,
+  0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10,
+  0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80,
+  0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00,
+  0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF,
+  0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00,
+  0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0,
+  0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40,
+  0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00,
+  0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF,
+  0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40,
+  0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0,
+  0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF,
+  0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F,
+  0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF,
+  0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F,
+  0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F,
+  0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07,
+  0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+};
+
+#endif
+
+#ifdef INCLUDE_LINUX_LOGO16
+
+unsigned char linux_logo16_red[] __initdata = {
+    0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5,
+    0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8
+};
+
+unsigned char linux_logo16_green[] __initdata = {
+    0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5,
+    0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8
+};
+
+unsigned char linux_logo16_blue[] __initdata = {
+    0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5,
+    0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8
+};
+
+unsigned char linux_logo16[] __initdata = {
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa1, 0x11, 0x11,
+    0x61, 0x16, 0x66, 0x66, 0x11, 0x11, 0x11, 0x11,
+    0x11, 0x11, 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xa8, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x87, 0x77, 0x77, 0x77, 0x77,
+    0x77, 0x77, 0x73, 0x33, 0x33, 0x3a, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77,
+    0x77, 0x27, 0x77, 0x77, 0x77, 0x33, 0x3a, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xa3, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x55, 0x50, 0x08, 0x33, 0x77, 0x77,
+    0x77, 0x72, 0x72, 0x27, 0x77, 0x77, 0x33, 0x33,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xa3, 0x33, 0x33, 0x77, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x58, 0x85, 0x00, 0x11, 0x11, 0xaa,
+    0xa3, 0x37, 0x77, 0x72, 0x22, 0x22, 0x77, 0x73,
+    0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3,
+    0x33, 0x37, 0x77, 0x33, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x56, 0x85, 0x00, 0x06, 0x66, 0x11,
+    0x11, 0x1a, 0xa3, 0x37, 0x77, 0x72, 0x22, 0x77,
+    0x73, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
+    0x33, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x55, 0x00, 0x00, 0x06, 0x66, 0x66,
+    0x66, 0x66, 0x11, 0x1a, 0xa3, 0x77, 0x72, 0x22,
+    0x77, 0x73, 0x3a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33,
+    0x33, 0x33, 0x33, 0xa0, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
+    0x66, 0x66, 0x66, 0x66, 0x11, 0xa3, 0x77, 0x22,
+    0x22, 0x77, 0x33, 0x33, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33,
+    0x33, 0x3a, 0xa1, 0x10, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x33,
+    0xaa, 0x11, 0x16, 0x66, 0x66, 0x61, 0x1a, 0x37,
+    0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x33,
+    0x3a, 0xa1, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x22,
+    0x22, 0x77, 0x3a, 0x11, 0x66, 0x66, 0x66, 0x1a,
+    0x37, 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, 0x3a,
+    0xa1, 0x11, 0x11, 0x10, 0x00, 0x00, 0x50, 0x00,
+    0x00, 0x05, 0x80, 0x50, 0x00, 0x00, 0x07, 0x72,
+    0x22, 0x22, 0x22, 0x73, 0xa1, 0x66, 0x66, 0x61,
+    0x1a, 0x77, 0x22, 0x27, 0x73, 0x33, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x3a, 0xaa,
+    0x11, 0x11, 0x1a, 0xa0, 0x08, 0x71, 0x05, 0x00,
+    0x00, 0x12, 0x22, 0x50, 0x00, 0x00, 0x07, 0x77,
+    0x77, 0x72, 0x22, 0x22, 0x27, 0x31, 0x16, 0x66,
+    0x61, 0x13, 0x77, 0x22, 0x77, 0x33, 0x3a, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xa1,
+    0x11, 0x1a, 0x33, 0x70, 0x07, 0x2e, 0x70, 0x00,
+    0x01, 0x44, 0x42, 0x60, 0x00, 0x00, 0x02, 0x22,
+    0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x31, 0x66,
+    0x66, 0x61, 0xa3, 0x72, 0x22, 0x77, 0x33, 0xaa,
+    0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xaa, 0x11,
+    0x1a, 0x33, 0x77, 0x30, 0x04, 0x82, 0x40, 0x00,
+    0x54, 0x48, 0x54, 0x40, 0x00, 0x00, 0x01, 0xaa,
+    0x32, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x31,
+    0x66, 0x66, 0x11, 0x37, 0x22, 0x27, 0x73, 0x3a,
+    0xaa, 0xaa, 0xa3, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
+    0xa3, 0x77, 0xaa, 0x10, 0x50, 0x08, 0x46, 0x05,
+    0x54, 0x80, 0x50, 0x42, 0x00, 0x00, 0x08, 0x66,
+    0x66, 0x1a, 0x32, 0x22, 0x22, 0x22, 0x22, 0x27,
+    0x31, 0x66, 0x66, 0x13, 0x72, 0x22, 0x77, 0x33,
+    0xaa, 0xaa, 0xaa, 0x33, 0xaa, 0xa1, 0xaa, 0xa3,
+    0x37, 0xa1, 0x1a, 0x30, 0x50, 0x06, 0x26, 0x00,
+    0x54, 0x00, 0x00, 0x44, 0x00, 0x00, 0x08, 0xe2,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, 0x22,
+    0x27, 0xa6, 0x66, 0x61, 0xa7, 0x72, 0x27, 0x73,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
+    0x31, 0x11, 0x37, 0x70, 0x02, 0x00, 0xab, 0xbb,
+    0xb6, 0x00, 0x00, 0xf4, 0x00, 0x00, 0xee, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
+    0x22, 0x23, 0x16, 0x66, 0x1a, 0x37, 0x22, 0x77,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x3a,
+    0x11, 0xa7, 0x33, 0x10, 0x04, 0x09, 0xbd, 0xdd,
+    0xbd, 0xd0, 0x04, 0x45, 0x00, 0x0e, 0xee, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
+    0x22, 0x22, 0x71, 0x66, 0x66, 0x13, 0x72, 0x27,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x11,
+    0xa3, 0x73, 0xa1, 0x60, 0x08, 0xbd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdb, 0x90, 0x00, 0x02, 0xec, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xce, 0x22,
+    0x22, 0x22, 0x27, 0xa6, 0x66, 0x61, 0x37, 0x27,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x1a,
+    0x33, 0xa1, 0x16, 0x60, 0x0b, 0xbd, 0xdd, 0xdd,
+    0xcd, 0xdd, 0xdd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xce, 0xa2,
+    0x22, 0x22, 0x22, 0x7a, 0x66, 0x66, 0x13, 0x77,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0x3a, 0x11, 0x33,
+    0xaa, 0x11, 0x66, 0x60, 0x9b, 0xdd, 0xdd, 0xdd,
+    0xcd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x61,
+    0x72, 0x22, 0x22, 0x22, 0xa1, 0x66, 0x61, 0x37,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x13, 0x3a,
+    0x11, 0x11, 0x11, 0x10, 0x5b, 0xdd, 0xdd, 0xdc,
+    0xdd, 0xdd, 0xbd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x86,
+    0x17, 0x22, 0x22, 0x22, 0x23, 0x16, 0x66, 0xaa,
+    0xaa, 0xa3, 0x3a, 0xaa, 0xaa, 0x1a, 0x3a, 0xa1,
+    0x11, 0x11, 0x1a, 0x70, 0x05, 0xbd, 0xdd, 0xdd,
+    0xdb, 0x5b, 0xdd, 0xb0, 0x00, 0x60, 0x2e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe6, 0x88,
+    0x66, 0x32, 0x22, 0x22, 0x22, 0x36, 0x66, 0x11,
+    0x33, 0x33, 0x3a, 0xaa, 0x11, 0xaa, 0xaa, 0xa1,
+    0x11, 0x1a, 0x3a, 0x60, 0x02, 0x99, 0xbb, 0xb9,
+    0x9b, 0xbb, 0xbc, 0x22, 0x00, 0x86, 0x5e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe1, 0x68,
+    0x86, 0x63, 0x22, 0x22, 0x22, 0x2a, 0x66, 0x66,
+    0x33, 0x33, 0xaa, 0xaa, 0x1a, 0xaa, 0xaa, 0x11,
+    0x1a, 0xa7, 0x68, 0x80, 0x02, 0x2b, 0xbd, 0xbb,
+    0xbb, 0xb9, 0x22, 0x22, 0x00, 0x06, 0x6e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc7, 0xa6,
+    0x88, 0x86, 0x32, 0x22, 0x22, 0x27, 0xa6, 0x66,
+    0x33, 0x3a, 0xaa, 0xa1, 0xaa, 0xaa, 0xa1, 0x11,
+    0xa3, 0xa6, 0x88, 0x80, 0x02, 0x22, 0x9b, 0xbb,
+    0xbb, 0x22, 0x24, 0xf4, 0x60, 0x00, 0x0c, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc2, 0x21,
+    0x68, 0x88, 0x63, 0x22, 0x22, 0x22, 0x71, 0x66,
+    0x33, 0x3a, 0x11, 0x11, 0xaa, 0xaa, 0x11, 0xaa,
+    0x71, 0x88, 0x88, 0x00, 0x02, 0xe2, 0x26, 0x99,
+    0x22, 0x22, 0x4f, 0xf4, 0x40, 0x00, 0x0c, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x22, 0x22,
+    0x16, 0x88, 0x86, 0xa2, 0x22, 0x22, 0x27, 0x11,
+    0x33, 0xa1, 0x11, 0x11, 0xaa, 0x31, 0x1a, 0xa3,
+    0x68, 0x88, 0x81, 0x00, 0x54, 0x42, 0x22, 0x22,
+    0x22, 0x44, 0xff, 0xff, 0x48, 0x00, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x22,
+    0x21, 0x88, 0x88, 0x6a, 0x22, 0x22, 0x22, 0x31,
+    0x3a, 0xa1, 0x11, 0x1a, 0xa3, 0x11, 0x33, 0x36,
+    0x88, 0x86, 0x30, 0x00, 0x4f, 0x44, 0x22, 0x22,
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+    0x62, 0x27, 0x37, 0x38, 0x88, 0x87, 0x55, 0x59,
+    0x95, 0x58, 0x16, 0x88, 0x8a, 0x66, 0x63, 0x68,
+    0x86, 0x67, 0x66, 0x66, 0x68, 0x88, 0x12, 0x11,
+    0x88, 0x88, 0x72, 0x77, 0x78, 0x85, 0x58, 0x17,
+    0x23, 0x32, 0x55, 0x55, 0x81, 0x13, 0x73, 0x66,
+    0x62, 0x7a, 0xaa, 0x38, 0x88, 0x58, 0x27, 0x55,
+    0x58, 0x32, 0x38, 0x88, 0x81, 0x66, 0xa2, 0x88,
+    0x86, 0x61, 0x66, 0x61, 0x66, 0x68, 0x13, 0x11,
+    0x88, 0x88, 0x12, 0x22, 0x71, 0x85, 0x58, 0x62,
+    0x23, 0xa2, 0x68, 0x88, 0x81, 0x66, 0x88, 0x88,
+    0x63, 0x2a, 0xaa, 0x28, 0x88, 0x55, 0x86, 0x61,
+    0x66, 0x66, 0x68, 0x88, 0x66, 0x66, 0x77, 0x88,
+    0x68, 0x16, 0x66, 0x62, 0x66, 0x68, 0xa1, 0x61,
+    0x88, 0x88, 0x62, 0x22, 0x22, 0x85, 0x55, 0x83,
+    0x72, 0x37, 0xa8, 0x88, 0x61, 0x66, 0x85, 0x55,
+    0x86, 0x23, 0xaa, 0x71, 0x88, 0x85, 0x88, 0x66,
+    0x88, 0x86, 0x88, 0x88, 0x16, 0x61, 0x21, 0x88,
+    0x66, 0xa6, 0x86, 0x17, 0x66, 0x66, 0x31, 0x61,
+    0x88, 0x88, 0x87, 0x72, 0x22, 0x68, 0x55, 0x86,
+    0x77, 0x77, 0x36, 0x88, 0x13, 0x68, 0x85, 0x55,
+    0x58, 0x12, 0x73, 0x72, 0x76, 0x88, 0x88, 0x68,
+    0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86,
+    0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61,
+    0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58,
+    0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55,
+    0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68,
+    0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68,
+    0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66,
+    0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88,
+    0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55,
+    0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66,
+    0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68,
+    0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66,
+    0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88,
+    0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85,
+    0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68,
+    0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88,
+    0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a
+};
+
+#endif

diff --git a/include/mpc106.h b/include/mpc106.h
new file mode 100644 (file)
index 0000000..3926f8b
--- /dev/null
+++ b/include/mpc106.h
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MPC106_PCI_H
+#define _MPC106_PCI_H
+
+/*
+ * Defines for the MPC106 PCI Config address and data registers followed by
+ * defines for the standard PCI device configuration header.
+ */
+#define PCIDEVID_MPC106                0x0
+
+/*
+ * MPC106 Registers
+ */
+#define        MPC106_REG                      0x80000000
+
+#ifdef CFG_ADDRESS_MAP_A
+#define MPC106_REG_ADDR                0x80000cf8
+#define        MPC106_REG_DATA                 0x80000cfc
+#define MPC106_ISA_IO_PHYS             0x80000000
+#define MPC106_ISA_IO_BUS              0x00000000
+#define MPC106_ISA_IO_SIZE             0x00800000
+#define MPC106_PCI_IO_PHYS             0x81000000
+#define MPC106_PCI_IO_BUS              0x01000000
+#define MPC106_PCI_IO_SIZE             0x3e800000
+#define MPC106_PCI_MEM_PHYS            0xc0000000
+#define MPC106_PCI_MEM_BUS             0x00000000
+#define MPC106_PCI_MEM_SIZE            0x3f000000
+#define        MPC106_PCI_MEMORY_PHYS          0x00000000
+#define        MPC106_PCI_MEMORY_BUS           0x80000000
+#define        MPC106_PCI_MEMORY_SIZE          0x80000000
+#else
+#define MPC106_REG_ADDR                0xfec00cf8
+#define        MPC106_REG_DATA                 0xfee00cfc
+#define MPC106_ISA_MEM_PHYS            0xfd000000
+#define MPC106_ISA_MEM_BUS             0x00000000
+#define MPC106_ISA_MEM_SIZE            0x01000000
+#define MPC106_ISA_IO_PHYS             0xfe000000
+#define MPC106_ISA_IO_BUS              0x00000000
+#define MPC106_ISA_IO_SIZE             0x00800000
+#define MPC106_PCI_IO_PHYS             0xfe800000
+#define MPC106_PCI_IO_BUS              0x00800000
+#define MPC106_PCI_IO_SIZE             0x00400000
+#define MPC106_PCI_MEM_PHYS            0x80000000
+#define MPC106_PCI_MEM_BUS             0x80000000
+#define MPC106_PCI_MEM_SIZE            0x7d000000
+#define        MPC106_PCI_MEMORY_PHYS          0x00000000
+#define        MPC106_PCI_MEMORY_BUS           0x00000000
+#define MPC106_PCI_MEMORY_SIZE         0x40000000
+#endif
+
+#define CMD_SERR                       0x0100
+#define PCI_CMD_MASTER                 0x0004
+#define PCI_CMD_MEMEN                  0x0002
+#define PCI_CMD_IOEN                   0x0001
+
+#define PCI_STAT_NO_RSV_BITS           0xffff
+
+#define PCI_BUSNUM                     0x40
+#define PCI_SUBBUSNUM                  0x41
+#define PCI_DISCOUNT                   0x42
+
+#define PCI_PICR1                      0xA8
+#define PICR1_CF_CBA(value)            ((value & 0xff) << 24)
+#define PICR1_CF_BREAD_WS(value)       ((value & 0x3) << 22)
+#define PICR1_PROC_TYPE_603            0x40000
+#define PICR1_PROC_TYPE_604            0x60000
+#define PICR1_MCP_EN                   0x800
+#define PICR1_CF_DPARK                 0x200
+#define PICR1_CF_LOOP_SNOOP            0x10
+#define PICR1_CF_L2_COPY_BACK          0x2
+#define PICR1_CF_L2_CACHE_MASK         0x3
+#define PICR1_CF_APARK                 0x8
+#define PICR1_ADDRESS_MAP              0x10000
+#define PICR1_XIO_MODE                 0x80000
+#define PICR1_CF_CACHE_1G              0x200000
+
+#define PCI_PICR2                      0xAC
+#define PICR2_CF_SNOOP_WS(value)       ((value & 0x3) << 18)
+#define PICR2_CF_FLUSH_L2              0x10000000
+#define PICR2_CF_L2_HIT_DELAY(value)   ((value & 0x3) << 9)
+#define PICR2_CF_APHASE_WS(value)      ((value & 0x3) << 2)
+#define PICR2_CF_INV_MODE              0x00001000
+#define PICR2_CF_MOD_HIGH              0x00020000
+#define PICR2_CF_HIT_HIGH              0x00010000
+#define PICR2_L2_SIZE_256K             0x00000000
+#define PICR2_L2_SIZE_512K             0x00000010
+#define PICR2_L2_SIZE_1MB              0x00000020
+#define PICR2_L2_EN                    0x40000000
+#define PICR2_L2_UPDATE_EN             0x80000000
+#define PICR2_CF_ADDR_ONLY_DISABLE     0x00004000
+#define PICR2_CF_FAST_CASTOUT          0x00000080
+#define PICR2_CF_WDATA                 0x00000001
+#define PICR2_CF_DATA_RAM_PBURST       0x00400000
+
+/*
+ * Memory controller
+ */
+#define MPC106_MCCR1                   0xF0
+#define MCCR1_TYPE_EDO                 0x00020000
+#define MCCR1_BK0_9BITS                        0x0
+#define MCCR1_BK0_10BITS               0x1
+#define MCCR1_BK0_11BITS               0x2
+#define MCCR1_BK0_12BITS               0x3
+#define MCCR1_BK1_9BITS                        0x0
+#define MCCR1_BK1_10BITS               0x4
+#define MCCR1_BK1_11BITS               0x8
+#define MCCR1_BK1_12BITS               0xC
+#define MCCR1_BK2_9BITS                        0x00
+#define MCCR1_BK2_10BITS               0x10
+#define MCCR1_BK2_11BITS               0x20
+#define MCCR1_BK2_12BITS               0x30
+#define MCCR1_BK3_9BITS                        0x00
+#define MCCR1_BK3_10BITS               0x40
+#define MCCR1_BK3_11BITS               0x80
+#define MCCR1_BK3_12BITS               0xC0
+#define MCCR1_MEMGO                    0x00080000
+
+#define MPC106_MCCR2                   0xF4
+#define MPC106_MCCR3                   0xF8
+#define MPC106_MCCR4                   0xFC
+
+#define MPC106_MSAR1                   0x80
+#define MPC106_EMSAR1                  0x88
+#define MPC106_EMSAR2                  0x8C
+#define MPC106_MEAR1                   0x90
+#define MPC106_EMEAR1                  0x98
+#define MPC106_EMEAR2                  0x9C
+
+#define MPC106_MBER                    0xA0
+#define MBER_BANK0                     0x1
+#define MBER_BANK1                     0x2
+#define MBER_BANK2                     0x4
+#define MBER_BANK3                     0x8
+
+#endif
+

diff --git a/rtc/mk48t59.c b/rtc/mk48t59.c
new file mode 100644 (file)
index 0000000..2d3c278
--- /dev/null
+++ b/rtc/mk48t59.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for the MK48T59 RTC
+ */
+
+#undef RTC_DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <rtc.h>
+#include <mk48t59.h>
+
+#if defined(CONFIG_RTC_MK48T59)
+
+#if defined(CONFIG_BAB7xx)
+
+static uchar rtc_read (short reg)
+{
+       out8(RTC_PORT_ADDR0, reg & 0xFF);
+       out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF);
+       return in8(RTC_PORT_DATA);
+}
+
+static void rtc_write (short reg, uchar val)
+{
+       out8(RTC_PORT_ADDR0, reg & 0xFF);
+       out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF);
+       out8(RTC_PORT_DATA, val);
+}
+
+#elif defined(CONFIG_PCIPPC2)
+
+#include "../board/pcippc2/pcippc2.h"
+
+static uchar rtc_read (short reg)
+{
+       return in8(RTC(reg));
+}
+
+static void rtc_write (short reg, uchar val)
+{
+       out8(RTC(reg),val);
+}
+
+#else
+# error Board specific rtc access functions should be supplied
+#endif
+
+static unsigned bcd2bin (uchar n)
+{
+       return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+static unsigned char bin2bcd (unsigned int n)
+{
+       return (((n / 10) << 4) | (n % 10));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void *nvram_read(void *dest, const short src, size_t count)
+{
+       uchar *d = (uchar *) dest;
+       short s = src;
+
+       while (count--)
+               *d++ = rtc_read(s++);
+
+       return dest;
+}
+
+void nvram_write(short dest, const void *src, size_t count)
+{
+       short d = dest;
+       uchar *s = (uchar *) src;
+
+       while (count--)
+               rtc_write(d++, *s++);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+/* ------------------------------------------------------------------------- */
+
+void rtc_get (struct rtc_time *tmp)
+{
+       uchar save_ctrl_a;
+       uchar sec, min, hour, mday, wday, mon, year;
+
+       /* Simple: freeze the clock, read it and allow updates again */
+       save_ctrl_a = rtc_read(RTC_CONTROLA);
+
+       /* Set the register to read the value. */
+       save_ctrl_a |= RTC_CA_READ;
+       rtc_write(RTC_CONTROLA, save_ctrl_a);
+
+       sec             = rtc_read (RTC_SECONDS);
+       min             = rtc_read (RTC_MINUTES);
+       hour    = rtc_read (RTC_HOURS);
+       mday    = rtc_read (RTC_DAY_OF_MONTH);
+       wday    = rtc_read (RTC_DAY_OF_WEEK);
+       mon             = rtc_read (RTC_MONTH);
+       year    = rtc_read (RTC_YEAR);
+
+       /* re-enable update */
+       save_ctrl_a &= ~RTC_CA_READ;
+       rtc_write(RTC_CONTROLA, save_ctrl_a);
+
+#ifdef RTC_DEBUG
+       printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
+               "hr: %02x min: %02x sec: %02x\n",
+               year, mon, mday, wday,
+               hour, min, sec );
+#endif
+       tmp->tm_sec  = bcd2bin (sec  & 0x7F);
+       tmp->tm_min  = bcd2bin (min  & 0x7F);
+       tmp->tm_hour = bcd2bin (hour & 0x3F);
+       tmp->tm_mday = bcd2bin (mday & 0x3F);
+       tmp->tm_mon  = bcd2bin (mon & 0x1F);
+       tmp->tm_year = bcd2bin (year);
+       tmp->tm_wday = bcd2bin (wday & 0x07);
+       if(tmp->tm_year<70)
+               tmp->tm_year+=2000;
+       else
+               tmp->tm_year+=1900;
+       tmp->tm_yday = 0;
+       tmp->tm_isdst= 0;
+#ifdef RTC_DEBUG
+       printf ( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+               tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+               tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+}
+
+void rtc_set (struct rtc_time *tmp)
+{
+       uchar save_ctrl_a;
+
+#ifdef RTC_DEBUG
+       printf ( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+               tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+               tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+       save_ctrl_a = rtc_read(RTC_CONTROLA);
+
+       save_ctrl_a |= RTC_CA_WRITE;
+       rtc_write(RTC_CONTROLA, save_ctrl_a); /* disables the RTC to update the regs */
+
+       rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100));
+       rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon));
+
+       rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
+       rtc_write (RTC_DAY_OF_MONTH, bin2bcd(tmp->tm_mday));
+       rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour));
+       rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min ));
+       rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec ));
+
+       save_ctrl_a &= ~RTC_CA_WRITE;
+       rtc_write(RTC_CONTROLA, save_ctrl_a); /* enables the RTC to update the regs */
+}
+
+void rtc_reset (void)
+{
+       uchar control_b;
+
+       /*
+        * Start oscillator here.
+        */
+       control_b = rtc_read(RTC_CONTROLB);
+
+       control_b &= ~RTC_CB_STOP;
+       rtc_write(RTC_CONTROLB, control_b);
+}
+
+void rtc_set_watchdog(short multi, short res)
+{
+       uchar wd_value;
+
+       wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3);
+       rtc_write(RTC_WATCHDOG, wd_value);
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_DATE) */
+#endif /* CONFIG_RTC_MK48T59 */