fpga: zynqpl: Check fpga config completion

This patch checks fpga config completion when a bitstream is loaded
into PL.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 4ab354bbba4b5991fed88be6e6d80969a7e45fcf..de71969399fe0ad2c05203a9c4b3ab103a01de71 100644 (file)
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -514,6 +514,8 @@ struct xilinx_fpga_op zynq_op = {
 int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
                      u8 bstype)
 {
+       u32 isr_status, ts;
+
        if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
                printf("%s: src and dst addr should be > 1M\n",
                       __func__);
@@ -544,8 +546,21 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
        if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
                return FPGA_FAIL;
 
-       writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),
-              &devcfg_base->ctrl);
+       if (bstype == BIT_FULL) {
+               isr_status = readl(&devcfg_base->int_sts);
+               /* Check FPGA configuration completion */
+               ts = get_timer(0);
+               while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
+                       if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+                               printf("%s: Timeout wait for FPGA to config\n",
+                                      __func__);
+                               return FPGA_FAIL;
+                       }
+                       isr_status = readl(&devcfg_base->int_sts);
+               }
+               printf("%s: FPGA config done\n", __func__);
+               zynq_slcr_devcfg_enable();
+       }
 
        return FPGA_SUCCESS;
 }