u32_env nvlim;
u32_env icache;
u32_env dcache;
+ u32_env l2_cache;
};
/*
{ "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim },
{ "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache },
{ "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
+#if defined(CONFIG_BOARD_HSDK_4XD)
+ { "l2_cache_ena", ENV_HEX, true, 0, 1, &env_common.l2_cache },
+#endif /* CONFIG_BOARD_HSDK_4XD */
{}
};
return get_board_type_runtime() == type_req;
}
+static bool is_board_match_config(enum board_type type_req)
+{
+ return get_board_type_config() == type_req;
+}
+
static const char * board_name(enum board_type type)
{
switch (type) {
flush_n_invalidate_dcache_all();
}
+static void init_cluster_slc(void)
+{
+ /* ARC HS38 doesn't support SLC disabling */
+ if (!is_board_match_config(T_BOARD_HSDK_4XD))
+ return;
+
+ if (env_common.l2_cache.val)
+ slc_enable();
+ else
+ slc_disable();
+}
+
static void init_master_icache(void)
{
if (icache_status()) {
* cores.
*/
init_cluster_nvlim();
+ init_cluster_slc();
}
static int check_master_cpu_id(void)