net: zynq_gem: Move RCLK details out of driver

The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index b4c11c324c01d6ea6cd9801bef1339aff75a21a0..6710d92c3441a651ab0f968f435628c745666c65 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -50,7 +50,7 @@ void zynq_slcr_cpu_reset(void)
 }
 
 /* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk)
 {
        zynq_slcr_unlock();
 
@@ -63,12 +63,12 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
                /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
                writel(clk, &slcr_base->gem1_clk_ctrl);
                /* Configure GEM_RCLK_CTRL */
-               writel(rclk, &slcr_base->gem1_rclk_ctrl);
+               writel(1, &slcr_base->gem1_rclk_ctrl);
        } else {
                /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
                writel(clk, &slcr_base->gem0_clk_ctrl);
                /* Configure GEM_RCLK_CTRL */
-               writel(rclk, &slcr_base->gem0_rclk_ctrl);
+               writel(1, &slcr_base->gem0_rclk_ctrl);
        }
        udelay(100000);
 out:

diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 8f925af8a41a88689c2fb473f0ef1757ac451e7f..a485d790a32795b2c834a2b8b7c668bbb30fba65 100644 (file)
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -10,7 +10,7 @@
 extern void zynq_slcr_lock(void);
 extern void zynq_slcr_unlock(void);
 extern void zynq_slcr_cpu_reset(void);
-extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_boot_mode(void);

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 381bca459e161f0d72b926bc2bbc08b712b142d3..2eb9e7d1ef39acdacff63e4a5778df37aa0f8819 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -270,7 +270,7 @@ static int zynq_gem_setup_mac(struct eth_device *dev)
 
 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 {
-       u32 i, rclk, clk = 0;
+       u32 i, clk = 0;
        struct phy_device *phydev;
        const u32 stat_size = (sizeof(struct zynq_gem_regs) -
                                offsetof(struct zynq_gem_regs, stat)) / 4;
@@ -348,17 +348,14 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
        case SPEED_1000:
                writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
                       &regs->nwcfg);
-               rclk = (0 << 4) | (1 << 0);
                clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
                break;
        case SPEED_100:
                clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
                                ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
-               rclk = 1 << 0;
                clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
                break;
        case SPEED_10:
-               rclk = 1 << 0;
                /* FIXME untested */
                clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
                break;
@@ -367,7 +364,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
        /* Change the rclk and clk only not using EMIO interface */
        if (!priv->emio)
                zynq_slcr_gem_clk_setup(dev->iobase !=
-                                       ZYNQ_GEM_BASEADDR0, rclk, clk);
+                                       ZYNQ_GEM_BASEADDR0, clk);
 
        setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
                                        ZYNQ_GEM_NWCTRL_TXEN_MASK);