/* SCC registers */
#define RENESAS_SDHI_SCC_DTCNTL 0x800
-#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
-#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
-#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
+#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
+#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
+#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
#define RENESAS_SDHI_SCC_TAPSET 0x804
#define RENESAS_SDHI_SCC_DT2FF 0x808
#define RENESAS_SDHI_SCC_CKSEL 0x80c
-#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
-#define RENESAS_SDHI_SCC_RVSCNTL 0x810
-#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
+#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
+#define RENESAS_SDHI_SCC_RVSCNTL 0x810
+#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
#define RENESAS_SDHI_SCC_RVSREQ 0x814
-#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
+#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
#define RENESAS_SDHI_SCC_SMPCMP 0x818
-#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
-#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
-#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
+#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
+#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
+#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
#define RENESAS_SDHI_MAX_TAP 3