#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init,
#endif
-#ifdef CONFIG_FSL_CLK
+#ifdef CONFIG_SYS_FSL_CLK
get_clocks,
#endif
#ifdef CONFIG_M68K
--- /dev/null
+Freescale system clock options
+
+ - CONFIG_SYS_FSL_CLK
+ Enable to call get_clocks() in board_init_f() for
+ non-PPC platforms and PCC 8xx platforms such as
+ TQM866M and TQM885D.
#define CONFIG_BSC9132
#endif
-#define CONFIG_FSL_CLK
#define CONFIG_MISC_INIT_R
#ifdef CONFIG_SDCARD
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
/*
* High Level Configuration Options
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
/*
* High Level Configuration Options
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_PHYS_64BIT
#endif
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_P1010
#define CONFIG_E500 /* BOOKE e500 family */
#include "../board/freescale/common/ics307_clk.h"
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_PPC_P2041
-#define CONFIG_FSL_CLK
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_MP /* support multiple processors */
#define CONFIG_PHYS_64BIT
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_FSL_CLK
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP 1
#define CONFIG_MP /* support multiple processors */
#define CONFIG_PHYS_64BIT
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_FSL_CLK
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP 1
#define CONFIG_T1040QDS
#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_T104xRDB
#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_E500 /* BOOKE e500 family */
#include <asm/config_mpc85xx.h>
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_FSL_CLK
#define CONFIG_MMC
#define CONFIG_USB_EHCI
#if defined(CONFIG_PPC_T2080)
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_T2080RDB
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_FSL_CLK
#define CONFIG_MMC
#define CONFIG_USB_EHCI
#define CONFIG_FSL_SATA_V2
#define CONFIG_T4240QDS
#define CONFIG_PHYS_64BIT
-#define CONFIG_FSL_CLK
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
#define CONFIG_T4240RDB
#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_FSL_ELBC
#define CONFIG_PCI
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_P1022
#define CONFIG_CONTROLCENTERD
#define CONFIG_MP /* support multiple processors */
-#define CONFIG_FSL_CLK
#define CONFIG_SYS_NO_FLASH
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#include "../board/freescale/common/ics307_clk.h"
#define CONFIG_IDENT_STRING " hrcon 0.01"
-#define CONFIG_FSL_CLK
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_ARMV7_PSCI
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ARMV7_PSCI
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
unsigned long get_board_ddr_clk(void);
#endif
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
unsigned long get_board_sys_clk(void);
#endif
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ 133333333
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_FIT
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0x81200000
#define CONFIG_MXC_GPIO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_TIMER_RATE 32768
#define CONFIG_SYS_TIMER_COUNTER \
#define CONFIG_MX35
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_OF_LIBFDT
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* ATAGs */
#define CONFIG_CMDLINE_TAG
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SYSCOUNTER_TIMER
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+#define CONFIG_SYS_FSL_CLK
/* Enable iomux-lpsr support */
#define CONFIG_IOMUX_LPSR
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_P1025
#define CONFIG_MX53
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_OF_LIBFDT
#define CONFIG_MXC_GPIO
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_MACH_TYPE 4146
/* High Level Configuration Options */
#define CONFIG_MX35
#define CONFIG_MX35_HCLK_FREQ 24000000
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_CACHELINE_SIZE 32