Clean config headers from old and not needed defines

diff --git a/u-boot/include/configs/ap143.h b/u-boot/include/configs/ap143.h
index f8b39f8026412470b5d083cfa584e6de2a258776..92be783a1f6275b53e03398f5379ccbec74f3956 100644 (file)
--- a/u-boot/include/configs/ap143.h
+++ b/u-boot/include/configs/ap143.h
@@ -188,11 +188,6 @@
 #define CONFIG_NETCONSOLE
 #define CONFIG_NETCONSOLE_PORT 6666
 
-/*modify from 0x4138 to 0x40c3, ddr refresh interval: 12uS to 7.8uS. by wkp 
-  from Li Guanwen, 30Dec14. */
-//#define CFG_DDR_REFRESH_VAL          0x40c3 (??????????????????)
-#define CFG_DDR_REFRESH_VAL            0x4138
-
 /*
  * Web Failsafe configuration
  */

diff --git a/u-boot/include/configs/ar7240.h b/u-boot/include/configs/ar7240.h
index ee7adfd6cbaa426378e9720eb5d11948923324b0..0966e245a10ede0b760ef8be0f87c34868c9c75b 100644 (file)
--- a/u-boot/include/configs/ar7240.h
+++ b/u-boot/include/configs/ar7240.h
@@ -44,46 +44,6 @@
        #define SILENT_ENV_VARIABLE     ""
 #endif
 
-/*
- ** PLL Config for different CPU/DDR/AHB frequencies
- */
-#define CFG_PLL_200_200_100            1
-#define CFG_PLL_200_200_200            2
-#define CFG_PLL_225_225_112            3
-#define CFG_PLL_225_225_225            4
-#define CFG_PLL_250_250_125            5
-#define CFG_PLL_250_250_250            6
-#define CFG_PLL_300_300_150            7
-#define CFG_PLL_325_325_162            8
-#define CFG_PLL_350_350_175            9
-#define CFG_PLL_360_360_180            10
-#define CFG_PLL_380_380_190            11
-#define CFG_PLL_400_400_200            12
-#define CFG_PLL_412_412_206            13
-#define CFG_PLL_420_420_210            14
-#define CFG_PLL_425_425_212            15
-#define CFG_PLL_437_437_218            16
-#define CFG_PLL_440_440_220            17
-#define CFG_PLL_450_450_225            18
-#define CFG_PLL_460_460_230            19
-#define CFG_PLL_475_475_237            20
-#define CFG_PLL_480_480_240            21
-#define CFG_PLL_487_487_243            22
-#define CFG_PLL_500_500_250            23
-#define CFG_PLL_500_250_250            24
-#define CFG_PLL_520_520_260            25
-#define CFG_PLL_525_262_131            26
-#define CFG_PLL_560_280_140            27
-#define CFG_PLL_580_290_145            28
-#define CFG_PLL_600_300_200            29
-
-// WASP
-#define CFG_PLL_566_400_200                    101
-#define CFG_PLL_566_500_250                    102
-#define CFG_PLL_600_1_2G_400_200       103
-#define CFG_PLL_560_480_240                    104
-#define CFG_PLL_533_400_200                    105
-
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */

diff --git a/u-boot/include/configs/db12x.h b/u-boot/include/configs/db12x.h
index 72ccff3201d3b15146df53f1b796383d34a5d414..5b9b2b15af79732f0c77c8a9609aa78570953afc 100644 (file)
--- a/u-boot/include/configs/db12x.h
+++ b/u-boot/include/configs/db12x.h
@@ -194,31 +194,6 @@
 #define CONFIG_NETCONSOLE
 #define CONFIG_NETCONSOLE_PORT 6666
 
-/* DDR settings for WASP */
-#define CFG_DDR_REFRESH_VAL     0x4270
-#define CFG_DDR_CONFIG_VAL      0xc7bc8cd0
-#define CFG_DDR_MODE_VAL_INIT   0x133
-#define CFG_DDR_EXT_MODE_VAL    0x0
-#define CFG_DDR_MODE_VAL        0x33
-#define CFG_DDR_TRTW_VAL        0x1f
-#define CFG_DDR_TWTR_VAL        0x1e
-#define CFG_DDR_CONFIG2_VAL     0x9dd0e6a8
-
-#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32     0xff
-#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16     0xffff
-
-#if DDR2_32BIT_SUPPORT
-       #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL         CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32
-#else
-       #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL         CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16
-#endif
-
-#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL                0xffff
-#define CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL       0xffffffff
-
-/* DDR2 Init values */
-#define CFG_DDR2_EXT_MODE_VAL    0x402
-
 #define CONFIG_NET_MULTI
 
 #ifdef CFG_ATHRS27_PHY