mtd: mxs_nand: fix the gf_13/14 definition issue
authorHan Xu <han.xu@nxp.com>
Mon, 4 May 2020 14:08:58 +0000 (22:08 +0800)
committerStefano Babic <sbabic@denx.de>
Sun, 10 May 2020 18:55:20 +0000 (20:55 +0200)
gf_13/14 mask was not set correctly in register definition.

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/include/asm/mach-imx/regs-bch.h
drivers/mtd/nand/raw/mxs_nand.c
include/mxs_nand.h

index 4b99edbb3df7d3702159f5ebd66478789e5cb3fe..664fb9fd4dc72d2ecb35bb7273589deb19ec5581 100644 (file)
@@ -151,9 +151,9 @@ struct mxs_bch_regs {
 #define        BCH_FLASHLAYOUT0_ECC0_ECC28                     (0xe << 12)
 #define        BCH_FLASHLAYOUT0_ECC0_ECC30                     (0xf << 12)
 #define        BCH_FLASHLAYOUT0_ECC0_ECC32                     (0x10 << 12)
-#define        BCH_FLASHLAYOUT0_GF13_0_GF14_1                  (1 << 10)
+#define        BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK             BIT(10)
 #define        BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET           10
-#define        BCH_FLASHLAYOUT0_DATA0_SIZE_MASK                0xfff
+#define        BCH_FLASHLAYOUT0_DATA0_SIZE_MASK                0x3ff
 #define        BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET              0
 
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_MASK                 (0xffff << 16)
@@ -182,9 +182,9 @@ struct mxs_bch_regs {
 #define        BCH_FLASHLAYOUT1_ECCN_ECC28                     (0xe << 12)
 #define        BCH_FLASHLAYOUT1_ECCN_ECC30                     (0xf << 12)
 #define        BCH_FLASHLAYOUT1_ECCN_ECC32                     (0x10 << 12)
-#define        BCH_FLASHLAYOUT1_GF13_0_GF14_1                  (1 << 10)
+#define        BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK             BIT(10)
 #define        BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET           10
-#define        BCH_FLASHLAYOUT1_DATAN_SIZE_MASK                0xfff
+#define        BCH_FLASHLAYOUT1_DATAN_SIZE_MASK                0x3ff
 #define        BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET              0
 
 #define        BCH_DEBUG0_RSVD1_MASK                           (0x1f << 27)
index facedf92c5c87295229f3f655830dfb2ce6e7e9b..1b66636a4f4c41be88fcbbd3725f691f1f064256 100644 (file)
@@ -1474,6 +1474,8 @@ void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l)
                        BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET);
        l->eccn = (tmp & BCH_FLASHLAYOUT1_ECCN_MASK) >>
                        BCH_FLASHLAYOUT1_ECCN_OFFSET;
+       l->gf_len = (tmp & BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK) >>
+                    BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
 }
 
 /*
index 1ac628d064719745a65a371dfa6256e5ab586cc6..21d68a909d7d53b29038fff537c49a8a3655fddb 100644 (file)
@@ -88,6 +88,7 @@ struct mxs_nand_layout {
        u32 ecc0;
        u32 datan_size;
        u32 eccn;
+       u32 gf_len;
 };
 
 int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);