armv8/ls1043aqds: add QSPI support in SD boot
authorGong Qianyu <Qianyu.Gong@freescale.com>
Mon, 25 Jan 2016 07:16:06 +0000 (15:16 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 27 Jan 2016 16:28:55 +0000 (08:28 -0800)
QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/soc.c
arch/arm/dts/fsl-ls1043a.dtsi
board/freescale/ls1043aqds/MAINTAINERS
board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg [new file with mode: 0644]
configs/ls1043aqds_sdcard_qspi_defconfig [new file with mode: 0644]
include/configs/ls1043a_common.h
include/configs/ls1043aqds.h

index d97a445179ae883094f0374e005a62444b163ae9..7ff01481bef68b2ebbf0b3fbd0ba960288e7bd37 100644 (file)
@@ -222,6 +222,9 @@ void fsl_lsch2_early_init_f(void)
        init_early_memctl_regs();       /* tighten IFC timing */
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+       out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
        /* Make SEC reads and writes snoopable */
        setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
                     SCFG_SNPCNFGCR_SECWRSNP);
index 12ea0ab541ff58c62672c586df6bd2981bedc1c6..66b409a05c21090e4715c5b8013d1cfc2cae5755 100644 (file)
                        clock-names = "ipg";
                        status = "disabled";
                };
+               qspi: quadspi@1550000 {
+                       compatible = "fsl,vf610-qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x1550000 0x10000>,
+                               <0x40000000 0x4000000>;
+                       num-cs = <2>;
+                       big-endian;
+                       status = "disabled";
+               };
        };
 };
index 0c7f648b6cbcdad7578fa305cae78c1567da51e5..868bb7297997e4d6a1f621294f40ce490c4c4a9d 100644 (file)
@@ -7,3 +7,4 @@ F:      configs/ls1043aqds_defconfig
 F:     configs/ls1043aqds_nor_ddr3_defconfig
 F:     configs/ls1043aqds_nand_defconfig
 F:     configs/ls1043aqds_sdcard_ifc_defconfig
+F:     configs/ls1043aqds_sdcard_qspi_defconfig
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
new file mode 100644 (file)
index 0000000..7783521
--- /dev/null
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable QSPI; disable IFC
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
+00000000 00000000 00000000 00038800
+20124000 00001100 00000096 00000001
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
new file mode 100644 (file)
index 0000000..09fb1ed
--- /dev/null
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_SYS_NS16550=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
index 35d97508a8b424172b322ccb3463516288f3224c..8900daee9501d443e7eeb3db0d146cb02c6a9860 100644 (file)
 #endif
 
 /* IFC */
+#ifndef CONFIG_SD_BOOT_QSPI
 #define CONFIG_FSL_IFC
 /*
  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 #endif
+#endif
 
 /* I2C */
 #define CONFIG_CMD_I2C
 #define CONFIG_SPI_FLASH_STMICRO       /* cs0 */
 #define CONFIG_SPI_FLASH_SST           /* cs1 */
 #define CONFIG_SPI_FLASH_EON           /* cs2 */
+#ifndef CONFIG_SD_BOOT_QSPI
 #define CONFIG_SF_DEFAULT_BUS          1
 #define CONFIG_SF_DEFAULT_CS           0
 #endif
+#endif
 
 #define CONFIG_FSL_CAAM                        /* Enable SEC/CAAM */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR                0x400d0000
+#define CONFIG_ENV_SPI_BUS             0
+#define CONFIG_ENV_SPI_CS              0
+#define CONFIG_ENV_SPI_MAX_HZ          1000000
+#define CONFIG_ENV_SPI_MODE            0x03
+#else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 /* FMan fireware Pre-load address */
 #define CONFIG_SYS_FMAN_FW_ADDR                0x60300000
+#endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
 #define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif
index e6725e3be8af23d2a08275bdaa32737827ce2199..60d189bf09cb39f58ff3be787dee1570a6fc9350 100644 (file)
@@ -85,8 +85,13 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW \
+       board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
+#else
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
 #endif
+#endif
 
 /* LPUART */
 #ifdef CONFIG_LPUART
@@ -113,6 +118,7 @@ unsigned long get_board_ddr_clk(void);
 /*
  * IFC Definitions
  */
+#ifndef CONFIG_SD_BOOT_QSPI
 #define CONFIG_SYS_NOR0_CSPR_EXT       (0x0)
 #define CONFIG_SYS_NOR0_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
                                CSPR_PORT_SIZE_16 | \
@@ -196,6 +202,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NAND
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+#endif
 
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SPL_PAD_TO              0x20000         /* block aligned */
@@ -203,6 +210,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (640 << 10)
 #endif
 
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
 /*
  * QIXIS Definitions
  */
@@ -219,6 +232,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_ALTBANK            0x04
 #define QIXIS_LBMAP_NAND               0x09
 #define QIXIS_LBMAP_SD                 0x00
+#define QIXIS_LBMAP_SD_QSPI            0xff
 #define QIXIS_RCW_SRC_NAND             0x106
 #define QIXIS_RCW_SRC_SD               0x040
 #define QIXIS_RST_CTL_RESET            0x41
@@ -347,6 +361,16 @@ unsigned long get_board_ddr_clk(void);
 #define VDD_MV_MIN                     819
 #define VDD_MV_MAX                     1212
 
+/* QSPI device */
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE            (1 << 24)
+#define FSL_QSPI_FLASH_NUM             2
+#endif
+#endif
+
 /*
  * Miscellaneous configurable options
  */