#define CONFIG_IMX_THERMAL
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_SIZE SZ_32M
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
#define CONFIG_IMX_THERMAL
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_LE
-#define CONFIG_SYS_FSL_QSPI_AHB
-#ifdef CONFIG_MX6SX_SABRESD_REVA
-#define FSL_QSPI_FLASH_SIZE SZ_16M
-#else
-#define FSL_QSPI_FLASH_SIZE SZ_32M
-#endif
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MXS
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZE SZ_32M
-#endif
-
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_SOFT_SPI
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZE SZ_32M
-#endif
-
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
#define CONFIG_VIDEO_BMP_LOGO
#endif
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZE SZ_64M
-#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
-#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
-#endif
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* QSPI Configs*/
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE (SZ_16M)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
#define CONFIG_LOADADDR 0x82000000
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
-/* QSPI Configs*/
-
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC