Initialize second PHY on OpenRD-Client and OpenRD-Ultimate
authorClint Adams <[clint@debian.org]>
Fri, 6 May 2011 16:36:47 +0000 (22:06 +0530)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 11 May 2011 21:03:16 +0000 (23:03 +0200)
Though the OpenRD-Base only has one gigabit Ethernet port,
both the OpenRD-Client and OpenRD-Ultimate each have two.

On the Ultimate, the PHY addresses are consecutive, but
on the Client they are not.

(based on
<62a0952ce368acc725063a00a5ec680a639d6c27.1301040318.git.julian.pidancet@citrix.com>
<ad0a2dc1e422698b005d6f0ceb6dd6f75a87e00a.1301040318.git.julian.pidancet@citrix.com>
)

Signed-off-by: Clint Adams <clint@debian.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Julian Pidancet <julian.pidancet@citrix.com>
board/Marvell/openrd/openrd.c
include/configs/openrd.h

index 14ca88e5b2dee154172668b572108d3fcbfd77dc..87939decf3cc49878ed89f3968b97195c0cecb78 100644 (file)
@@ -124,12 +124,11 @@ int board_init(void)
 }
 
 #ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
+/* Configure and enable MV88E1116/88E1121 PHY */
+void mv_phy_init(char *name)
 {
        u16 reg;
        u16 devadr;
-       char *name = "egiga0";
 
        if (miiphy_set_current_dev(name))
                return;
@@ -154,6 +153,24 @@ void reset_phy(void)
        /* reset the phy */
        miiphy_reset(name, devadr);
 
-       printf("88E1116 Initialized on %s\n", name);
+       printf(PHY_NO" Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+       mv_phy_init("egiga0");
+
+#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+       /* Kirkwood ethernet driver is written with the assumption that in case
+        * of multiple PHYs, their addresses are consecutive. But unfortunately
+        * in case of OpenRD-Client, PHY addresses are not consecutive.*/
+       miiphy_write("egiga1", 0xEE, 0xEE, 24);
+#endif
+
+#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
+       defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+       /* configure and initialize both PHY's */
+       mv_phy_init("egiga1");
+#endif
 }
 #endif /* CONFIG_RESET_PHY_R */
index 72997498ba8f4c3c23143562767a219668dd82d7..8d860678dadf547c206a80e18904ae18d6a37a1c 100644 (file)
  * Ethernet Driver configuration
  */
 #ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS     {1, 0}  /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR    0x8
+# ifdef CONFIG_BOARD_IS_OPENRD_BASE
+#  define CONFIG_MVGBE_PORTS   {1, 0}  /* enable port 0 only */
+# else
+#  define CONFIG_MVGBE_PORTS   {1, 1}  /* enable both ports */
+# endif
+# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
+#  define CONFIG_PHY_BASE_ADR  0x0
+#  define PHY_NO               "88E1121"
+# else
+#  define CONFIG_PHY_BASE_ADR  0x8
+#  define PHY_NO               "88E1116"
+# endif
 #endif /* CONFIG_CMD_NET */
 
 /*