ARM: MediaTek: Add support for MediaTek MT8518 SoC

Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>

diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
new file mode 100644 (file)
index 0000000..9f56122
--- /dev/null
+++ b/arch/arm/dts/mt8518.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+#include <dt-bindings/clock/mt8518-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       compatible = "mediatek,mt8518";
+       interrupt-parent = <&sysirq>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+
+
+       topckgen: clock-controller@10000000 {
+               compatible = "mediatek,mt8518-topckgen";
+               reg = <0x10000000 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       gic: interrupt-controller@0c000000 {
+                compatible = "arm,gic-v3";
+               #interrupt-cells = <3>;
+               interrupt-parent = <&gic>;
+               interrupt-controller;
+               reg = <0xc000000 0x40000>,      /* GICD */
+                         <0xc100000 0x200000>; /* GICR */
+               interrupts = <GIC_PPI 9
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
+       sysirq: interrupt-controller@10200a80 {
+               compatible = "mediatek,sysirq";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               interrupt-parent = <&gic>;
+               reg = <0x10200a80 0x50>;
+       };
+
+       timer0: apxgpt@10008000 {
+               compatible = "mediatek,timer";
+               reg = <0x10008000 0x1000>;
+               interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_CLK26M_D2>,
+                        <&topckgen CLK_TOP_CLK32K>,
+                        <&topckgen CLK_TOP_APXGPT>;
+               clock-names = "clk13m",
+                        "clk32k",
+                        "bus";
+       };
+
+       watchdog0: watchdog@10007000 {
+               compatible = "mediatek,wdt";
+               reg = <0x10007000 0x1000>;
+               interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
+               #reset-cells = <1>;
+               status = "disabled";
+               timeout-sec = <60>;
+               reset-on-timeout;
+       };
+
+
+
+       mmc0: mmc@11120000 {
+               compatible = "mediatek,mt8516-mmc";
+               reg = <0x11120000 0x1000>;
+               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_MSDC0>,
+                       <&topckgen CLK_TOP_MSDC0>,
+                       <&topckgen CLK_TOP_MSDC0_B>;
+               clock-names = "source", "hclk", "source_cg";
+               status = "disabled";
+       };
+
+       uart0: serial@11005000 {
+               compatible = "mediatek,hsuart";
+               reg = <0x11005000 0x1000>;
+               interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_UART0_SEL>,
+                       <&topckgen CLK_TOP_UART0>;
+               clock-names = "baud", "bus";
+               status = "disabled";
+       };
+
+};

diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 25ef7651f0c891ada95a49225833ca2a61cde5c2..8e343c3182b8dbf452d89542086e364c291e7d51 100644 (file)
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -38,6 +38,15 @@ config TARGET_MT8516
          Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
          chip and several DDR3 and DDR4 options.
 
+config TARGET_MT8518
+       bool "MediaTek MT8518 SoC"
+       select ARM64
+       help
+         The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53.
+         including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+         Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+         chip and several DDR3 and DDR4 options.
+
 endchoice
 
 source "board/mediatek/mt7623/Kconfig"

diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index ea414dc407bd6fb21cb1438d56026bb945438a81..b9b2355e03d1095128b7abab6bd45e5170a4dbbd 100644 (file)
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_SPL_BUILD) += spl.o
 obj-$(CONFIG_TARGET_MT7623) += mt7623/
 obj-$(CONFIG_TARGET_MT7629) += mt7629/
 obj-$(CONFIG_TARGET_MT8516) += mt8516/
+obj-$(CONFIG_TARGET_MT8518) += mt8518/

diff --git a/arch/arm/mach-mediatek/mt8518/Makefile b/arch/arm/mach-mediatek/mt8518/Makefile
new file mode 100644 (file)
index 0000000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:     GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o

diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c
new file mode 100644 (file)
index 0000000..5a97c8c
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/init.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Configuration for MediaTek MT8518 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dt-bindings/clock/mt8518-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+       int ret;
+
+       ret = fdtdec_setup_memory_banksize();
+       if (ret)
+               return ret;
+
+       return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = gd->ram_base;
+       gd->bd->bi_dram[0].size = gd->ram_size;
+
+       return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+       psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+       printf("CPU:   MediaTek MT8518\n");
+       return 0;
+}
+
+static struct mm_region mt8518_mem_map[] = {
+       {
+               /* DDR */
+               .virt = 0x40000000UL,
+               .phys = 0x40000000UL,
+               .size = 0x20000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+       }, {
+               .virt = 0x00000000UL,
+               .phys = 0x00000000UL,
+               .size = 0x20000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               0,
+       }
+};
+
+struct mm_region *mem_map = mt8518_mem_map;

diff --git a/arch/arm/mach-mediatek/mt8518/lowlevel_init.S b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S
new file mode 100644 (file)
index 0000000..ad39212
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+       mov     x3, x2
+       mov     x2, x1
+       mov     x1, x4
+       mov     x4, #0
+       /* Define in src\bsp\trustzone\atf\v1.2\ */
+       /* mt8xxx\plat\mediatek\common\sip_svc.h */
+       /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/
+       ldr x0, =0xC2000200
+       SMC #0
+       ret