This patch provides u-boot support for Liebherr (LWN) mccmon6 board.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
select BOARD_LATE_INIT
select SUPPORT_SPL
+config TARGET_MCCMON6
+ bool "mccmon6"
+ select SUPPORT_SPL
+
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
select BOARD_LATE_INIT
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"
+source "board/liebherr/mccmon6/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
--- /dev/null
+if TARGET_MCCMON6
+
+config SYS_BOARD
+ default "mccmon6"
+
+config SYS_VENDOR
+ default "liebherr"
+
+config SYS_CONFIG_NAME
+ default "mccmon6"
+
+endif
--- /dev/null
+MCCMON6 BOARD
+M: Lukasz Majewski <lukma@denx.de>
+S: Maintained
+F: board/liebherr/mccmon6/
+F: include/configs/mccmon6.h
+F: configs/mccmon6_nor_defconfig
+F: configs/mccmon6_sd_defconfig
--- /dev/null
+#
+# (C) Copyright 2016-2017
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mccmon6.o spl.o
--- /dev/null
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/spi.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <micrel.h>
+#include <phy.h>
+#include <input.h>
+#include <i2c.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define ETH_PHY_RESET IMX_GPIO_NR(1, 27)
+#define ECSPI3_CS0 IMX_GPIO_NR(4, 24)
+#define ECSPI3_FLWP IMX_GPIO_NR(4, 27)
+#define NOR_WP IMX_GPIO_NR(1, 1)
+#define DISPLAY_EN IMX_GPIO_NR(1, 2)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* Carrier MicroSD Card Detect */
+ IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
+ | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
+ | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
+ | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ /* KSZ9031 PHY Reset */
+ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart1_pads);
+}
+
+static void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+
+ /* Reset KSZ9031 PHY */
+ gpio_direction_output(ETH_PHY_RESET, 0);
+ mdelay(10);
+ gpio_set_value(ETH_PHY_RESET, 1);
+ udelay(100);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ /*
+ * eMMC don't have card detect pin - since it is soldered to the
+ * PCB board
+ */
+ ret = 1;
+ break;
+ }
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ u32 index = 0;
+
+ /*
+ * MMC MAP
+ * (U-Boot device node) (Physical Port)
+ * mmc0 Soldered on board eMMC device
+ * mmc1 MicroSD card
+ */
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+ break;
+ case 1:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ gpio_direction_input(USDHC2_CD_GPIO);
+ break;
+ default:
+ printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+
+ /* NOR configuration */
+ writel(0x00620181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0b020000, &weim_regs->cs0rcr1);
+ writel(0x0000b000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000000, &weim_regs->cs0wcr2);
+
+ writel(0x00000120, &weim_regs->wcr);
+ writel(0x00000010, &weim_regs->wiar);
+ writel(0x00000000, &weim_regs->ear);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void setup_eimnor(void)
+{
+ SETUP_IOMUX_PADS(eimnor_pads);
+ gpio_direction_output(NOR_WP, 1);
+
+ enable_eim_clk(1);
+ eimnor_cs_setup();
+}
+
+/* mccmon6 board has SPI Flash is connected to SPI3 */
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
+}
+
+static iomux_v3_cfg_t const ecspi3_pads[] = {
+ /* SPI3 */
+ IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+};
+
+void setup_spi(void)
+{
+ SETUP_IOMUX_PADS(ecspi3_pads);
+
+ enable_spi_clk(true, 2);
+
+ /* set cs0 to high */
+ gpio_direction_output(ECSPI3_CS0, 1);
+
+ /* set flwp to high */
+ gpio_direction_output(ECSPI3_FLWP, 1);
+}
+
+struct i2c_pads_info mx6q_i2c1_pad_info = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+struct i2c_pads_info mx6q_i2c2_pad_info = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ gpio_direction_output(DISPLAY_EN, 1);
+
+ setup_eimnor();
+ setup_spi();
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("board_name", "mccmon6");
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MCCMON6\n");
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * Default setting for GMII Clock Pad Skew Register 0x1EF:
+ * MMD Address 0x2h, Register 0x8h
+ *
+ * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
+ * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
+ *
+ * Adjustment -> write 0x3FF:
+ * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
+ * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
+ *
+ */
+ ksz9031_phy_extended_write(phydev, 0x2,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
+
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
+
+ ksz9031_phy_extended_write(phydev, 0x2,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ 0x3333);
+
+ ksz9031_phy_extended_write(phydev, 0x2,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ 0x2052);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ setup_eimnor();
+
+ gpio_direction_output(DISPLAY_EN, 1);
+}
+#endif /* CONFIG_SPL_BOARD_INIT */
+
+#ifdef CONFIG_SPL_BUILD
+void board_boot_order(u32 *spl_boot_list)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC1:
+ spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+ break;
+
+ case BOOT_DEVICE_NOR:
+ spl_boot_list[0] = BOOT_DEVICE_NOR;
+ break;
+ }
+}
+#endif /* CONFIG_SPL_BUILD */
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ char s[16];
+ int ret;
+ /*
+ * We use BOOT_DEVICE_MMC1, but SD card is connected
+ * to MMC2
+ *
+ * Correct "mapping" is delivered in board defined
+ * board_boot_order() function.
+ *
+ * SD card boot is regarded as a "development" one,
+ * hence we _always_ go through the u-boot.
+ *
+ */
+ if (spl_boot_device() == BOOT_DEVICE_MMC1)
+ return 1;
+
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ env_init();
+ ret = getenv_f("boot_os", s, sizeof(s));
+ if ((ret != -1) && (strcmp(s, "no") == 0))
+ return 1;
+
+ /*
+ * Check if SWUpdate recovery needs to be started
+ *
+ * recovery_status = NULL (not set - ret == -1) -> normal operation
+ *
+ * recovery_status = progress or
+ * recovery_status = failed or
+ * recovery_status = <any value> -> start SWUpdate
+ *
+ */
+ ret = getenv_f("recovery_status", s, sizeof(s));
+ if (ret != -1)
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
--- /dev/null
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM nor
--- /dev/null
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
--- /dev/null
+/*
+ * Copyright (C) 2014 Wandboard
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ * Richard Hu <hakahu@gmail.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+/*
+ * Driving strength:
+ * 0x30 == 40 Ohm
+ * 0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH 0x30
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_cas = IMX6DQ_DRIVE_STRENGTH,
+ .dram_ras = IMX6DQ_DRIVE_STRENGTH,
+ .dram_reset = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* H5T04G63AFR-PB */
+static struct mx6_ddr3_cfg h5t04g63afr = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* H5TQ2G63DFR-H9 */
+static struct mx6_ddr3_cfg h5tq2g63dfr = {
+ .mem_speed = 1333,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001f001f,
+ .p0_mpwldectrl1 = 0x001f001f,
+ .p1_mpwldectrl0 = 0x001f001f,
+ .p1_mpwldectrl1 = 0x001f001f,
+ .p0_mpdgctrl0 = 0x4301030d,
+ .p0_mpdgctrl1 = 0x03020277,
+ .p1_mpdgctrl0 = 0x4300030a,
+ .p1_mpdgctrl1 = 0x02780248,
+ .p0_mprddlctl = 0x4536393b,
+ .p1_mprddlctl = 0x36353441,
+ .p0_mpwrdlctl = 0x41414743,
+ .p1_mpwrdlctl = 0x462f453f,
+};
+
+/* DDR 64bit 2GB */
+static struct mx6_ddr_sysinfo mem_q = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001f001f,
+ .p0_mpwldectrl1 = 0x001f001f,
+ .p1_mpwldectrl0 = 0x001f001f,
+ .p1_mpwldectrl1 = 0x001f001f,
+ .p0_mpdgctrl0 = 0x420e020e,
+ .p0_mpdgctrl1 = 0x02000200,
+ .p1_mpdgctrl0 = 0x42020202,
+ .p1_mpdgctrl1 = 0x01720172,
+ .p0_mprddlctl = 0x494c4f4c,
+ .p1_mprddlctl = 0x4a4c4c49,
+ .p0_mpwrdlctl = 0x3f3f3133,
+ .p1_mpwrdlctl = 0x39373f2e,
+};
+
+static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x0040003c,
+ .p0_mpwldectrl1 = 0x0032003e,
+ .p0_mpdgctrl0 = 0x42350231,
+ .p0_mpdgctrl1 = 0x021a0218,
+ .p0_mprddlctl = 0x4b4b4e49,
+ .p0_mpwrdlctl = 0x3f3f3035,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+ .dsize = 1,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+ mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
+ } else if (is_cpu_type(MXC_CPU_MX6DL)) {
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
+ } else if (is_cpu_type(MXC_CPU_MX6Q)) {
+ mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+ mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
+ }
+
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MCCMON6=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MCCMON6=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#include "imx6_spl.h"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000)
+#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000)
+#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K)
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
+
+/*
+ * Below defines are set but NOT really used since we by
+ * design force U-Boot run when we boot in development
+ * mode from SD card (SD2)
+ */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800)
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 2
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#undef CONFIG_SYS_NO_FLASH
+/* NOR 16-bit mode */
+#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_VERIFY
+
+/* NOR Flash MTD */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
+#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
+
+/* MTD support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT "nor0=8000000.nor"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=8000000.nor:" \
+ "32m@0x0(mccmon6-image.nor)," \
+ "256k@0x40000(u-boot-env.nor)," \
+ "1m@0x80000(u-boot.nor)," \
+ "8m@0x180000(kernel.nor)," \
+ "8m@0x980000(swupdate-kernel.nor)," \
+ "8m@0x1180000(swupdate-rootfs.nor)," \
+ "128k@0x1980000(kernel-dtb.nor)," \
+ "128k@0x19C0000(swupdate-kernel-dtb.nor)"
+
+/* USB Configs */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttymxc0,115200\0" \
+ "fdtfile=imx6q-mccmon6.dtb\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "boot_os=yes\0" \
+ "download_kernel=" \
+ "tftpboot ${kernel_addr} ${kernel_file};" \
+ "tftpboot ${fdt_addr} ${fdtfile};\0" \
+ "get_boot_medium=" \
+ "setenv boot_medium nor;" \
+ "setexpr.l _src_sbmr1 *0x020d8004;" \
+ "setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \
+ "if test ${_b_medium} = 40; then " \
+ "setenv boot_medium sdcard;" \
+ "fi\0" \
+ "kernel_file=uImage\0" \
+ "load_kernel=" \
+ "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \
+ "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \
+ "boot_sd=" \
+ "echo '#######################';" \
+ "echo '# Factory SDcard Boot #';" \
+ "echo '#######################';" \
+ "setenv mmcdev 1;" \
+ "setenv mmcfactorydev 0;" \
+ "setenv mmcfactorypart 1;" \
+ "run factory_flash_img;\0" \
+ "boot_nor=" \
+ "setenv kernelnor 0x08180000;" \
+ "setenv dtbnor 0x09980000;" \
+ "setenv bootargs console=${console} quiet " \
+ ""MTDPARTS_DEFAULT" " \
+ "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \
+ "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \
+ "bootm ${kernelnor} - ${dtbloadaddr};\0" \
+ "boot_recovery=" \
+ "echo '#######################';" \
+ "echo '# RECOVERY SWU Boot #';" \
+ "echo '#######################';" \
+ "setenv rootfsloadaddr 0x13000000;" \
+ "setenv swukernelnor 0x08980000;" \
+ "setenv swurootfsnor 0x09180000;" \
+ "setenv swudtbnor 0x099A0000;" \
+ "setenv bootargs console=${console} " \
+ ""MTDPARTS_DEFAULT" " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}::off root=/dev/ram rw;" \
+ "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \
+ "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \
+ "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \
+ "boot_tftp=" \
+ "echo '#######################';" \
+ "echo '# TFTP Boot #';" \
+ "echo '#######################';" \
+ "if run download_kernel; then " \
+ "setenv bootargs console=${console} " \
+ "root=/dev/mmcblk0p2 rootwait;" \
+ "bootm ${kernel_addr} - ${fdt_addr};" \
+ "fi\0" \
+ "bootcmd=" \
+ "if test -n ${recovery_status}; then " \
+ "run boot_recovery;" \
+ "else " \
+ "if test ! -n ${boot_medium}; then " \
+ "run get_boot_medium;" \
+ "if test ${boot_medium} = sdcard; then " \
+ "run boot_sd;" \
+ "else " \
+ "run boot_nor;" \
+ "fi;" \
+ "else " \
+ "if test ${boot_medium} = tftp; then " \
+ "run boot_tftp;" \
+ "fi;" \
+ "fi;" \
+ "fi\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "fdt_addr=0x18000000\0" \
+ "bootdev=1\0" \
+ "bootpart=1\0" \
+ "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "netdev=eth0\0" \
+ "load_addr=0x11000000\0" \
+ "dtbloadaddr=0x12000000\0" \
+ "uboot_file=u-boot.img\0" \
+ "SPL_file=SPL\0" \
+ "load_uboot=tftp ${load_addr} ${uboot_file}\0" \
+ "nor_img_addr=0x11000000\0" \
+ "nor_img_file=core-image-lwn-mccmon6.nor\0" \
+ "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \
+ "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
+ "nor_img_size=0x02000000\0" \
+ "factory_script_file=factory.scr\0" \
+ "factory_load_script=" \
+ "if test -e mmc ${mmcdev}:${mmcfactorypart} " \
+ "${factory_script_file}; then " \
+ "load mmc ${mmcdev}:${mmcfactorypart} " \
+ "${loadaddr} ${factory_script_file};" \
+ "fi\0" \
+ "factory_script=echo Running factory script from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "factory_flash_img="\
+ "echo 'Flash mccmon6 with factory images'; " \
+ "if run factory_load_script; then " \
+ "run factory_script;" \
+ "else " \
+ "echo No factory script: ${factory_script_file} found on " \
+ "device ${mmcdev};" \
+ "run factory_nor_img;" \
+ "run factory_eMMC_img;" \
+ "fi\0" \
+ "factory_eMMC_img="\
+ "echo 'Update mccmon6 eMMC image'; " \
+ "if load mmc ${mmcdev}:${mmcfactorypart} " \
+ "${loadaddr} ${emmc_img_file}; then " \
+ "setexpr fw_sz ${filesize} / 0x200;" \
+ "setexpr fw_sz ${fw_sz} + 1;" \
+ "mmc dev ${mmcfactorydev};" \
+ "mmc write ${loadaddr} 0x0 ${fw_sz};" \
+ "fi\0" \
+ "factory_nor_img="\
+ "echo 'Update mccmon6 NOR image'; " \
+ "if load mmc ${mmcdev}:${mmcfactorypart} " \
+ "${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
+ "nor_update=" \
+ "protect off ${nor_bank_start} +${nor_img_size};" \
+ "erase ${nor_bank_start} +${nor_img_size};" \
+ "setexpr nor_img_size ${nor_img_size} / 4; " \
+ "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \
+ "tftp_nor_uboot="\
+ "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \
+ "setenv nor_img_file u-boot.img; " \
+ "setenv nor_img_size 0x80000; " \
+ "setenv nor_bank_start 0x08080000; " \
+ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
+ "tftp_nor_uImg="\
+ "echo 'Update mccmon6 NOR uImage via TFTP'; " \
+ "setenv nor_img_file uImage; " \
+ "setenv nor_img_size 0x500000; " \
+ "setenv nor_bank_start 0x08180000; " \
+ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
+ "tftp_nor_img="\
+ "echo 'Update mccmon6 NOR image via TFTP'; " \
+ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+ "run nor_update;" \
+ "fi\0" \
+ "tftp_nor_SPL="\
+ "if tftp ${load_addr} SPL_padded; then " \
+ "erase 0x08000000 +0x20000;" \
+ "cp.b ${load_addr} 0x08000000 0x20000;" \
+ "fi;\0" \
+ "tftp_sd_SPL="\
+ "if mmc dev 1; then " \
+ "if tftp ${load_addr} ${SPL_file}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${load_addr} 0x2 ${fw_sz};" \
+ "fi;" \
+ "fi;\0" \
+ "tftp_sd_uboot="\
+ "if mmc dev 1; then " \
+ "if run load_uboot; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${load_addr} 0x8A ${fw_sz};" \
+ "fi;" \
+ "fi;\0"
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE (SZ_128K)
+
+/* Envs are stored in NOR flash */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (SZ_128K)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#endif /* __CONFIG_H * */
projects / oweals / u-boot.git / commitdiff