Merge tag 'arc-last-minute-for-2019.04' of git://git.denx.de/u-boot-arc

This is last minute change which fixes problems in runtime on
AXS10x board caused by some changes in NAND framework and
tiny documentation improvement.

Anyways NAND flash storage was never really used on the board for various
reasons and now we decided to drop it for good.

Note this change only touches 1 ARC board so that should be safe for others.
As usual - build tested in TravisCI, see
https://travis-ci.org/abrodkin/u-boot/builds/512041342

diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
index ebbd234d78ee8a4afd7748394ab91cc06c5c00d6..3de640724dfd768de94786297017a4ecf1876850 100644 (file)
--- a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
@@ -19,6 +19,10 @@
        };
 };
 
+&vcc_sdhi0 {
+       u-boot,off-on-delay-us = <20000>;
+};
+
 &sdhi2_pins {
        groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
        power-source = <1800>;

diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
index 8be5e41a511bfda58340f23fce6f3307c766833c..a22028bb3184b662257411bd33d6df8cfed7ddc1 100644 (file)
--- a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
@@ -8,6 +8,14 @@
 #include "r8a7795-salvator-x.dts"
 #include "r8a7795-u-boot.dtsi"
 
+&vcc_sdhi0 {
+       u-boot,off-on-delay-us = <20000>;
+};
+
+&vcc_sdhi3 {
+       u-boot,off-on-delay-us = <20000>;
+};
+
 &sdhi2_pins {
        groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
        power-source = <1800>;

diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
index 4e960081f9ca880206d8149932e24e2445866243..612cc87c71045137dc16c1e11ea0a445f1d5d843 100644 (file)
--- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
@@ -19,6 +19,10 @@
        };
 };
 
+&vcc_sdhi0 {
+       u-boot,off-on-delay-us = <20000>;
+};
+
 &sdhi2_pins {
        groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
        power-source = <1800>;

diff --git a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
index 44b2f9fb3731fa1ce6765d5c9a6794dd9d46dd00..c730b90a42c5d8bd30c5da18dadcd0a91320be06 100644 (file)
--- a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
@@ -8,6 +8,14 @@
 #include "r8a7796-salvator-x.dts"
 #include "r8a7796-u-boot.dtsi"
 
+&vcc_sdhi0 {
+       u-boot,off-on-delay-us = <20000>;
+};
+
+&vcc_sdhi3 {
+       u-boot,off-on-delay-us = <20000>;
+};
+
 &sdhi2_pins {
        groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
        power-source = <1800>;

diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts
index 9e0cd26f4086e965512c3e8f86dd5fc78f2bc9d2..cfc0f74081592580e0e5a490d3a0c5d176da0ef3 100644 (file)
--- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts
@@ -8,6 +8,14 @@
 #include "r8a77965-salvator-x.dts"
 #include "r8a77965-u-boot.dtsi"
 
+&vcc_sdhi0 {
+       u-boot,off-on-delay-us = <20000>;
+};
+
+&vcc_sdhi3 {
+       u-boot,off-on-delay-us = <20000>;
+};
+
 &sdhi2_pins {
        groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
        power-source = <1800>;

diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts
index b030d5c649d28c98971011665874070a25025ba2..4c1669e022cc6599fe2600b7aa6d0ef93e8152c8 100644 (file)
--- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts
+++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts
@@ -36,6 +36,7 @@
 
                gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
                enable-active-high;
+               u-boot,off-on-delay-us = <20000>;
        };
 
        vccq_sdhi0: regulator-vccq-sdhi0 {
@@ -60,6 +61,7 @@
 
                gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
                enable-active-high;
+               u-boot,off-on-delay-us = <20000>;
        };
 
        vccq_sdhi1: regulator-vccq-sdhi1 {

diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index f0671dd8a127e4f6cd51a953afb15e41d0e585a8..995290ca5f37999783494a4d65019c2df8919ee1 100644 (file)
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -56,4 +56,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
-CONFIG_USE_TINY_PRINTF=y

diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index 6dfd02f2eb5790058a38b19f015fd973d6fad0ca..13111b341af50ee2206d39f11d52ca66c51de0e0 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -44,13 +44,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
        {  0,  0 },
 };
 
-static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div)
+static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
 {
-       while ((*table++).val) {
-               if ((*table).div == div)
-                       return div;
+       for (;;) {
+               if (!(*table).div)
+                       return 0xff;
+
+               if ((*table).val == val)
+                       return (*table).div;
+
+               table++;
        }
-       return 0xff;
 }
 
 static int gen2_clk_enable(struct clk *clk)
@@ -117,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
 
        case CLK_TYPE_FF:
                rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
-               debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
+               debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
                      __func__, __LINE__,
                      core->parent, core->mult, core->div, rate);
                return rate;
@@ -202,8 +206,50 @@ static ulong gen2_clk_get_rate(struct clk *clk)
        return -ENOENT;
 }
 
+static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
+{
+       struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
+       struct cpg_mssr_info *info = priv->info;
+       const struct cpg_core_clk *core;
+       struct clk parent, pparent;
+       u32 val;
+       int ret;
+
+       ret = renesas_clk_get_parent(clk, info, &parent);
+       if (ret) {
+               debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
+               return ret;
+       }
+
+       if (renesas_clk_is_mod(&parent))
+               return 0;
+
+       ret = renesas_clk_get_core(&parent, info, &core);
+       if (ret)
+               return ret;
+
+       if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1"))
+               return 0;
+
+       ret = renesas_clk_get_parent(&parent, info, &pparent);
+       if (ret) {
+               debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
+               return ret;
+       }
+
+       val = (gen2_clk_get_rate(&pparent) / rate) - 1;
+
+       debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset);
+
+       writel(val, priv->base + core->offset);
+
+       return 0;
+}
+
 static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
 {
+       /* Force correct MMC-IF divider configuration if applicable */
+       gen2_clk_setup_mmcif_div(clk, rate);
        return gen2_clk_get_rate(clk);
 }
 

diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index 306daf141559e49731d4e384eb1f3593ca99a679..c8875ce8f8150950566c6b18869b30738b5640cb 100644 (file)
--- a/drivers/mmc/sh_mmcif.c
+++ b/drivers/mmc/sh_mmcif.c
@@ -696,7 +696,7 @@ static int sh_mmcif_dm_probe(struct udevice *dev)
                return ret;
        }
 
-       host->clk = clk_get_rate(&sh_mmcif_clk);
+       host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
 
        plat->cfg.name = dev->name;
        plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;

diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 01d8c2b92544edfcbf64d592918d1c719a0bbed4..812205a21f6a0731e51be595d95ac77489cf5060 100644 (file)
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -783,7 +783,10 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
        plat->cfg.f_min = mclk /
                        (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
        plat->cfg.f_max = mclk;
-       plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
+       if (quirks & TMIO_SD_CAP_16BIT)
+               plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
+       else
+               plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
 
        upriv->mmc = &plat->mmc;