ppc4xx: Consolidate pci_target_init() function
authorStefan Roese <sr@denx.de>
Thu, 12 Nov 2009 11:00:49 +0000 (12:00 +0100)
committerStefan Roese <sr@denx.de>
Thu, 19 Nov 2009 10:35:08 +0000 (11:35 +0100)
This patch removes the duplicted implementations of the pci_target_init()
function by introducing a weak default function for it. This weak default
has a different implementation for 440EP(x)/GR(x) PPC's. It can be
overridden by a board specific version (e.g. PMC440, korat).

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
27 files changed:
board/amcc/bamboo/bamboo.c
board/amcc/canyonlands/canyonlands.c
board/amcc/ebony/ebony.c
board/amcc/katmai/katmai.c
board/amcc/luan/luan.c
board/amcc/ocotea/ocotea.c
board/amcc/sequoia/sequoia.c
board/amcc/taishan/taishan.c
board/amcc/yosemite/yosemite.c
board/amcc/yucca/yucca.c
board/esd/du440/du440.c
board/esd/du440/du440.h
board/gdsys/gdppc440etx/gdppc440etx.c
board/gdsys/intip/intip.c
board/korat/korat.c
board/lwmon5/lwmon5.c
board/netstal/hcu5/hcu5.c
board/pcs440ep/pcs440ep.c
board/prodrive/alpr/alpr.c
board/prodrive/p3p440/p3p440.c
board/sandburst/common/sb_common.c
board/xes/xpedite1000/xpedite1000.c
cpu/ppc4xx/4xx_pci.c
include/asm-ppc/4xx_pci.h
include/configs/DU440.h
include/configs/PMC440.h
include/configs/korat.h

index 313f9f36a65cbfc5c61acd45f6b75287fdb73f88..3ffdac8bd5e679ac8228b0f10e7d874d62bed29e 100644 (file)
@@ -521,67 +521,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*--------------------------------------------------------------------------+
-        * Set up Direct MMIO registers
-        *--------------------------------------------------------------------------*/
-       /*--------------------------------------------------------------------------+
-         | PowerPC440 EP PCI Master configuration.
-         | Map one 1Gig range of PLB/processor addresses to PCI memory space.
-         |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
-         |   Use byte reversed out routines to handle endianess.
-         | Make this region non-prefetchable.
-         +--------------------------------------------------------------------------*/
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
-
-       /*--------------------------------------------------------------------------+
-        * Set up Configuration registers
-        *--------------------------------------------------------------------------*/
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 /*************************************************************************
  *  pci_master_init
  *
index 9a8ca8eceab3b6d149bf9255b8a112528a9ae864..13a0daced774ae24ebeb579df73f0fb4633998f7 100644 (file)
@@ -326,43 +326,6 @@ phys_size_t initdram(int board_type)
 }
 #endif
 
-/*
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*
-        * Disable everything
-        */
-       out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
-       out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
-       out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
-       out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
-
-       /*
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
-        * strapping options to not support sizes such as 128/256 MB.
-        */
-       out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out_le32((void *)PCIL0_PIM0LAH, 0);
-       out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-       out_le32((void *)PCIL0_BAR0, 0);
-
-       /*
-        * Program the board's subsystem id/vendor id
-        */
-       out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
-       out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #if defined(CONFIG_PCI)
 int board_pcie_first(void)
 {
index 1524b5333a4d6dd8863f024abf80e20a4d32db6c..e4d168f9d847cd7efc936e0752215fa4c86e1e8e 100644 (file)
@@ -195,42 +195,3 @@ int pci_pre_init(struct pci_controller *hose)
        return 1;
 }
 #endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*--------------------------------------------------------------------------+
-        * Disable everything
-        *--------------------------------------------------------------------------*/
-       out32r(PCIL0_PIM0SA, 0);        /* disable */
-       out32r(PCIL0_PIM1SA, 0);        /* disable */
-       out32r(PCIL0_PIM2SA, 0);        /* disable */
-       out32r(PCIL0_EROMBA, 0);        /* disable expansion rom */
-
-       /*--------------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-     * options to not support sizes such as 128/256 MB.
-        *--------------------------------------------------------------------------*/
-       out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out32r(PCIL0_PIM0LAH, 0);
-       out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
-       out32r(PCIL0_BAR0, 0);
-
-       /*--------------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *--------------------------------------------------------------------------*/
-       out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
-       out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
index f43e76448bb9632258cadf0fbdab59ea2dcfde3b..f0b48c0d320975f9e9a1e0273d7948e01e8af793 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2009
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -291,44 +291,6 @@ int pci_pre_init(struct pci_controller * hose )
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*-------------------------------------------------------------------+
-        * Disable everything
-        *-------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0SA, 0 ); /* disable */
-       out32r( PCIL0_PIM1SA, 0 ); /* disable */
-       out32r( PCIL0_PIM2SA, 0 ); /* disable */
-       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*-------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
-        * strapping options to not support sizes such as 128/256 MB.
-        *-------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIL0_PIM0LAH, 0 );
-       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-       out32r( PCIL0_BAR0, 0 );
-
-       /*-------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *-------------------------------------------------------------------*/
-       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #if defined(CONFIG_PCI)
 int board_pcie_card_present(int port)
 {
index 94ba6437f6dbd4ca56ca7fc657fb2420e614a596..e0b297e7072af2a13ff6cf8d74a08dfa679f36a6 100644 (file)
@@ -159,46 +159,6 @@ int pci_pre_init( struct pci_controller *hose )
 #endif /* defined(CONFIG_PCI) */
 
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*--------------------------------------------------------------------------+
-        * Disable everything
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0SA, 0 ); /* disable */
-       out32r( PCIL0_PIM1SA, 0 ); /* disable */
-       out32r( PCIL0_PIM2SA, 0 ); /* disable */
-       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*--------------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-        * options to not support sizes such as 128/256 MB.
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIL0_PIM0LAH, 0 );
-       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
-       out32r( PCIL0_BAR0, 0 );
-
-       /*--------------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *--------------------------------------------------------------------------*/
-       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
 /*************************************************************************
  *  hw_watchdog_reset
  *
index 2f64764ee2942911a11aafbf60531bae7256d5a2..b38f3cc400fdba9df8a20e22730eff3dca89dc78 100644 (file)
@@ -307,46 +307,6 @@ int pci_pre_init(struct pci_controller * hose )
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*--------------------------------------------------------------------------+
-        * Disable everything
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0SA, 0 ); /* disable */
-       out32r( PCIL0_PIM1SA, 0 ); /* disable */
-       out32r( PCIL0_PIM2SA, 0 ); /* disable */
-       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*--------------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-        * options to not support sizes such as 128/256 MB.
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIL0_PIM0LAH, 0 );
-       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
-       out32r( PCIL0_BAR0, 0 );
-
-       /*--------------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *--------------------------------------------------------------------------*/
-       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
 void fpga_init(void)
 {
        unsigned long group;
index 43938200616375db74c36e175bd5348963af398d..b8ef4e7633755cec9e11c6449ea6c522c3aff19f 100644 (file)
@@ -427,71 +427,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*
-        * Set up Direct MMIO registers
-        */
-       /*
-        * PowerPC440EPX PCI Master configuration.
-        * Map one 1Gig range of PLB/processor addresses to PCI memory space.
-        * PLB address 0xA0000000-0xDFFFFFFF
-        *     ==> PCI address 0xA0000000-0xDFFFFFFF
-        * Use byte reversed out routines to handle endianess.
-        * Make this region non-prefetchable.
-        */
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
-                                               /* - disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
-                                               /* and enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
-                                               /* - disabled b4 setting */
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
-                                               /* and enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
-
-       /*
-        * Set up Configuration registers
-        */
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
index 81e8fe14ab84346434aa06f089bab2bedc2ea3dd..574ff1a7bc20cc02d2e42ecc4b856ef17789a482 100644 (file)
@@ -240,45 +240,6 @@ int pci_pre_init(struct pci_controller * hose )
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*--------------------------------------------------------------------------+
-        * Disable everything
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0SA, 0 ); /* disable */
-       out32r( PCIL0_PIM1SA, 0 ); /* disable */
-       out32r( PCIL0_PIM2SA, 0 ); /* disable */
-       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*--------------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-        * options to not support sizes such as 128/256 MB.
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIL0_PIM0LAH, 0 );
-       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
-       out32r( PCIL0_BAR0, 0 );
-
-       /*--------------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *--------------------------------------------------------------------------*/
-       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #ifdef CONFIG_POST
 /*
  * Returns 1 if keys pressed to start the power-on long-running tests
index e416eeb1676c47a0e5f0aad919120bd7e50b82ec..cd14a6a487ddd7e6fc306beb19fb8179a6307806 100644 (file)
@@ -407,67 +407,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*--------------------------------------------------------------------------+
-        * Set up Direct MMIO registers
-        *--------------------------------------------------------------------------*/
-       /*--------------------------------------------------------------------------+
-         | PowerPC440 EP PCI Master configuration.
-         | Map one 1Gig range of PLB/processor addresses to PCI memory space.
-         |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
-         |   Use byte reversed out routines to handle endianess.
-         | Make this region non-prefetchable.
-         +--------------------------------------------------------------------------*/
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
-
-       /*--------------------------------------------------------------------------+
-        * Set up Configuration registers
-        *--------------------------------------------------------------------------*/
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 /*************************************************************************
  *  pci_master_init
  *
index 7315033dc89abd2f69a9a97c96b63f7866d7b8a0..0ec26f14d19e01186af45e0e5dfffd488ec880a0 100644 (file)
@@ -619,44 +619,6 @@ int pci_pre_init(struct pci_controller * hose )
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*-------------------------------------------------------------------+
-        * Disable everything
-        *-------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0SA, 0 ); /* disable */
-       out32r( PCIL0_PIM1SA, 0 ); /* disable */
-       out32r( PCIL0_PIM2SA, 0 ); /* disable */
-       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*-------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
-        * strapping options to not support sizes such as 128/256 MB.
-        *-------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIL0_PIM0LAH, 0 );
-       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-       out32r( PCIL0_BAR0, 0 );
-
-       /*-------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *-------------------------------------------------------------------*/
-       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #if defined(CONFIG_PCI)
 int board_pcie_card_present(int port)
 {
index 8f9f9500e298af849429f56939f9ccbb035807c4..866dcafcfa37aa7cbcac24c3e349c056b5f23a63 100644 (file)
@@ -414,73 +414,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*
-        * Set up Direct MMIO registers
-        */
-       /*
-        * PowerPC440EPX PCI Master configuration.
-        * Map one 1Gig range of PLB/processor addresses to PCI memory space.
-        * PLB address 0xA0000000-0xDFFFFFFF
-        *     ==> PCI address 0xA0000000-0xDFFFFFFF
-        * Use byte reversed out routines to handle endianess.
-        * Make this region non-prefetchable.
-        */
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
-                                               /* - disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
-                                               /* and enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
-                                               /* - disabled b4 setting */
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
-                                               /* and enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
-
-       /*
-        * Set up Configuration registers
-        */
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             PCI_VENDOR_ID_ESDGMBH);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
-
-       pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
index a124a7ee9b51df8f16f245a55247673efbb87b4d..37697ec854f985a4cd44d95abe0b387322fa1d59 100644 (file)
@@ -38,6 +38,3 @@
 #define PWR_RDY                        0x10
 
 #define CPLD_IRQ               (32+30)
-
-#define PCI_VENDOR_ID_ESDGMBH  0x12fe
-#define PCI_DEVICE_ID_DU440    0x0444
index 92f5d822f69ce8d87d1538b093b252a6f32611b4..b93a420154f6d379d587dc337363f8b7c6e250ba 100644 (file)
@@ -216,69 +216,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*
-        * Set up Direct MMIO registers
-        */
-
-       /*
-        * PowerPC440 EP PCI Master configuration.
-        * Map one 1Gig range of PLB/processor addresses to PCI memory space.
-        *       PLB address 0xA0000000-0xDFFFFFFF
-        *   ==> PCI address 0xA0000000-0xDFFFFFFF
-        *   Use byte reversed out routines to handle endianess.
-        * Make this region non-prefetchable.
-        */
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);
-       out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* disabled b4 setting */
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);
-       out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);
-       out32r(PCIL0_PTM1LA, 0);
-       out32r(PCIL0_PTM2MS, 0);
-       out32r(PCIL0_PTM2LA, 0);
-
-       /*
-        * Set up Configuration registers
-        */
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 /*
  *  pci_master_init
  *
index 49d245135821c2bd05b7da38bedeeb0259fd85cc..23a10c41f9f415c0c082d8fda0686edc23684163 100644 (file)
@@ -141,43 +141,6 @@ int checkboard(void)
        return 0;
 }
 
-/*
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*
-        * Disable everything
-        */
-       out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
-       out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
-       out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
-       out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
-
-       /*
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
-        * strapping options to not support sizes such as 128/256 MB.
-        */
-       out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out_le32((void *)PCIL0_PIM0LAH, 0);
-       out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-       out_le32((void *)PCIL0_BAR0, 0);
-
-       /*
-        * Program the board's subsystem id/vendor id
-        */
-       out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
-       out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 int board_early_init_r(void)
 {
        /*
index b0e6a56a63c0bf5cf8f755184e3b98df97ff40e1..02ebfdf37107f5e1000f35479aaf6cfc7edbaf25 100644 (file)
@@ -35,6 +35,7 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-uic.h>
 #include <asm/processor.h>
+#include <asm/4xx_pci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -668,60 +669,8 @@ int pci_pre_init(struct pci_controller *hose)
 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-       /*
-        * Set up Direct MMIO registers
-        */
-       /*
-        * PowerPC440EPX PCI Master configuration.
-        * Map one 1Gig range of PLB/processor addresses to PCI memory space.
-        * PLB address 0x80000000-0xBFFFFFFF
-        *     ==> PCI address 0x80000000-0xBFFFFFFF
-        * Use byte reversed out routines to handle endianess.
-        * Make this region non-prefetchable.
-        */
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
-                                               /* - disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIL0_PMM0PCILA,
-              CONFIG_SYS_PCI_MEMBASE);         /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
-                                               /* and enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
-                                               /* - disabled b4 setting */
-       out32r(PCIL0_PMM1LA,
-              CONFIG_SYS_PCI_MEMBASE + 0x20000000);    /* PMM0 Local Address */
-       out32r(PCIL0_PMM1PCILA,
-              CONFIG_SYS_PCI_MEMBASE + 0x20000000);    /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
-                                               /* and enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
-
-       /*
-        * Set up Configuration registers
-        */
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+       /* First do 440EP(x) common setup */
+       __pci_target_init(hose);
 
        /*
         * Set up Configuration registers for on-board NEC uPD720101 USB
index 09ba2b933d64571d492f757a291ab19132655ea2..77f2d7f688fb6f8059058086da914c5a7afe3bc8 100644 (file)
@@ -330,67 +330,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*--------------------------------------------------------------------------+
-        * Set up Direct MMIO registers
-        *--------------------------------------------------------------------------*/
-       /*--------------------------------------------------------------------------+
-         | PowerPC440EPX PCI Master configuration.
-         | Map one 1Gig range of PLB/processor addresses to PCI memory space.
-         |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
-         |   Use byte reversed out routines to handle endianess.
-         | Make this region non-prefetchable.
-         +--------------------------------------------------------------------------*/
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
-
-       /*--------------------------------------------------------------------------+
-        * Set up Configuration registers
-        *--------------------------------------------------------------------------*/
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 /*************************************************************************
  *  pci_master_init
  *
index 7ffc2620245758f70640bf26873d35f21f6fe011..144fdd97047f0120eb05cbb312349a014d6a18d3 100644 (file)
@@ -376,71 +376,6 @@ int pci_pre_init(struct pci_controller *hose)
        return board_with_pci();
 }
 
-/*
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- */
-void pci_target_init(struct pci_controller *hose)
-{
-       if (!board_with_pci()) { return; }
-       /*
-        * Set up Direct MMIO registers
-        *
-        * PowerPC440EPX PCI Master configuration.
-        * Map one 1Gig range of PLB/processor addresses to PCI memory space.
-        *   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
-        *                0xA0000000-0xDFFFFFFF
-        *   Use byte reversed out routines to handle endianess.
-        * Make this region non-prefetchable.
-        */
-       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM0MA, 0x00000000);
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       /* 512M + No prefetching, and enable region */
-       out32r(PCIL0_PMM0MA, 0xE0000001);
-
-       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM1MA, 0x00000000);
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
-       /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       /* 512M + No prefetching, and enable region */
-       out32r(PCIL0_PMM1MA, 0xE0000001);
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
-
-       /*
-        * Set up Configuration registers
-        */
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-}
-
 /*
  *  pci_master_init
  *
index 2155711d6f839c9f6bfb3f2a05f10d251b5cb378..929375987cc8808d07e59c05a9460cc9bb464128 100644 (file)
@@ -605,67 +605,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*--------------------------------------------------------------------------+
-        * Set up Direct MMIO registers
-        *--------------------------------------------------------------------------*/
-       /*--------------------------------------------------------------------------+
-         | PowerPC440 EP PCI Master configuration.
-         | Map one 1Gig range of PLB/processor addresses to PCI memory space.
-         |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
-         |   Use byte reversed out routines to handle endianess.
-         | Make this region non-prefetchable.
-         +--------------------------------------------------------------------------*/
-       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
-       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
-
-       /*--------------------------------------------------------------------------+
-        * Set up Configuration registers
-        *--------------------------------------------------------------------------*/
-
-       /* Program the board's subsystem id/vendor id */
-       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
-       /* Configure command register as bus master */
-       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-       /* 240nS PCI clock */
-       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-       /* No error reporting */
-       pci_write_config_word(0, PCI_ERREN, 0);
-
-       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 /*************************************************************************
  *  pci_master_init
  *
index e9e2bf3e0ba2e1311c16c424355d201a2173702a..c06aadb4141beb2181323cd2f0d2a217c06c04bd 100644 (file)
@@ -178,45 +178,6 @@ int pci_pre_init(struct pci_controller * hose )
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*--------------------------------------------------------------------------+
-        * Disable everything
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0SA, 0 ); /* disable */
-       out32r( PCIL0_PIM1SA, 0 ); /* disable */
-       out32r( PCIL0_PIM2SA, 0 ); /* disable */
-       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*--------------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-        * options to not support sizes such as 128/256 MB.
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIL0_PIM0LAH, 0 );
-       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
-       out32r( PCIL0_BAR0, 0 );
-
-       /*--------------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *--------------------------------------------------------------------------*/
-       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 /*************************************************************************
  * Override weak is_pci_host()
  *
index e07400794b063f2a9604e70fcc528cfe04269f69..5761e708454b961304503a2d9606d4635cb26383 100644 (file)
@@ -195,45 +195,6 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-       /*--------------------------------------------------------------------------+
-        * Disable everything
-        *--------------------------------------------------------------------------*/
-       out32r(PCIL0_PIM0SA, 0);        /* disable */
-       out32r(PCIL0_PIM1SA, 0);        /* disable */
-       out32r(PCIL0_PIM2SA, 0);        /* disable */
-       out32r(PCIL0_EROMBA, 0);        /* disable expansion rom */
-
-       /*--------------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-        * options to not support sizes such as 128/256 MB.
-        *--------------------------------------------------------------------------*/
-       out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out32r(PCIL0_PIM0LAH, 0);
-       out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
-       out32r(PCIL0_BAR0, 0);
-
-       /*--------------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *--------------------------------------------------------------------------*/
-       out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
-       out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 /*************************************************************************
  * Override weak is_pci_host()
  *
index 5749084583c4a56556682cca0a1b07a1835376f0..45e9043851ec510b7dc8cbfc018eb4bf8e09b602 100644 (file)
@@ -332,46 +332,6 @@ int pci_pre_init(struct pci_controller * hose )
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*--------------------------------------------------------------------------+
-        * Disable everything
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0SA, 0 ); /* disable */
-       out32r( PCIL0_PIM1SA, 0 ); /* disable */
-       out32r( PCIL0_PIM2SA, 0 ); /* disable */
-       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*--------------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-        * options to not support sizes such as 128/256 MB.
-        *--------------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIL0_PIM0LAH, 0 );
-       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
-       out32r( PCIL0_BAR0, 0 );
-
-       /*--------------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *--------------------------------------------------------------------------*/
-       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
 /*************************************************************************
  *  board_get_enetaddr
  *
index 0c4cf9463fafd5f08237021c49774ab7220f26ef..db37ca0516ab0b7342719921fcf4c9e1438ca4a9 100644 (file)
@@ -166,38 +166,6 @@ int pci_pre_init(struct pci_controller * hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-/*
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-void pci_target_init(struct pci_controller * hose)
-{
-       /* Disable everything */
-       out32r(PCIL0_PIM0SA, 0);
-       out32r(PCIL0_PIM1SA, 0);
-       out32r(PCIL0_PIM2SA, 0);
-       out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
-
-       /*
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
-        * options to not support sizes such as 128/256 MB.
-        */
-       out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out32r(PCIL0_PIM0LAH, 0);
-       out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
-       out32r(PCIL0_BAR0, 0);
-
-       /* Program the board's subsystem id/vendor id */
-       out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
-       out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #if defined(CONFIG_PCI)
 /*
  * Override weak is_pci_host()
index 40017f4d6b57b1495ef3d001d3b65e23b09cd75f..20e134b63e9ddb9cf3033eaa9675fd2cd398f16f 100644 (file)
@@ -77,6 +77,7 @@
 #include <asm/4xx_pci.h>
 #endif
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <pci.h>
 
 #ifdef CONFIG_PCI
@@ -499,6 +500,111 @@ int __is_pci_host(struct pci_controller *hose)
 int is_pci_host(struct pci_controller *hose)
        __attribute__((weak, alias("__is_pci_host")));
 
+/*
+ *  pci_target_init
+ *
+ *     The bootstrap configuration provides default settings for the pci
+ *     inbound map (PIM). But the bootstrap config choices are limited and
+ *     may not be sufficient for a given board.
+ */
+#if defined(CONFIG_SYS_PCI_TARGET_INIT)
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440GRX)
+void __pci_target_init(struct pci_controller *hose)
+{
+       /*
+        * Set up Direct MMIO registers
+        */
+
+       /*
+        * PowerPC440 EP PCI Master configuration.
+        * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+        * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+        * Use byte reversed out routines to handle endianess.
+        * Make this region non-prefetchable.
+        */
+       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out_le32((void *)PCIL0_PMM0MA, 0x00000000);
+       /* PMM0 Local Address */
+       out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
+       /* PMM0 PCI Low Address */
+       out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+       /* PMM0 PCI High Address */
+       out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
+       /* 512M + No prefetching, and enable region */
+       out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
+
+       /* PMM1 Mask/Attribute - disabled b4 setting */
+       out_le32((void *)PCIL0_PMM1MA, 0x00000000);
+       /* PMM1 Local Address */
+       out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
+       /* PMM1 PCI Low Address */
+       out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+       /* PMM1 PCI High Address */
+       out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
+       /* 512M + No prefetching, and enable region */
+       out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
+
+       out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+       out_le32((void *)PCIL0_PTM1LA, 0);      /* Local Addr. Reg */
+       out_le32((void *)PCIL0_PTM2MS, 0);      /* Memory Size/Attribute */
+       out_le32((void *)PCIL0_PTM2LA, 0);      /* Local Addr. Reg */
+
+       /*
+        * Set up Configuration registers
+        */
+
+       /* Program the board's subsystem id/vendor id */
+       pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
+
+       /* Configure command register as bus master */
+       pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+       /* 240nS PCI clock */
+       pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+       /* No error reporting */
+       pci_write_config_word(0, PCI_ERREN, 0);
+
+       pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+}
+#else /* defined(CONFIG_440EP) ... */
+void __pci_target_init(struct pci_controller * hose)
+{
+       /*
+        * Disable everything
+        */
+       out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+       out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
+
+       /*
+        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+        * strapping options do not support sizes such as 128/256 MB.
+        */
+       out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out_le32((void *)PCIL0_PIM0LAH, 0);
+       out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out_le32((void *)PCIL0_BAR0, 0);
+
+       /*
+        * Program the board's subsystem id/vendor id
+        */
+       out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+
+       out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
+                PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_440EP) ... */
+void pci_target_init(struct pci_controller * hose)
+       __attribute__((weak, alias("__pci_target_init")));
+
+#endif /* defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
 int pci_440_init (struct pci_controller *hose)
 {
        int reg_num = 0;
index 30125a19ef65629946c8967dac6f2d7ceb8de894..5400a035ea0da274e36d8a996790d3202f1f9555 100644 (file)
@@ -49,4 +49,6 @@
 
 #define PCIDEVID_405GP 0x0
 
+void __pci_target_init(struct pci_controller *hose);
+
 #endif
index e9ea1bf7d0878072dc3cad39ccd04ac936f02929..65dc2359d01b0a01405c647630a8a3ab58473a6b 100644 (file)
@@ -60,8 +60,9 @@
 #define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
 #define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
 #define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-#define CONFIG_SYS_PCI_IOBASE          0xe8000000
-
+#define CONFIG_SYS_PCI_IOBASE          0xe8000000
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
+#define CONFIG_SYS_PCI_SUBSYS_ID       0x0444          /* device ID for DU440 */
 
 /* Don't change either of these */
 #define CONFIG_SYS_PERIPHERAL_BASE     0xef600000      /* internal peripherals */
index d6e2f6bc5e2be03e4610e676ca11264a9744f3e3..d2c5188a67203ffb73e7bf221d5375ef6938f815 100644 (file)
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441     /* PCI Device ID: Non-Monarch */
 #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440        /* PCI Device ID: Monarch */
+/* for weak __pci_target_init() */
+#define CONFIG_SYS_PCI_SUBSYS_ID       CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH    PCI_CLASS_PROCESSOR_POWERPC
 #define CONFIG_SYS_PCI_CLASSCODE_MONARCH       PCI_CLASS_BRIDGE_HOST
 
index ea6ba8938d7b6463e1408b206dd900a3c4c8e0b1..7e74ef7051419782da8231a35484a10259f6e7be 100644 (file)
@@ -69,6 +69,7 @@
 #define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_OCM_BASE
 #define CONFIG_SYS_PCI_BASE            0xe0000000      /* Internal PCI regs    */
 #define CONFIG_SYS_PCI_MEMBASE         0x80000000      /* mapped pci memory    */
+#define CONFIG_SYS_PCI_MEMBASE2                (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
 
 /* Don't change either of these */
 #define CONFIG_SYS_PERIPHERAL_BASE     0xef600000      /* internal peripherals */