These headers are only included locally in arch/arm/mach-uniphier/.
There is no reason to export them by putting in the mach/ directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_ARM_MPCORE_H
+#define ARCH_ARM_MPCORE_H
+
+/* Snoop Control Unit */
+#define SCU_OFFSET 0x00
+
+/* SCU Control Register */
+#define SCU_CTRL 0x00
+/* SCU Configuration Register */
+#define SCU_CONF 0x04
+/* SCU CPU Power Status Register */
+#define SCU_PWR_STATUS 0x08
+/* SCU Invalidate All Registers in Secure State */
+#define SCU_INV_ALL 0x0C
+/* SCU Filtering Start Address Register */
+#define SCU_FILTER_START 0x40
+/* SCU Filtering End Address Register */
+#define SCU_FILTER_END 0x44
+/* SCU Access Control Register */
+#define SCU_SAC 0x50
+/* SCU Non-secure Access Control Register */
+#define SCU_SNSAC 0x54
+
+/* Global Timer */
+#define GLOBAL_TIMER_OFFSET 0x200
+
+/* Global Timer Counter Registers */
+#define GTIMER_CNT_L 0x00
+#define GTIMER_CNT_H 0x04
+/* Global Timer Control Register */
+#define GTIMER_CTRL 0x08
+/* Global Timer Interrupt Status Register */
+#define GTIMER_STAT 0x0C
+/* Comparator Value Registers */
+#define GTIMER_CMP_L 0x10
+#define GTIMER_CMP_H 0x14
+/* Auto-increment Register */
+#define GTIMER_INC 0x18
+
+#endif /* ARCH_ARM_MPCORE_H */
*/
#include <linux/io.h>
-#include <mach/bcu-regs.h>
-#include <mach/init.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
*/
#include <linux/io.h>
-#include <mach/bcu-regs.h>
-#include <mach/init.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
--- /dev/null
+/*
+ * UniPhier BCU (Bus Control Unit) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_BCU_REGS_H
+#define ARCH_BCU_REGS_H
+
+#define BCU_BASE 0x50080000
+
+#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4)
+#define BCSCR0 (BCSCR(0))
+#define BCSCR1 (BCSCR(1))
+#define BCSCR2 (BCSCR(2))
+#define BCSCR3 (BCSCR(3))
+#define BCSCR4 (BCSCR(4))
+#define BCSCR5 (BCSCR(5))
+
+#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4)
+#define BCIPPCCHR0 (BCIPPCCHR(0))
+#define BCIPPCCHR1 (BCIPPCCHR(1))
+#define BCIPPCCHR2 (BCIPPCCHR(2))
+#define BCIPPCCHR3 (BCIPPCCHR(3))
+#define BCIPPCCHR4 (BCIPPCCHR(4))
+#define BCIPPCCHR5 (BCIPPCCHR(5))
+
+#endif /* ARCH_BCU_REGS_H */
*/
#include <common.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
int board_init(void)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
-#include <mach/soc_info.h>
+#include "init.h"
+#include "micro-support-card.h"
+#include "soc-info.h"
int board_early_init_f(void)
{
*/
#include <common.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
int board_early_init_r(void)
{
#include <common.h>
#include <libfdt.h>
#include <linux/kernel.h>
-#include <mach/init.h>
+
+#include "init.h"
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_BOOT_DEVICE_H_
+#define _ASM_BOOT_DEVICE_H_
+
+struct boot_device_info {
+ u32 type;
+ char *info;
+};
+
+u32 ph1_sld3_boot_device(void);
+u32 ph1_ld4_boot_device(void);
+u32 ph1_pro5_boot_device(void);
+u32 proxstream2_boot_device(void);
+
+void ph1_sld3_boot_mode_show(void);
+void ph1_ld4_boot_mode_show(void);
+void ph1_pro5_boot_mode_show(void);
+void proxstream2_boot_mode_show(void);
+
+#endif /* _ASM_BOOT_DEVICE_H_ */
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
#include <common.h>
#include <spl.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/soc_info.h>
+
+#include "../sbc/sbc-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
u32 spl_boot_device(void)
{
*/
#include <common.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/soc_info.h>
+
+#include "../sbc/sbc-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#include <common.h>
#include <linux/io.h>
#include <asm/armv7.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_maint_all(u32 operation)
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_ld4_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_pro4_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_pro5_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void proxstream2_clk_init(void)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/sg-regs.h>
+
+#include "sg-regs.h"
int print_cpuinfo(void)
{
#include <linux/serial_reg.h>
#include <linux/linkage.h>
-#include <mach/bcu-regs.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "bcu/bcu-regs.h"
+#include "sc-regs.h"
+#include "sg-regs.h"
#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
#include <common.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
/* Select either decimal or hexadecimal */
#if 1
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
#include <config.h>
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
--- /dev/null
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+
+#ifndef __ASSEMBLY__
+
+struct ddrphy {
+ u32 ridr; /* Revision Identification Register */
+ u32 pir; /* PHY Initialixation Register */
+ u32 pgcr[2]; /* PHY General Configuration Register */
+ u32 pgsr[2]; /* PHY General Status Register */
+ u32 pllcr; /* PLL Control Register */
+ u32 ptr[5]; /* PHY Timing Register */
+ u32 acmdlr; /* AC Master Delay Line Register */
+ u32 acbdlr; /* AC Bit Delay Line Register */
+ u32 aciocr; /* AC I/O Configuration Register */
+ u32 dxccr; /* DATX8 Common Configuration Register */
+ u32 dsgcr; /* DDR System General Configuration Register */
+ u32 dcr; /* DRAM Configuration Register */
+ u32 dtpr[3]; /* DRAM Timing Parameters Register */
+ u32 mr0; /* Mode Register 0 */
+ u32 mr1; /* Mode Register 1 */
+ u32 mr2; /* Mode Register 2 */
+ u32 mr3; /* Mode Register 3 */
+ u32 odtcr; /* ODT Configuration Register */
+ u32 dtcr; /* Data Training Configuration Register */
+ u32 dtar[4]; /* Data Training Address Register */
+ u32 dtdr[2]; /* Data Training Data Register */
+ u32 dtedr[2]; /* Data Training Eye Data Register */
+ u32 pgcr2; /* PHY General Configuration Register 2 */
+ u32 rsv0[8]; /* Reserved */
+ u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
+ u32 rdimmcr0[2]; /* RDIMM Control Register */
+ u32 dcuar; /* DCU Address Register */
+ u32 dcudr; /* DCU Data Register */
+ u32 dcurr; /* DCU Run Register */
+ u32 dculr; /* DCU Loop Register */
+ u32 dcugcr; /* DCU General Configuration Register */
+ u32 dcutpr; /* DCU Timing Parameters Register */
+ u32 dcusr[2]; /* DCU Status Register */
+ u32 rsv1[8]; /* Reserved */
+ u32 bistrr; /* BIST Run Register */
+ u32 bistwcr; /* BIST Word Count Register */
+ u32 bistmskr[3]; /* BIST Mask Register */
+ u32 bistlsr; /* BIST LFSR Sed Register */
+ u32 bistar[3]; /* BIST Address Register */
+ u32 bistudpr; /* BIST User Data Pattern Register */
+ u32 bistgsr; /* BIST General Status Register */
+ u32 bistwer; /* BIST Word Error Register */
+ u32 bistber[4]; /* BIST Bit Error Register */
+ u32 bistwcsr; /* BIST Word Count Status Register */
+ u32 bistfwr[3]; /* BIST Fail Word Register */
+ u32 rsv2[10]; /* Reserved */
+ u32 gpr[2]; /* General Purpose Register */
+ struct ddrphy_zq { /* ZQ */
+ u32 cr[2]; /* Impedance Control Register */
+ u32 sr[2]; /* Impedance Status Register */
+ } zq[4];
+ struct ddrphy_datx8 { /* DATX8 */
+ u32 gcr; /* General Configuration Register */
+ u32 gsr[2]; /* General Status Register */
+ u32 bdlr[5]; /* Bit Delay Line Register */
+ u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
+ u32 mdlr; /* Master Delay Line Register */
+ u32 gtr; /* General Timing Register */
+ u32 gsr2; /* General Status Register 2 */
+ u32 rsv[2]; /* Reserved */
+ } dx[9];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define PIR_INIT BIT(0) /* Initialization Trigger */
+#define PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define PIR_DCAL BIT(5) /* DDL Calibration */
+#define PIR_PHYRST BIT(6) /* PHY Reset */
+#define PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define PIR_WL BIT(9) /* Write Leveling */
+#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
+#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
+#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define PIR_INITBYP BIT(31) /* Initialization Bypass */
+
+#define PGSR0_IDONE BIT(0) /* Initialization Done */
+#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define PGSR0_IERR BIT(16) /* Initialization Error */
+#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
+#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
+#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
+#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
+#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
+#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
+#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
+
+#define DXCCR_DQSRES_OPEN (0 << 5)
+#define DXCCR_DQSRES_688_OHM (1 << 5)
+#define DXCCR_DQSRES_611_OHM (2 << 5)
+#define DXCCR_DQSRES_550_OHM (3 << 5)
+#define DXCCR_DQSRES_500_OHM (4 << 5)
+#define DXCCR_DQSRES_458_OHM (5 << 5)
+#define DXCCR_DQSRES_393_OHM (6 << 5)
+#define DXCCR_DQSRES_344_OHM (7 << 5)
+
+#define DXCCR_DQSNRES_OPEN (0 << 9)
+#define DXCCR_DQSNRES_688_OHM (1 << 9)
+#define DXCCR_DQSNRES_611_OHM (2 << 9)
+#define DXCCR_DQSNRES_550_OHM (3 << 9)
+#define DXCCR_DQSNRES_500_OHM (4 << 9)
+#define DXCCR_DQSNRES_458_OHM (5 << 9)
+#define DXCCR_DQSNRES_393_OHM (6 << 9)
+#define DXCCR_DQSNRES_344_OHM (7 << 9)
+
+#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
+#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
+#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
+#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
+
+#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
+
+/* SoC-specific parameters */
+#define NR_DATX8_PER_DDRPHY 2
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+#define NR_DDRPHY_PER_CH 1
+#else
+#define NR_DDRPHY_PER_CH 2
+#endif
+
+#define NR_DDRCH 2
+
+#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
+
+#ifndef __ASSEMBLY__
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
+int ddrphy_training(struct ddrphy __iomem *phy);
+#endif
+
+#endif /* ARCH_DDRPHY_REGS_H */
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
--- /dev/null
+/*
+ * UniPhier UMC (Universal Memory Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_UMC_REGS_H
+#define ARCH_UMC_REGS_H
+
+#define UMC_BASE 0x5b800000
+
+/* SSIF registers */
+#define UMC_SSIF_BASE UMC_BASE
+
+#define UMC_CPURST 0x00000700
+#define UMC_IDSRST 0x0000070C
+#define UMC_IXMRST 0x00000714
+#define UMC_HDMRST 0x00000718
+#define UMC_MDMRST 0x0000071C
+#define UMC_HDDRST 0x00000720
+#define UMC_MDDRST 0x00000724
+#define UMC_SIORST 0x00000728
+#define UMC_GIORST 0x0000072C
+#define UMC_HD2RST 0x00000734
+#define UMC_VIORST 0x0000073C
+#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
+#define UMC_DVCRST 0x00000748 /* Pro4 */
+#define UMC_RGLRST 0x00000750
+#define UMC_VPERST 0x00000758
+#define UMC_AIORST 0x00000764
+#define UMC_DMDRST 0x00000770
+
+#define UMC_HDMCHSEL 0x00000898
+#define UMC_MDMCHSEL 0x0000089C
+#define UMC_DVCCHSEL 0x000008C8
+#define UMC_DMDCHSEL 0x000008F0
+
+#define UMC_CLKEN_SSIF_FETCH 0x0000C060
+#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
+#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
+#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
+#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
+#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
+#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
+#define UMC_CLKEN_SSIF_WC 0x0000C07C
+#define UMC_CLKEN_SSIF_RC 0x0000C080
+#define UMC_CLKEN_SSIF_DST 0x0000C084
+
+/* CA registers */
+#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
+
+/* DRAM controller registers */
+#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
+
+#define UMC_CMDCTLA 0x00000000
+#define UMC_CMDCTLB 0x00000004
+#define UMC_INITCTLA 0x00000008
+#define UMC_INITCTLB 0x0000000C
+#define UMC_INITCTLC 0x00000010
+#define UMC_INITSET 0x00000014
+#define UMC_INITSTAT 0x00000018
+#define UMC_DRMMR0 0x0000001C
+#define UMC_DRMMR1 0x00000020
+#define UMC_DRMMR2 0x00000024
+#define UMC_DRMMR3 0x00000028
+#define UMC_SPCCTLA 0x00000030
+#define UMC_SPCCTLB 0x00000034
+#define UMC_SPCSETA 0x00000038
+#define UMC_SPCSETB 0x0000003C
+#define UMC_SPCSETC 0x00000040
+#define UMC_SPCSETD 0x00000044
+#define UMC_SPCSTATA 0x00000050
+#define UMC_SPCSTATB 0x00000054
+#define UMC_SPCSTATC 0x00000058
+#define UMC_ACSSETA 0x00000060
+#define UMC_FLOWCTLA 0x00000400
+#define UMC_FLOWCTLB 0x00000404
+#define UMC_FLOWCTLC 0x00000408
+#define UMC_FLOWCTLG 0x00000508
+#define UMC_RDATACTL_D0 0x00000600
+#define UMC_WDATACTL_D0 0x00000604
+#define UMC_RDATACTL_D1 0x00000608
+#define UMC_WDATACTL_D1 0x0000060C
+#define UMC_DATASET 0x00000610
+#define UMC_DCCGCTL 0x00000720
+#define UMC_DICGCTLA 0x00000724
+#define UMC_DICGCTLB 0x00000728
+#define UMC_DIOCTLA 0x00000C00
+#define UMC_DFICUPDCTLA 0x00000C20
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+static inline void umc_polling(u32 address, u32 expval, u32 mask)
+{
+ u32 nmask = ~mask;
+ u32 data;
+ do {
+ data = readl(address) & nmask;
+ } while (data != expval);
+}
+
+static inline void umc_dram_init_start(void __iomem *dramcont)
+{
+ writel(0x00000002, dramcont + UMC_INITSET);
+}
+
+static inline void umc_dram_init_poll(void __iomem *dramcont)
+{
+ while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
+ ;
+}
+
+#endif
+
+#endif
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+#include "../init.h"
+#include "../sg-regs.h"
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
{
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_ARM_MPCORE_H
-#define ARCH_ARM_MPCORE_H
-
-/* Snoop Control Unit */
-#define SCU_OFFSET 0x00
-
-/* SCU Control Register */
-#define SCU_CTRL 0x00
-/* SCU Configuration Register */
-#define SCU_CONF 0x04
-/* SCU CPU Power Status Register */
-#define SCU_PWR_STATUS 0x08
-/* SCU Invalidate All Registers in Secure State */
-#define SCU_INV_ALL 0x0C
-/* SCU Filtering Start Address Register */
-#define SCU_FILTER_START 0x40
-/* SCU Filtering End Address Register */
-#define SCU_FILTER_END 0x44
-/* SCU Access Control Register */
-#define SCU_SAC 0x50
-/* SCU Non-secure Access Control Register */
-#define SCU_SNSAC 0x54
-
-/* Global Timer */
-#define GLOBAL_TIMER_OFFSET 0x200
-
-/* Global Timer Counter Registers */
-#define GTIMER_CNT_L 0x00
-#define GTIMER_CNT_H 0x04
-/* Global Timer Control Register */
-#define GTIMER_CTRL 0x08
-/* Global Timer Interrupt Status Register */
-#define GTIMER_STAT 0x0C
-/* Comparator Value Registers */
-#define GTIMER_CMP_L 0x10
-#define GTIMER_CMP_H 0x14
-/* Auto-increment Register */
-#define GTIMER_INC 0x18
-
-#endif /* ARCH_ARM_MPCORE_H */
+++ /dev/null
-/*
- * UniPhier BCU (Bus Control Unit) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_BCU_REGS_H
-#define ARCH_BCU_REGS_H
-
-#define BCU_BASE 0x50080000
-
-#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4)
-#define BCSCR0 (BCSCR(0))
-#define BCSCR1 (BCSCR(1))
-#define BCSCR2 (BCSCR(2))
-#define BCSCR3 (BCSCR(3))
-#define BCSCR4 (BCSCR(4))
-#define BCSCR5 (BCSCR(5))
-
-#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4)
-#define BCIPPCCHR0 (BCIPPCCHR(0))
-#define BCIPPCCHR1 (BCIPPCCHR(1))
-#define BCIPPCCHR2 (BCIPPCCHR(2))
-#define BCIPPCCHR3 (BCIPPCCHR(3))
-#define BCIPPCCHR4 (BCIPPCCHR(4))
-#define BCIPPCCHR5 (BCIPPCCHR(5))
-
-#endif /* ARCH_BCU_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_BOOT_DEVICE_H_
-#define _ASM_BOOT_DEVICE_H_
-
-struct boot_device_info {
- u32 type;
- char *info;
-};
-
-u32 ph1_sld3_boot_device(void);
-u32 ph1_ld4_boot_device(void);
-u32 ph1_pro5_boot_device(void);
-u32 proxstream2_boot_device(void);
-
-void ph1_sld3_boot_mode_show(void);
-void ph1_ld4_boot_mode_show(void);
-void ph1_pro5_boot_mode_show(void);
-void proxstream2_boot_mode_show(void);
-
-#endif /* _ASM_BOOT_DEVICE_H_ */
+++ /dev/null
-/*
- * UniPhier DDR PHY registers
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_DDRPHY_REGS_H
-#define ARCH_DDRPHY_REGS_H
-
-#include <linux/bitops.h>
-#include <linux/compiler.h>
-
-#ifndef __ASSEMBLY__
-
-struct ddrphy {
- u32 ridr; /* Revision Identification Register */
- u32 pir; /* PHY Initialixation Register */
- u32 pgcr[2]; /* PHY General Configuration Register */
- u32 pgsr[2]; /* PHY General Status Register */
- u32 pllcr; /* PLL Control Register */
- u32 ptr[5]; /* PHY Timing Register */
- u32 acmdlr; /* AC Master Delay Line Register */
- u32 acbdlr; /* AC Bit Delay Line Register */
- u32 aciocr; /* AC I/O Configuration Register */
- u32 dxccr; /* DATX8 Common Configuration Register */
- u32 dsgcr; /* DDR System General Configuration Register */
- u32 dcr; /* DRAM Configuration Register */
- u32 dtpr[3]; /* DRAM Timing Parameters Register */
- u32 mr0; /* Mode Register 0 */
- u32 mr1; /* Mode Register 1 */
- u32 mr2; /* Mode Register 2 */
- u32 mr3; /* Mode Register 3 */
- u32 odtcr; /* ODT Configuration Register */
- u32 dtcr; /* Data Training Configuration Register */
- u32 dtar[4]; /* Data Training Address Register */
- u32 dtdr[2]; /* Data Training Data Register */
- u32 dtedr[2]; /* Data Training Eye Data Register */
- u32 pgcr2; /* PHY General Configuration Register 2 */
- u32 rsv0[8]; /* Reserved */
- u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
- u32 rdimmcr0[2]; /* RDIMM Control Register */
- u32 dcuar; /* DCU Address Register */
- u32 dcudr; /* DCU Data Register */
- u32 dcurr; /* DCU Run Register */
- u32 dculr; /* DCU Loop Register */
- u32 dcugcr; /* DCU General Configuration Register */
- u32 dcutpr; /* DCU Timing Parameters Register */
- u32 dcusr[2]; /* DCU Status Register */
- u32 rsv1[8]; /* Reserved */
- u32 bistrr; /* BIST Run Register */
- u32 bistwcr; /* BIST Word Count Register */
- u32 bistmskr[3]; /* BIST Mask Register */
- u32 bistlsr; /* BIST LFSR Sed Register */
- u32 bistar[3]; /* BIST Address Register */
- u32 bistudpr; /* BIST User Data Pattern Register */
- u32 bistgsr; /* BIST General Status Register */
- u32 bistwer; /* BIST Word Error Register */
- u32 bistber[4]; /* BIST Bit Error Register */
- u32 bistwcsr; /* BIST Word Count Status Register */
- u32 bistfwr[3]; /* BIST Fail Word Register */
- u32 rsv2[10]; /* Reserved */
- u32 gpr[2]; /* General Purpose Register */
- struct ddrphy_zq { /* ZQ */
- u32 cr[2]; /* Impedance Control Register */
- u32 sr[2]; /* Impedance Status Register */
- } zq[4];
- struct ddrphy_datx8 { /* DATX8 */
- u32 gcr; /* General Configuration Register */
- u32 gsr[2]; /* General Status Register */
- u32 bdlr[5]; /* Bit Delay Line Register */
- u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
- u32 mdlr; /* Master Delay Line Register */
- u32 gtr; /* General Timing Register */
- u32 gsr2; /* General Status Register 2 */
- u32 rsv[2]; /* Reserved */
- } dx[9];
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define PIR_INIT BIT(0) /* Initialization Trigger */
-#define PIR_ZCAL BIT(1) /* Impedance Calibration */
-#define PIR_PLLINIT BIT(4) /* PLL Initialization */
-#define PIR_DCAL BIT(5) /* DDL Calibration */
-#define PIR_PHYRST BIT(6) /* PHY Reset */
-#define PIR_DRAMRST BIT(7) /* DRAM Reset */
-#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
-#define PIR_WL BIT(9) /* Write Leveling */
-#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
-#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
-#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
-#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
-#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
-#define PIR_WREYE BIT(15) /* Write Data Eye Training */
-#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
-#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
-#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
-#define PIR_INITBYP BIT(31) /* Initialization Bypass */
-
-#define PGSR0_IDONE BIT(0) /* Initialization Done */
-#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
-#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
-#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
-#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
-#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
-#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
-#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
-#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
-#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
-#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
-#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
-#define PGSR0_IERR BIT(16) /* Initialization Error */
-#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
-#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
-#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
-#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
-#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
-#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
-#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
-#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
-#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
-#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
-#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
-#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
-#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
-#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
-
-#define DXCCR_DQSRES_OPEN (0 << 5)
-#define DXCCR_DQSRES_688_OHM (1 << 5)
-#define DXCCR_DQSRES_611_OHM (2 << 5)
-#define DXCCR_DQSRES_550_OHM (3 << 5)
-#define DXCCR_DQSRES_500_OHM (4 << 5)
-#define DXCCR_DQSRES_458_OHM (5 << 5)
-#define DXCCR_DQSRES_393_OHM (6 << 5)
-#define DXCCR_DQSRES_344_OHM (7 << 5)
-
-#define DXCCR_DQSNRES_OPEN (0 << 9)
-#define DXCCR_DQSNRES_688_OHM (1 << 9)
-#define DXCCR_DQSNRES_611_OHM (2 << 9)
-#define DXCCR_DQSNRES_550_OHM (3 << 9)
-#define DXCCR_DQSNRES_500_OHM (4 << 9)
-#define DXCCR_DQSNRES_458_OHM (5 << 9)
-#define DXCCR_DQSNRES_393_OHM (6 << 9)
-#define DXCCR_DQSNRES_344_OHM (7 << 9)
-
-#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
-#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
-#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
-#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
-#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
-
-#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
-#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
-
-/* SoC-specific parameters */
-#define NR_DATX8_PER_DDRPHY 2
-
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
-#define NR_DDRPHY_PER_CH 1
-#else
-#define NR_DDRPHY_PER_CH 2
-#endif
-
-#define NR_DDRCH 2
-
-#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
-
-#ifndef __ASSEMBLY__
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
-int ddrphy_training(struct ddrphy __iomem *phy);
-#endif
-
-#endif /* ARCH_DDRPHY_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MACH_INIT_H
-#define __MACH_INIT_H
-
-struct uniphier_board_data {
- unsigned long dram_ch0_base;
- unsigned long dram_ch0_size;
- unsigned long dram_ch0_width;
- unsigned long dram_ch1_base;
- unsigned long dram_ch1_size;
- unsigned long dram_ch1_width;
- unsigned long dram_ch2_base;
- unsigned long dram_ch2_size;
- unsigned long dram_ch2_width;
- unsigned int dram_freq;
-};
-
-const struct uniphier_board_data *uniphier_get_board_param(void);
-
-int ph1_sld3_init(const struct uniphier_board_data *bd);
-int ph1_ld4_init(const struct uniphier_board_data *bd);
-int ph1_pro4_init(const struct uniphier_board_data *bd);
-int ph1_sld8_init(const struct uniphier_board_data *bd);
-int ph1_pro5_init(const struct uniphier_board_data *bd);
-int proxstream2_init(const struct uniphier_board_data *bd);
-
-#if defined(CONFIG_MICRO_SUPPORT_CARD)
-int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
-int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
-int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
-int proxstream2_sbc_init(const struct uniphier_board_data *bd);
-#else
-static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
-{
- return 0;
-}
-
-static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
-{
- return 0;
-}
-
-static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
-{
- return 0;
-}
-
-static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
-{
- return 0;
-}
-#endif
-
-int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
-int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
-
-int memconf_init(const struct uniphier_board_data *bd);
-int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
-int proxstream2_memconf_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
-int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
-int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
-int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
-int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
-
-int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
-int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
-int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
-
-int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
-int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
-int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
-
-void ph1_sld3_pin_init(void);
-void ph1_ld4_pin_init(void);
-void ph1_pro4_pin_init(void);
-void ph1_sld8_pin_init(void);
-void ph1_pro5_pin_init(void);
-void proxstream2_pin_init(void);
-void ph1_ld6b_pin_init(void);
-
-void ph1_ld4_clk_init(void);
-void ph1_pro4_clk_init(void);
-void ph1_pro5_clk_init(void);
-void proxstream2_clk_init(void);
-
-#define pr_err(fmt, args...) printf(fmt, ##args)
-
-#endif /* __MACH_INIT_H */
+++ /dev/null
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_BOARD_H
-#define ARCH_BOARD_H
-
-#if defined(CONFIG_MICRO_SUPPORT_CARD)
-void support_card_reset(void);
-void support_card_init(void);
-void support_card_late_init(void);
-int check_support_card(void);
-void led_puts(const char *s);
-#else
-static inline void support_card_reset(void)
-{
-}
-
-static inline void support_card_init(void)
-{
-}
-
-static inline void support_card_late_init(void)
-{
-}
-
-static inline int check_support_card(void)
-{
- return 0;
-}
-
-static inline void led_puts(const char *s)
-{
-}
-#endif
-
-#endif /* ARCH_BOARD_H */
+++ /dev/null
-/*
- * UniPhier SBC (System Bus Controller) registers
- *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SBC_REGS_H
-#define ARCH_SBC_REGS_H
-
-#define SBBASE_BASE 0x58c00100
-#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
-
-#define SBBASE0 (SBBASE(0))
-#define SBBASE1 (SBBASE(1))
-#define SBBASE2 (SBBASE(2))
-#define SBBASE3 (SBBASE(3))
-#define SBBASE4 (SBBASE(4))
-#define SBBASE5 (SBBASE(5))
-#define SBBASE6 (SBBASE(6))
-#define SBBASE7 (SBBASE(7))
-
-#define SBBASE_BANK_ENABLE (0x00000001)
-
-#define SBCTRL_BASE 0x58c00200
-#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
-
-#define SBCTRL00 SBCTRL(0, 0)
-#define SBCTRL01 SBCTRL(0, 1)
-#define SBCTRL02 SBCTRL(0, 2)
-#define SBCTRL03 SBCTRL(0, 3)
-#define SBCTRL04 (SBCTRL_BASE + 0x100)
-
-#define SBCTRL10 SBCTRL(1, 0)
-#define SBCTRL11 SBCTRL(1, 1)
-#define SBCTRL12 SBCTRL(1, 2)
-#define SBCTRL13 SBCTRL(1, 3)
-#define SBCTRL14 (SBCTRL_BASE + 0x110)
-
-#define SBCTRL20 SBCTRL(2, 0)
-#define SBCTRL21 SBCTRL(2, 1)
-#define SBCTRL22 SBCTRL(2, 2)
-#define SBCTRL23 SBCTRL(2, 3)
-#define SBCTRL24 (SBCTRL_BASE + 0x120)
-
-#define SBCTRL30 SBCTRL(3, 0)
-#define SBCTRL31 SBCTRL(3, 1)
-#define SBCTRL32 SBCTRL(3, 2)
-#define SBCTRL33 SBCTRL(3, 3)
-#define SBCTRL34 (SBCTRL_BASE + 0x130)
-
-#define SBCTRL40 SBCTRL(4, 0)
-#define SBCTRL41 SBCTRL(4, 1)
-#define SBCTRL42 SBCTRL(4, 2)
-#define SBCTRL43 SBCTRL(4, 3)
-#define SBCTRL44 (SBCTRL_BASE + 0x140)
-
-#define SBCTRL50 SBCTRL(5, 0)
-#define SBCTRL51 SBCTRL(5, 1)
-#define SBCTRL52 SBCTRL(5, 2)
-#define SBCTRL53 SBCTRL(5, 3)
-#define SBCTRL54 (SBCTRL_BASE + 0x150)
-
-#define SBCTRL60 SBCTRL(6, 0)
-#define SBCTRL61 SBCTRL(6, 1)
-#define SBCTRL62 SBCTRL(6, 2)
-#define SBCTRL63 SBCTRL(6, 3)
-#define SBCTRL64 (SBCTRL_BASE + 0x160)
-
-#define SBCTRL70 SBCTRL(7, 0)
-#define SBCTRL71 SBCTRL(7, 1)
-#define SBCTRL72 SBCTRL(7, 2)
-#define SBCTRL73 SBCTRL(7, 3)
-#define SBCTRL74 (SBCTRL_BASE + 0x170)
-
-/* slower but LED works */
-#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
-#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
-
-/* faster but LED does not work */
-#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
-/* NOR flash needs more wait counts than SRAM */
-#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
-
-#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
-
-#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
-
-#define PC0CTRL 0x598000c0
-#define ROM_BOOT_ROMRSV2 0x59801208
-
-#ifndef __ASSEMBLY__
-#include <linux/io.h>
-static inline int boot_is_swapped(void)
-{
- return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
-}
-#endif
-
-#endif /* ARCH_SBC_REGS_H */
+++ /dev/null
-/*
- * UniPhier SC (System Control) block registers
- *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SC_REGS_H
-#define ARCH_SC_REGS_H
-
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
-#define SC_BASE_ADDR 0xf1840000
-#else
-#define SC_BASE_ADDR 0x61840000
-#endif
-
-#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
-#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
-#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
-
-#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
-#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
-#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
-#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
-
-#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
-#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
-
-#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
-#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
-#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
-
-#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
-
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
-#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
-#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
-
-#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
-#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
-#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
-
-#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
-#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
-#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
-#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
-#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
-#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
-/* Pro4 or older */
-#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
-#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
-#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
-
-#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
-#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
-#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
-
-#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
-
-/* Pro5 or newer */
-#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
-#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
-#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
-#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
-#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
-#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
-#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
-#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
-
-#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
-#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
-#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
-#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
-#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
-#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
-#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
-/* Pro4 or older */
-#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
-#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
-#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
-#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
-
-/* Pro5 or newer */
-#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
-#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
-#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
-#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
-#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
-
-/* System reset control register */
-#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
-#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
-#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
-
-#endif /* ARCH_SC_REGS_H */
+++ /dev/null
-/*
- * UniPhier SG (SoC Glue) block registers
- *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SG_REGS_H
-#define ARCH_SG_REGS_H
-
-/* Base Address */
-#define SG_CTRL_BASE 0x5f800000
-#define SG_DBG_BASE 0x5f900000
-
-/* Revision */
-#define SG_REVISION (SG_CTRL_BASE | 0x0000)
-#define SG_REVISION_TYPE_SHIFT 16
-#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
-#define SG_REVISION_MODEL_SHIFT 8
-#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
-#define SG_REVISION_REV_SHIFT 0
-#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
-
-/* Memory Configuration */
-#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
-
-#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
-#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
-#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
-#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
-#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
-#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
-#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
-
-#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
-#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
-#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
-#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
-#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
-#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
-#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
-
-#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
-#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
-#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
-#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
-#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
-#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
-#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
-#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
-/* PH1-LD6b, ProXstream2 only */
-#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
-
-#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
-
-/* Pin Control */
-#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
-
-/* PH1-Pro4, PH1-Pro5 */
-#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
-
-/* Input Enable */
-#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
-
-/* Pin Monitor */
-#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
-
-#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
-
-#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
-
-#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
-
-#ifdef __ASSEMBLY__
-
- .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
- ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
- ldr \rd, [\ra]
- and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
- orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
- str \rd, [\ra]
- .endm
-
-#else
-
-#include <linux/types.h>
-#include <linux/io.h>
-
-static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
- unsigned mux_bits, unsigned reg_stride)
-{
- unsigned shift = pin * mux_bits % 32;
- unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
- u32 mask = (1U << mux_bits) - 1;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~(mask << shift);
- tmp |= (mask & muxval) << shift;
- writel(tmp, reg);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* ARCH_SG_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MACH_SOC_INFO_H__
-#define __MACH_SOC_INFO_H__
-
-enum uniphier_soc_id {
- SOC_UNIPHIER_PH1_SLD3,
- SOC_UNIPHIER_PH1_LD4,
- SOC_UNIPHIER_PH1_PRO4,
- SOC_UNIPHIER_PH1_SLD8,
- SOC_UNIPHIER_PH1_PRO5,
- SOC_UNIPHIER_PROXSTREAM2,
- SOC_UNIPHIER_PH1_LD6B,
- SOC_UNIPHIER_PH1_SLD11,
- SOC_UNIPHIER_PH1_LD10,
- SOC_UNIPHIER_UNKNOWN,
-};
-
-#define UNIPHIER_NR_ENABLED_SOCS \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10)
-
-#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
-
-#if UNIPHIER_MULTI_SOC
-enum uniphier_soc_id uniphier_get_soc_type(void);
-#else
-static inline enum uniphier_soc_id uniphier_get_soc_type(void)
-{
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- return SOC_UNIPHIER_PH1_SLD3;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
- return SOC_UNIPHIER_PH1_LD4;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
- return SOC_UNIPHIER_PH1_PRO4;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- return SOC_UNIPHIER_PH1_SLD8;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- return SOC_UNIPHIER_PH1_PRO5;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
- return SOC_UNIPHIER_PROXSTREAM2;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- return SOC_UNIPHIER_PH1_LD6B;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11)
- return SOC_UNIPHIER_PH1_SLD11;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10)
- return SOC_UNIPHIER_PH1_LD10;
-#endif
-
- return SOC_UNIPHIER_UNKNOWN;
-}
-#endif
-
-int uniphier_get_soc_model(void);
-int uniphier_get_soc_revision(void);
-
-#endif /* __MACH_SOC_INFO_H__ */
+++ /dev/null
-/*
- * UniPhier System Cache (L2 Cache) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SSC_REGS_H
-#define ARCH_SSC_REGS_H
-
-#define SSCC 0x500c0000
-#define SSCC_BST (0x1 << 20)
-#define SSCC_ACT (0x1 << 19)
-#define SSCC_WTG (0x1 << 18)
-#define SSCC_PRD (0x1 << 17)
-#define SSCC_WBWA (0x1 << 16)
-#define SSCC_EX (0x1 << 13)
-#define SSCC_ON (0x1 << 0)
-
-#define SSCLPDAWCR 0x500c0030
-
-#define SSCOPE 0x506c0244
-#define SSCOPE_CM_SYNC 0x00000008
-
-#define SSCOQM 0x506c0248
-#define SSCOQM_TID_MASK (0x3 << 21)
-#define SSCOQM_TID_BY_WAY (0x2 << 21)
-#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
-#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
-#define SSCOQM_S_MASK (0x3 << 17)
-#define SSCOQM_S_WAY (0x2 << 17)
-#define SSCOQM_S_ALL (0x1 << 17)
-#define SSCOQM_S_ADDRESS (0x0 << 17)
-#define SSCOQM_CE (0x1 << 15)
-#define SSCOQM_CW (0x1 << 14)
-#define SSCOQM_CM_MASK (0x7)
-#define SSCOQM_CM_DIRT_TOUCH (0x7)
-#define SSCOQM_CM_ZERO_TOUCH (0x6)
-#define SSCOQM_CM_NORM_TOUCH (0x5)
-#define SSCOQM_CM_PREF_FETCH (0x4)
-#define SSCOQM_CM_SSC_FETCH (0x3)
-#define SSCOQM_CM_WB_INV (0x2)
-#define SSCOQM_CM_WB (0x1)
-#define SSCOQM_CM_INV (0x0)
-
-#define SSCOQAD 0x506c024c
-#define SSCOQSZ 0x506c0250
-#define SSCOQWN 0x506c0258
-
-#define SSCOPPQSEF 0x506c025c
-#define SSCOPPQSEF_FE (0x1 << 1)
-#define SSCOPPQSEF_OE (0x1 << 0)
-
-#define SSCOLPQS 0x506c0260
-#define SSCOLPQS_EF (0x1 << 2)
-#define SSCOLPQS_EST (0x1 << 1)
-#define SSCOLPQS_QST (0x1 << 0)
-
-#define SSCOQCE0 0x506c0270
-
-#define SSC_LINE_SIZE 128
-#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
-
-#endif /* ARCH_SSC_REGS_H */
+++ /dev/null
-/*
- * UniPhier UMC (Universal Memory Controller) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_UMC_REGS_H
-#define ARCH_UMC_REGS_H
-
-#define UMC_BASE 0x5b800000
-
-/* SSIF registers */
-#define UMC_SSIF_BASE UMC_BASE
-
-#define UMC_CPURST 0x00000700
-#define UMC_IDSRST 0x0000070C
-#define UMC_IXMRST 0x00000714
-#define UMC_HDMRST 0x00000718
-#define UMC_MDMRST 0x0000071C
-#define UMC_HDDRST 0x00000720
-#define UMC_MDDRST 0x00000724
-#define UMC_SIORST 0x00000728
-#define UMC_GIORST 0x0000072C
-#define UMC_HD2RST 0x00000734
-#define UMC_VIORST 0x0000073C
-#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
-#define UMC_DVCRST 0x00000748 /* Pro4 */
-#define UMC_RGLRST 0x00000750
-#define UMC_VPERST 0x00000758
-#define UMC_AIORST 0x00000764
-#define UMC_DMDRST 0x00000770
-
-#define UMC_HDMCHSEL 0x00000898
-#define UMC_MDMCHSEL 0x0000089C
-#define UMC_DVCCHSEL 0x000008C8
-#define UMC_DMDCHSEL 0x000008F0
-
-#define UMC_CLKEN_SSIF_FETCH 0x0000C060
-#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
-#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
-#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
-#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
-#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
-#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
-#define UMC_CLKEN_SSIF_WC 0x0000C07C
-#define UMC_CLKEN_SSIF_RC 0x0000C080
-#define UMC_CLKEN_SSIF_DST 0x0000C084
-
-/* CA registers */
-#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
-
-/* DRAM controller registers */
-#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
-
-#define UMC_CMDCTLA 0x00000000
-#define UMC_CMDCTLB 0x00000004
-#define UMC_INITCTLA 0x00000008
-#define UMC_INITCTLB 0x0000000C
-#define UMC_INITCTLC 0x00000010
-#define UMC_INITSET 0x00000014
-#define UMC_INITSTAT 0x00000018
-#define UMC_DRMMR0 0x0000001C
-#define UMC_DRMMR1 0x00000020
-#define UMC_DRMMR2 0x00000024
-#define UMC_DRMMR3 0x00000028
-#define UMC_SPCCTLA 0x00000030
-#define UMC_SPCCTLB 0x00000034
-#define UMC_SPCSETA 0x00000038
-#define UMC_SPCSETB 0x0000003C
-#define UMC_SPCSETC 0x00000040
-#define UMC_SPCSETD 0x00000044
-#define UMC_SPCSTATA 0x00000050
-#define UMC_SPCSTATB 0x00000054
-#define UMC_SPCSTATC 0x00000058
-#define UMC_ACSSETA 0x00000060
-#define UMC_FLOWCTLA 0x00000400
-#define UMC_FLOWCTLB 0x00000404
-#define UMC_FLOWCTLC 0x00000408
-#define UMC_FLOWCTLG 0x00000508
-#define UMC_RDATACTL_D0 0x00000600
-#define UMC_WDATACTL_D0 0x00000604
-#define UMC_RDATACTL_D1 0x00000608
-#define UMC_WDATACTL_D1 0x0000060C
-#define UMC_DATASET 0x00000610
-#define UMC_DCCGCTL 0x00000720
-#define UMC_DICGCTLA 0x00000724
-#define UMC_DICGCTLB 0x00000728
-#define UMC_DIOCTLA 0x00000C00
-#define UMC_DFICUPDCTLA 0x00000C20
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-static inline void umc_polling(u32 address, u32 expval, u32 mask)
-{
- u32 nmask = ~mask;
- u32 data;
- do {
- data = readl(address) & nmask;
- } while (data != expval);
-}
-
-static inline void umc_dram_init_start(void __iomem *dramcont)
-{
- writel(0x00000002, dramcont + UMC_INITSET);
-}
-
-static inline void umc_dram_init_poll(void __iomem *dramcont)
-{
- while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
- ;
-}
-
-#endif
-
-#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_INIT_H
+#define __MACH_INIT_H
+
+struct uniphier_board_data {
+ unsigned long dram_ch0_base;
+ unsigned long dram_ch0_size;
+ unsigned long dram_ch0_width;
+ unsigned long dram_ch1_base;
+ unsigned long dram_ch1_size;
+ unsigned long dram_ch1_width;
+ unsigned long dram_ch2_base;
+ unsigned long dram_ch2_size;
+ unsigned long dram_ch2_width;
+ unsigned int dram_freq;
+};
+
+const struct uniphier_board_data *uniphier_get_board_param(void);
+
+int ph1_sld3_init(const struct uniphier_board_data *bd);
+int ph1_ld4_init(const struct uniphier_board_data *bd);
+int ph1_pro4_init(const struct uniphier_board_data *bd);
+int ph1_sld8_init(const struct uniphier_board_data *bd);
+int ph1_pro5_init(const struct uniphier_board_data *bd);
+int proxstream2_init(const struct uniphier_board_data *bd);
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
+int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
+int proxstream2_sbc_init(const struct uniphier_board_data *bd);
+#else
+static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+#endif
+
+int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
+int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
+
+int memconf_init(const struct uniphier_board_data *bd);
+int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
+int proxstream2_memconf_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
+int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
+int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
+int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
+int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
+
+int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
+int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
+int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
+
+int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
+int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
+
+void ph1_sld3_pin_init(void);
+void ph1_ld4_pin_init(void);
+void ph1_pro4_pin_init(void);
+void ph1_sld8_pin_init(void);
+void ph1_pro5_pin_init(void);
+void proxstream2_pin_init(void);
+void ph1_ld6b_pin_init(void);
+
+void ph1_ld4_clk_init(void);
+void ph1_pro4_clk_init(void);
+void ph1_pro5_clk_init(void);
+void proxstream2_clk_init(void);
+
+#define pr_err(fmt, args...) printf(fmt, ##args)
+
+#endif /* __MACH_INIT_H */
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_ld4_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_pro4_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_pro5_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_sld3_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_sld8_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int proxstream2_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/soc_info.h>
+
+#include "../init.h"
+#include "../soc-info.h"
void spl_board_init(void)
{
*/
#include <linux/linkage.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
ENTRY(lowlevel_init)
ldr r1, = SSCC
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int proxstream2_memconf_init(const struct uniphier_board_data *bd)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int memconf_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/ctype.h>
#include <linux/io.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
#define MICRO_SUPPORT_CARD_BASE 0x43f00000
#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
--- /dev/null
+/*
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_BOARD_H
+#define ARCH_BOARD_H
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+void support_card_reset(void);
+void support_card_init(void);
+void support_card_late_init(void);
+int check_support_card(void);
+void led_puts(const char *s);
+#else
+static inline void support_card_reset(void)
+{
+}
+
+static inline void support_card_init(void)
+{
+}
+
+static inline void support_card_late_init(void)
+{
+}
+
+static inline int check_support_card(void)
+{
+ return 0;
+}
+
+static inline void led_puts(const char *s)
+{
+}
+#endif
+
+#endif /* ARCH_BOARD_H */
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_ld4_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_ld6b_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_pro4_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_pro5_pin_init(void)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_sld3_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_sld8_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void proxstream2_pin_init(void)
{
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
+#include "../init.h"
int ph1_sld3_pll_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
static void dpll_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
/*
- * Copyright (C) 2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/micro-support-card.h>
+#include "micro-support-card.h"
int misc_init_f(void)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/sc-regs.h>
+
+#include "sc-regs.h"
void reset_cpu(unsigned long ignored)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int proxstream2_sbc_init(const struct uniphier_board_data *bd)
{
--- /dev/null
+/*
+ * UniPhier SBC (System Bus Controller) registers
+ *
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SBC_REGS_H
+#define ARCH_SBC_REGS_H
+
+#define SBBASE_BASE 0x58c00100
+#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
+
+#define SBBASE0 (SBBASE(0))
+#define SBBASE1 (SBBASE(1))
+#define SBBASE2 (SBBASE(2))
+#define SBBASE3 (SBBASE(3))
+#define SBBASE4 (SBBASE(4))
+#define SBBASE5 (SBBASE(5))
+#define SBBASE6 (SBBASE(6))
+#define SBBASE7 (SBBASE(7))
+
+#define SBBASE_BANK_ENABLE (0x00000001)
+
+#define SBCTRL_BASE 0x58c00200
+#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
+
+#define SBCTRL00 SBCTRL(0, 0)
+#define SBCTRL01 SBCTRL(0, 1)
+#define SBCTRL02 SBCTRL(0, 2)
+#define SBCTRL03 SBCTRL(0, 3)
+#define SBCTRL04 (SBCTRL_BASE + 0x100)
+
+#define SBCTRL10 SBCTRL(1, 0)
+#define SBCTRL11 SBCTRL(1, 1)
+#define SBCTRL12 SBCTRL(1, 2)
+#define SBCTRL13 SBCTRL(1, 3)
+#define SBCTRL14 (SBCTRL_BASE + 0x110)
+
+#define SBCTRL20 SBCTRL(2, 0)
+#define SBCTRL21 SBCTRL(2, 1)
+#define SBCTRL22 SBCTRL(2, 2)
+#define SBCTRL23 SBCTRL(2, 3)
+#define SBCTRL24 (SBCTRL_BASE + 0x120)
+
+#define SBCTRL30 SBCTRL(3, 0)
+#define SBCTRL31 SBCTRL(3, 1)
+#define SBCTRL32 SBCTRL(3, 2)
+#define SBCTRL33 SBCTRL(3, 3)
+#define SBCTRL34 (SBCTRL_BASE + 0x130)
+
+#define SBCTRL40 SBCTRL(4, 0)
+#define SBCTRL41 SBCTRL(4, 1)
+#define SBCTRL42 SBCTRL(4, 2)
+#define SBCTRL43 SBCTRL(4, 3)
+#define SBCTRL44 (SBCTRL_BASE + 0x140)
+
+#define SBCTRL50 SBCTRL(5, 0)
+#define SBCTRL51 SBCTRL(5, 1)
+#define SBCTRL52 SBCTRL(5, 2)
+#define SBCTRL53 SBCTRL(5, 3)
+#define SBCTRL54 (SBCTRL_BASE + 0x150)
+
+#define SBCTRL60 SBCTRL(6, 0)
+#define SBCTRL61 SBCTRL(6, 1)
+#define SBCTRL62 SBCTRL(6, 2)
+#define SBCTRL63 SBCTRL(6, 3)
+#define SBCTRL64 (SBCTRL_BASE + 0x160)
+
+#define SBCTRL70 SBCTRL(7, 0)
+#define SBCTRL71 SBCTRL(7, 1)
+#define SBCTRL72 SBCTRL(7, 2)
+#define SBCTRL73 SBCTRL(7, 3)
+#define SBCTRL74 (SBCTRL_BASE + 0x170)
+
+/* slower but LED works */
+#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
+#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
+#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
+#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
+
+/* faster but LED does not work */
+#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
+#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
+#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
+
+#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
+
+#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
+
+#define PC0CTRL 0x598000c0
+#define ROM_BOOT_ROMRSV2 0x59801208
+
+#ifndef __ASSEMBLY__
+#include <linux/io.h>
+static inline int boot_is_swapped(void)
+{
+ return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
+#endif
+
+#endif /* ARCH_SBC_REGS_H */
--- /dev/null
+/*
+ * UniPhier SC (System Control) block registers
+ *
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SC_REGS_H
+#define ARCH_SC_REGS_H
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+#define SC_BASE_ADDR 0xf1840000
+#else
+#define SC_BASE_ADDR 0x61840000
+#endif
+
+#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
+#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
+#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
+
+#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
+#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
+#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
+#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
+
+#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
+#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
+
+#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
+#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
+#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
+
+#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
+
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
+#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
+#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
+
+#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
+#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
+#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
+
+#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
+#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
+#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
+#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
+#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
+/* Pro4 or older */
+#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
+#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
+#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
+
+#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
+#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
+
+#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
+
+/* Pro5 or newer */
+#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
+#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
+#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
+#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
+#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
+#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
+#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
+#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
+
+#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
+#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
+#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
+#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
+#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
+#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
+/* Pro4 or older */
+#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
+#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
+#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
+#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
+
+/* Pro5 or newer */
+#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
+#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
+#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
+#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
+
+/* System reset control register */
+#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
+#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
+#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
+
+#endif /* ARCH_SC_REGS_H */
--- /dev/null
+/*
+ * UniPhier SG (SoC Glue) block registers
+ *
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SG_REGS_H
+#define ARCH_SG_REGS_H
+
+/* Base Address */
+#define SG_CTRL_BASE 0x5f800000
+#define SG_DBG_BASE 0x5f900000
+
+/* Revision */
+#define SG_REVISION (SG_CTRL_BASE | 0x0000)
+#define SG_REVISION_TYPE_SHIFT 16
+#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
+#define SG_REVISION_MODEL_SHIFT 8
+#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
+#define SG_REVISION_REV_SHIFT 0
+#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
+
+/* Memory Configuration */
+#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
+
+#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
+#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
+#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
+
+#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
+#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
+#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
+
+#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
+#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
+#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
+/* PH1-LD6b, ProXstream2 only */
+#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
+
+#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
+
+/* Pin Control */
+#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
+
+/* PH1-Pro4, PH1-Pro5 */
+#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
+
+/* Input Enable */
+#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
+
+/* Pin Monitor */
+#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
+
+#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
+
+#ifdef __ASSEMBLY__
+
+ .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
+ ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
+ ldr \rd, [\ra]
+ and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
+ orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
+ str \rd, [\ra]
+ .endm
+
+#else
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
+ unsigned mux_bits, unsigned reg_stride)
+{
+ unsigned shift = pin * mux_bits % 32;
+ unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
+ u32 mask = (1U << mux_bits) - 1;
+ u32 tmp;
+
+ tmp = readl(reg);
+ tmp &= ~(mask << shift);
+ tmp |= (mask & muxval) << shift;
+ writel(tmp, reg);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* ARCH_SG_REGS_H */
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_SOC_INFO_H__
+#define __MACH_SOC_INFO_H__
+
+enum uniphier_soc_id {
+ SOC_UNIPHIER_PH1_SLD3,
+ SOC_UNIPHIER_PH1_LD4,
+ SOC_UNIPHIER_PH1_PRO4,
+ SOC_UNIPHIER_PH1_SLD8,
+ SOC_UNIPHIER_PH1_PRO5,
+ SOC_UNIPHIER_PROXSTREAM2,
+ SOC_UNIPHIER_PH1_LD6B,
+ SOC_UNIPHIER_PH1_SLD11,
+ SOC_UNIPHIER_PH1_LD10,
+ SOC_UNIPHIER_UNKNOWN,
+};
+
+#define UNIPHIER_NR_ENABLED_SOCS \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10)
+
+#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
+
+#if UNIPHIER_MULTI_SOC
+enum uniphier_soc_id uniphier_get_soc_type(void);
+#else
+static inline enum uniphier_soc_id uniphier_get_soc_type(void)
+{
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ return SOC_UNIPHIER_PH1_SLD3;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ return SOC_UNIPHIER_PH1_LD4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ return SOC_UNIPHIER_PH1_PRO4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ return SOC_UNIPHIER_PH1_SLD8;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ return SOC_UNIPHIER_PH1_PRO5;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+ return SOC_UNIPHIER_PROXSTREAM2;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ return SOC_UNIPHIER_PH1_LD6B;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11)
+ return SOC_UNIPHIER_PH1_SLD11;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10)
+ return SOC_UNIPHIER_PH1_LD10;
+#endif
+
+ return SOC_UNIPHIER_UNKNOWN;
+}
+#endif
+
+int uniphier_get_soc_model(void);
+int uniphier_get_soc_revision(void);
+
+#endif /* __MACH_SOC_INFO_H__ */
#include <linux/io.h>
#include <linux/types.h>
-#include <mach/sg-regs.h>
-#include <mach/soc_info.h>
+
+#include "sg-regs.h"
+#include "soc-info.h"
#if UNIPHIER_MULTI_SOC
enum uniphier_soc_id uniphier_get_soc_type(void)
--- /dev/null
+/*
+ * UniPhier System Cache (L2 Cache) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SSC_REGS_H
+#define ARCH_SSC_REGS_H
+
+#define SSCC 0x500c0000
+#define SSCC_BST (0x1 << 20)
+#define SSCC_ACT (0x1 << 19)
+#define SSCC_WTG (0x1 << 18)
+#define SSCC_PRD (0x1 << 17)
+#define SSCC_WBWA (0x1 << 16)
+#define SSCC_EX (0x1 << 13)
+#define SSCC_ON (0x1 << 0)
+
+#define SSCLPDAWCR 0x500c0030
+
+#define SSCOPE 0x506c0244
+#define SSCOPE_CM_SYNC 0x00000008
+
+#define SSCOQM 0x506c0248
+#define SSCOQM_TID_MASK (0x3 << 21)
+#define SSCOQM_TID_BY_WAY (0x2 << 21)
+#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
+#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
+#define SSCOQM_S_MASK (0x3 << 17)
+#define SSCOQM_S_WAY (0x2 << 17)
+#define SSCOQM_S_ALL (0x1 << 17)
+#define SSCOQM_S_ADDRESS (0x0 << 17)
+#define SSCOQM_CE (0x1 << 15)
+#define SSCOQM_CW (0x1 << 14)
+#define SSCOQM_CM_MASK (0x7)
+#define SSCOQM_CM_DIRT_TOUCH (0x7)
+#define SSCOQM_CM_ZERO_TOUCH (0x6)
+#define SSCOQM_CM_NORM_TOUCH (0x5)
+#define SSCOQM_CM_PREF_FETCH (0x4)
+#define SSCOQM_CM_SSC_FETCH (0x3)
+#define SSCOQM_CM_WB_INV (0x2)
+#define SSCOQM_CM_WB (0x1)
+#define SSCOQM_CM_INV (0x0)
+
+#define SSCOQAD 0x506c024c
+#define SSCOQSZ 0x506c0250
+#define SSCOQWN 0x506c0258
+
+#define SSCOPPQSEF 0x506c025c
+#define SSCOPPQSEF_FE (0x1 << 1)
+#define SSCOPPQSEF_OE (0x1 << 0)
+
+#define SSCOLPQS 0x506c0260
+#define SSCOLPQS_EF (0x1 << 2)
+#define SSCOLPQS_EST (0x1 << 1)
+#define SSCOLPQS_QST (0x1 << 0)
+
+#define SSCOQCE0 0x506c0270
+
+#define SSC_LINE_SIZE 128
+#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
+
+#endif /* ARCH_SSC_REGS_H */
#include <common.h>
#include <linux/io.h>
-#include <mach/arm-mpcore.h>
+
+#include "arm-mpcore.h"
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
projects / oweals / u-boot.git / commitdiff