* PLL configuration preset list
* =============================
*/
-#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50)
+#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_410_410_205) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_420_420_210) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(33, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_430_430_215) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(34, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(410)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_440_440_220) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(35, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(205)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(22, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_450_450_225) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(45, 2, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_460_460_230) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_470_470_235) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(37, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_480_480_240) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(38, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(410)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_490_490_245) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(39, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(205)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250) /* Tested! */
#define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
#define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_510_510_255) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_520_520_260) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(41, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_530_265_132) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(42, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(410)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_540_270_135) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(43, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(205)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_275_137) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_280_140) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_570_285_142) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(45, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_580_290_145) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(46, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(410)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(29, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
#else
#error "QCA PLL configuration not supported or not selected!"
#endif
#define QCA_PLL_PRESET_400_300_300 44
#define QCA_PLL_PRESET_400_400_200 45
#define QCA_PLL_PRESET_400_400_300 46
-#define QCA_PLL_PRESET_500_200_100 47
-#define QCA_PLL_PRESET_500_200_150 48
-#define QCA_PLL_PRESET_500_200_200 49
-#define QCA_PLL_PRESET_500_300_100 50
-#define QCA_PLL_PRESET_500_300_150 51
-#define QCA_PLL_PRESET_500_300_200 52
-#define QCA_PLL_PRESET_500_300_250 53
-#define QCA_PLL_PRESET_500_300_300 54
-#define QCA_PLL_PRESET_500_400_100 55
-#define QCA_PLL_PRESET_500_400_200 56
-#define QCA_PLL_PRESET_500_400_250 57
-#define QCA_PLL_PRESET_500_500_100 58
-#define QCA_PLL_PRESET_500_500_150 59
-#define QCA_PLL_PRESET_500_500_200 60
-#define QCA_PLL_PRESET_500_500_250 61
-#define QCA_PLL_PRESET_500_500_300 62
-#define QCA_PLL_PRESET_550_200_100 63
-#define QCA_PLL_PRESET_550_200_150 64
-#define QCA_PLL_PRESET_550_200_200 65
-#define QCA_PLL_PRESET_550_300_100 66
-#define QCA_PLL_PRESET_550_300_150 67
-#define QCA_PLL_PRESET_550_300_200 68
-#define QCA_PLL_PRESET_550_300_275 69
-#define QCA_PLL_PRESET_550_300_300 70
-#define QCA_PLL_PRESET_550_375_250 71
-#define QCA_PLL_PRESET_550_400_200 72
-#define QCA_PLL_PRESET_560_450_225 73
-#define QCA_PLL_PRESET_600_200_100 74
-#define QCA_PLL_PRESET_600_200_150 75
-#define QCA_PLL_PRESET_600_200_200 76
-#define QCA_PLL_PRESET_600_300_100 77
-#define QCA_PLL_PRESET_600_300_150 78
-#define QCA_PLL_PRESET_600_300_200 79
-#define QCA_PLL_PRESET_600_300_250 80
-#define QCA_PLL_PRESET_600_300_300 81
-#define QCA_PLL_PRESET_600_400_100 82
-#define QCA_PLL_PRESET_600_400_150 83
-#define QCA_PLL_PRESET_600_400_200 84
-#define QCA_PLL_PRESET_600_400_300 85
-#define QCA_PLL_PRESET_600_450_100 86
-#define QCA_PLL_PRESET_600_450_150 87
-#define QCA_PLL_PRESET_600_450_200 88
-#define QCA_PLL_PRESET_600_450_225 89
-#define QCA_PLL_PRESET_600_450_300 90
-#define QCA_PLL_PRESET_600_500_100 91
-#define QCA_PLL_PRESET_600_500_150 92
-#define QCA_PLL_PRESET_600_500_200 93
-#define QCA_PLL_PRESET_600_500_250 94
-#define QCA_PLL_PRESET_600_500_300 95
-#define QCA_PLL_PRESET_600_550_100 96
-#define QCA_PLL_PRESET_600_550_150 97
-#define QCA_PLL_PRESET_600_550_200 98
-#define QCA_PLL_PRESET_600_550_275 99
-#define QCA_PLL_PRESET_600_550_300 100
-#define QCA_PLL_PRESET_600_600_100 101
-#define QCA_PLL_PRESET_600_600_150 102
-#define QCA_PLL_PRESET_600_600_200 103
-#define QCA_PLL_PRESET_600_600_250 104
-#define QCA_PLL_PRESET_600_600_300 105
-#define QCA_PLL_PRESET_620_200_100 106
-#define QCA_PLL_PRESET_620_200_150 107
-#define QCA_PLL_PRESET_620_200_200 108
-#define QCA_PLL_PRESET_620_300_100 109
-#define QCA_PLL_PRESET_620_300_150 110
-#define QCA_PLL_PRESET_620_300_200 111
-#define QCA_PLL_PRESET_620_300_300 112
-#define QCA_PLL_PRESET_620_400_100 113
-#define QCA_PLL_PRESET_620_400_155 114
-#define QCA_PLL_PRESET_620_400_200 115
-#define QCA_PLL_PRESET_620_400_310 116
-#define QCA_PLL_PRESET_620_500_100 117
-#define QCA_PLL_PRESET_620_500_155 118
-#define QCA_PLL_PRESET_620_500_166 119
-#define QCA_PLL_PRESET_620_500_206 120
-#define QCA_PLL_PRESET_620_500_250 121
-#define QCA_PLL_PRESET_620_500_310 122
-#define QCA_PLL_PRESET_650_400_200 123
-#define QCA_PLL_PRESET_650_420_210 124
-#define QCA_PLL_PRESET_650_450_225 125
-
+#define QCA_PLL_PRESET_410_410_205 47
+#define QCA_PLL_PRESET_420_420_210 48
+#define QCA_PLL_PRESET_430_430_215 49
+#define QCA_PLL_PRESET_440_440_220 50
+#define QCA_PLL_PRESET_450_450_225 51
+#define QCA_PLL_PRESET_460_460_230 52
+#define QCA_PLL_PRESET_470_470_235 53
+#define QCA_PLL_PRESET_480_480_240 54
+#define QCA_PLL_PRESET_490_490_245 55
+#define QCA_PLL_PRESET_500_200_100 56
+#define QCA_PLL_PRESET_500_200_150 57
+#define QCA_PLL_PRESET_500_200_200 58
+#define QCA_PLL_PRESET_500_300_100 59
+#define QCA_PLL_PRESET_500_300_150 60
+#define QCA_PLL_PRESET_500_300_200 61
+#define QCA_PLL_PRESET_500_300_250 62
+#define QCA_PLL_PRESET_500_300_300 63
+#define QCA_PLL_PRESET_500_400_100 64
+#define QCA_PLL_PRESET_500_400_200 65
+#define QCA_PLL_PRESET_500_400_250 66
+#define QCA_PLL_PRESET_500_500_100 67
+#define QCA_PLL_PRESET_500_500_150 68
+#define QCA_PLL_PRESET_500_500_200 69
+#define QCA_PLL_PRESET_500_500_250 70
+#define QCA_PLL_PRESET_500_500_300 71
+#define QCA_PLL_PRESET_510_510_255 72
+#define QCA_PLL_PRESET_520_520_260 73
+#define QCA_PLL_PRESET_530_265_132 74
+#define QCA_PLL_PRESET_540_275_135 75
+#define QCA_PLL_PRESET_550_200_100 76
+#define QCA_PLL_PRESET_550_200_150 77
+#define QCA_PLL_PRESET_550_200_200 78
+#define QCA_PLL_PRESET_550_275_137 79
+#define QCA_PLL_PRESET_550_300_100 80
+#define QCA_PLL_PRESET_550_300_150 81
+#define QCA_PLL_PRESET_550_300_200 82
+#define QCA_PLL_PRESET_550_300_275 83
+#define QCA_PLL_PRESET_550_300_300 84
+#define QCA_PLL_PRESET_550_375_250 85
+#define QCA_PLL_PRESET_550_400_200 86
+#define QCA_PLL_PRESET_560_280_140 87
+#define QCA_PLL_PRESET_560_450_225 88
+#define QCA_PLL_PRESET_570_285_142 89
+#define QCA_PLL_PRESET_580_290_145 90
+#define QCA_PLL_PRESET_600_200_100 91
+#define QCA_PLL_PRESET_600_200_150 92
+#define QCA_PLL_PRESET_600_200_200 93
+#define QCA_PLL_PRESET_600_300_100 94
+#define QCA_PLL_PRESET_600_300_150 95
+#define QCA_PLL_PRESET_600_300_200 96
+#define QCA_PLL_PRESET_600_300_250 97
+#define QCA_PLL_PRESET_600_300_300 98
+#define QCA_PLL_PRESET_600_400_100 99
+#define QCA_PLL_PRESET_600_400_150 100
+#define QCA_PLL_PRESET_600_400_200 101
+#define QCA_PLL_PRESET_600_400_300 102
+#define QCA_PLL_PRESET_600_450_100 103
+#define QCA_PLL_PRESET_600_450_150 104
+#define QCA_PLL_PRESET_600_450_200 105
+#define QCA_PLL_PRESET_600_450_225 106
+#define QCA_PLL_PRESET_600_450_300 107
+#define QCA_PLL_PRESET_600_500_100 108
+#define QCA_PLL_PRESET_600_500_150 109
+#define QCA_PLL_PRESET_600_500_200 110
+#define QCA_PLL_PRESET_600_500_250 111
+#define QCA_PLL_PRESET_600_500_300 112
+#define QCA_PLL_PRESET_600_550_100 113
+#define QCA_PLL_PRESET_600_550_150 114
+#define QCA_PLL_PRESET_600_550_200 115
+#define QCA_PLL_PRESET_600_550_275 116
+#define QCA_PLL_PRESET_600_550_300 117
+#define QCA_PLL_PRESET_600_600_100 118
+#define QCA_PLL_PRESET_600_600_150 119
+#define QCA_PLL_PRESET_600_600_200 120
+#define QCA_PLL_PRESET_600_600_250 121
+#define QCA_PLL_PRESET_600_600_300 122
+#define QCA_PLL_PRESET_620_200_100 123
+#define QCA_PLL_PRESET_620_200_150 124
+#define QCA_PLL_PRESET_620_200_200 125
+#define QCA_PLL_PRESET_620_300_100 126
+#define QCA_PLL_PRESET_620_300_150 127
+#define QCA_PLL_PRESET_620_300_200 128
+#define QCA_PLL_PRESET_620_300_300 129
+#define QCA_PLL_PRESET_620_400_100 130
+#define QCA_PLL_PRESET_620_400_155 131
+#define QCA_PLL_PRESET_620_400_200 132
+#define QCA_PLL_PRESET_620_400_310 133
+#define QCA_PLL_PRESET_620_500_100 134
+#define QCA_PLL_PRESET_620_500_155 135
+#define QCA_PLL_PRESET_620_500_166 136
+#define QCA_PLL_PRESET_620_500_206 137
+#define QCA_PLL_PRESET_620_500_250 138
+#define QCA_PLL_PRESET_620_500_310 139
+#define QCA_PLL_PRESET_650_400_200 140
+#define QCA_PLL_PRESET_650_420_210 141
+#define QCA_PLL_PRESET_650_450_225 142
#endif /* _QCA_PLL_LIST_H_ */
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