config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
+ select ARCH_QEMU_E500
select PHYS_64BIT
config TARGET_T102XQDS
config ARCH_P5040
bool
+config ARCH_QEMU_E500
+ bool
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
obj-y += cpu_init.o
obj-y += cpu_init_early.o
obj-y += interrupts.o
-ifneq ($(CONFIG_QEMU_E500),y)
+ifneq ($(CONFIG_ARCH_QEMU_E500),y)
obj-y += speed.o
endif
obj-y += tlb.o
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
- defined(CONFIG_QEMU_E500)
+ defined(CONFIG_ARCH_QEMU_E500)
return fsl_ddr_sdram_size();
#else
return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
/* gd area was zeroed during startup */
-#ifdef CONFIG_QEMU_E500
+#ifdef CONFIG_ARCH_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
#endif
mtspr HID0,r0
-#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
+#if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
-#elif defined(CONFIG_QEMU_E500)
+#elif defined(CONFIG_ARCH_QEMU_E500)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_QEMU_E500
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
CONFIG_P_CLK_FREQ
CONFIG_QBMAN_CLK_DIV
CONFIG_QE
-CONFIG_QEMU_E500
CONFIG_QEMU_MIPS
CONFIG_QIXIS_I2C_ACCESS
CONFIG_QSPI