compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
- spi0 = &qspi;
+ spi0 = &snfi;
};
chosen {
};
&pinctrl {
- qspi_pins: qspi-pins {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
mux {
function = "flash";
groups = "spi_nor";
};
};
-&qspi {
- pinctrl-names = "default";
- pinctrl-0 = <&qspi_pins>;
+&snfi {
+ pinctrl-names = "default", "snfi";
+ pinctrl-0 = <&snor_pins>;
+ pinctrl-1 = <&snfi_pins>;
status = "okay";
spi-flash@0{
status = "disabled";
};
- qspi: qspi@11014000 {
- compatible = "mediatek,mt7629-qspi";
- reg = <0x11014000 0xe0>, <0x30000000 0x10000000>;
- reg-names = "reg_base", "mem_base";
+ snfi: snfi@1100d000 {
+ compatible = "mediatek,mtk-snfi-spi";
+ reg = <0x1100d000 0x2000>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;