riscv: sifive: dts: fu540: Add board -u-boot.dtsi files

Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.

So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index db55773bd238163c64d50e4d6e53f50b9ab61a51..fbfe296a03287febf0d65285f4ca29d317d552e2 100644 (file)
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -4,11 +4,72 @@
  */
 
 / {
+       cpus {
+               assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+               assigned-clock-rates = <1000000000>;
+               u-boot,dm-spl;
+               cpu0: cpu@0 {
+                       clocks = <&prci PRCI_CLK_COREPLL>;
+                       u-boot,dm-spl;
+                       status = "okay";
+                       cpu0_intc: interrupt-controller {
+                               u-boot,dm-spl;
+                       };
+               };
+               cpu1: cpu@1 {
+                       clocks = <&prci PRCI_CLK_COREPLL>;
+                       u-boot,dm-spl;
+                       cpu1_intc: interrupt-controller {
+                               u-boot,dm-spl;
+                       };
+               };
+               cpu2: cpu@2 {
+                       clocks = <&prci PRCI_CLK_COREPLL>;
+                       u-boot,dm-spl;
+                       cpu2_intc: interrupt-controller {
+                                u-boot,dm-spl;
+                       };
+               };
+               cpu3: cpu@3 {
+                       clocks = <&prci PRCI_CLK_COREPLL>;
+                       u-boot,dm-spl;
+                       cpu3_intc: interrupt-controller {
+                               u-boot,dm-spl;
+                       };
+               };
+               cpu4: cpu@4 {
+                       clocks = <&prci PRCI_CLK_COREPLL>;
+                       u-boot,dm-spl;
+                       cpu4_intc: interrupt-controller {
+                               u-boot,dm-spl;
+                       };
+               };
+       };
+
        soc {
+               u-boot,dm-spl;
                otp: otp@10070000 {
                        compatible = "sifive,fu540-c000-otp";
                        reg = <0x0 0x10070000 0x0 0x0FFF>;
                        fuse-count = <0x1000>;
                };
+               clint@2000000 {
+                       compatible = "riscv,clint0";
+                       interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
+                       reg = <0x0 0x2000000 0x0 0xc0000>;
+                       u-boot,dm-spl;
+               };
        };
 };
+
+&prci {
+       u-boot,dm-spl;
+};
+
+&uart0 {
+       u-boot,dm-spl;
+};
+
+&qspi2 {
+       u-boot,dm-spl;
+};

diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 9af089ffe712535812c540ef994f49a37aac7c4d..9787332bf1a2c89d2857d00c459e79af98f7c858 100644 (file)
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -10,4 +10,19 @@
                spi0 = &qspi0;
                spi2 = &qspi2;
        };
+
+       hfclk {
+               u-boot,dm-spl;
+       };
+
+       rtcclk {
+               u-boot,dm-spl;
+       };
+
+};
+
+&qspi2 {
+       mmc@0 {
+               u-boot,dm-spl;
+       };
 };