x86: Make cpu init functions weak

diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c
index e96380aa926e582bdd914e8134f0e89ddc1f1202..2339cd41bbe71d037bc7900dd1222b83b8194528 100644 (file)
--- a/arch/i386/cpu/cpu.c
+++ b/arch/i386/cpu/cpu.c
@@ -87,7 +87,7 @@ static void reload_gdt(void)
 }
 
 
-int cpu_init_f(void)
+int x86_cpu_init_f(void)
 {
        const u32 em_rst = ~X86_CR0_EM;
        const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
@@ -102,15 +102,25 @@ int cpu_init_f(void)
 
        return 0;
 }
+int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
 
-int cpu_init_r(void)
+int x86_cpu_init_r(void)
 {
+       const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
+       /* turn on the cache and disable write through */
+       asm("movl       %%cr0, %%eax\n"
+           "andl       %0, %%eax\n"
+           "movl       %%eax, %%cr0\n"
+           "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+
        reload_gdt();
 
        /* Initialize core interrupt and exception functionality of CPU */
        cpu_init_interrupts ();
        return 0;
 }
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {

diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 21037d29d761e8a63045b85e8f63f09b6def735d..b99408cc999ce9eb0e072770122abf4e0d3a9fad 100644 (file)
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ * Daniel Engstr�m, Omicron Ceti AB <daniel@omicron.se>.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -40,10 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
 
-void init_sc520(void)
+int cpu_init_f(void)
 {
-       const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
-
        /*
         * Set the UARTxCTL register at it's slower,
         * baud clock giving us a 1.8432 MHz reference
@@ -85,10 +83,7 @@ void init_sc520(void)
        /* turn on the SDRAM write buffer */
        writeb(0x11, &sc520_mmcr->dbctl);
 
-       /* turn on the cache and disable write through */
-       asm("movl       %%cr0, %%eax\n"
-           "andl       %0, %%eax\n"
-           "movl       %%eax, %%cr0\n"  : : "i" (nw_cd_rst) : "eax");
+       return x86_cpu_init_f();
 }
 
 unsigned long init_sc520_dram(void)

diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h
index ce097a3bfa6845f3a3916bc1f41cac71a66ae859..80db52fc6f9393af64fd35ab10d17c7650669444 100644 (file)
--- a/arch/i386/include/asm/u-boot-i386.h
+++ b/arch/i386/include/asm/u-boot-i386.h
@@ -25,7 +25,9 @@
 #define _U_BOOT_I386_H_        1
 
 /* cpu/.../cpu.c */
+int x86_cpu_init_r(void);
 int cpu_init_r(void);
+int x86_cpu_init_f(void);
 int cpu_init_f(void);
 
 /* cpu/.../timer.c */

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 7f0e2577f1bf1d4537cddb0cdd39c8cef17b21e3..30d8750d7616209b7a0c502850637a24de6abb75 100644 (file)
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -48,33 +48,11 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
 static void enet_timer_isr(void);
 static void enet_toggle_run_led(void);
 
-void init_sc520_enet (void)
-{
-       /* Set CPU Speed to 100MHz */
-       writeb(0x01, &sc520_mmcr->cpuctl);
-
-       /* wait at least one millisecond */
-       asm("movl       $0x2000,%%ecx\n"
-           "0: pushl %%ecx\n"
-           "popl       %%ecx\n"
-           "loop 0b\n": : : "ecx");
-
-       /* turn on the SDRAM write buffer */
-       writeb(0x11, &sc520_mmcr->dbctl);
-
-       /* turn on the cache and disable write through */
-       asm("movl       %%cr0, %%eax\n"
-           "andl       $0x9fffffff, %%eax\n"
-           "movl       %%eax, %%cr0\n"  : : : "eax");
-}
-
 /*
  * Miscellaneous platform dependent initializations
  */
 int board_early_init_f(void)
 {
-       init_sc520_enet();
-
        writeb(0x01, &sc520_mmcr->gpcsrt);              /* GP Chip Select Recovery Time */
        writeb(0x07, &sc520_mmcr->gpcspw);              /* GP Chip Select Pulse Width */
        writeb(0x00, &sc520_mmcr->gpcsoff);             /* GP Chip Select Offset */