Cache update and added CFG_UNIFY_CACHE

Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only.

Signed-off-by: TsiChung <tcliew@Goku.(none)>

diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c
index b056fbe310f255e3931a9278b3d53180dbe96236..32711a17443cd4aa2072c0cabc5e5d80ae691ba9 100644 (file)
--- a/cpu/mcf532x/cpu_init.c
+++ b/cpu/mcf532x/cpu_init.c
@@ -113,6 +113,8 @@ void cpu_init_f(void)
        fbcs->cscr5 = CFG_CS5_CTRL;
        fbcs->csmr5 = CFG_CS5_MASK;
 #endif
+
+       icache_enable();
 }
 
 /*
@@ -120,6 +122,5 @@ void cpu_init_f(void)
  */
 int cpu_init_r(void)
 {
-       icache_enable();
        return (0);
 }

diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index acd34941a9b8333205c6ec42204829322fc714ac..ac44aaabec77d04b0fc9b8a0c90d81756710ef4d 100644 (file)
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -270,8 +270,6 @@ icache_enable:
        movec   %d0, %CACR                      /* Invalidate cache */
        move.l  #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
        movec   %d0, %ACR0                      /* Enable cache */
-       move.l  #(CFG_CS0_BASE + 0x0000), %d0   /* Setup cache mask */
-       movec   %d0, %ACR1                      /* Enable cache */
 
        move.l  #0x80000200, %d0                /* Setup cache mask */
        movec   %d0, %CACR                      /* Enable cache */
@@ -284,11 +282,11 @@ icache_enable:
 
        .globl  icache_disable
 icache_disable:
-       move.l  #0x00000100, %d0                /* Setup cache mask */
-       movec   %d0, %CACR                      /* Enable cache */
+       move.l  #0x01000000, %d0                /* Setup cache mask */
+       movec   %d0, %CACR                      /* Disable cache */
        clr.l   %d0                             /* Setup cache mask */
-       movec   %d0, %ACR0                      /* Enable cache */
-       movec   %d0, %ACR1                      /* Enable cache */
+       movec   %d0, %ACR0
+       movec   %d0, %ACR1
 
        move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
        moveq   #0, %d0
@@ -303,7 +301,7 @@ icache_status:
 
        .globl  icache_invalid
 icache_invalid:
-       move.l  #0x01000000, %d0                /* Setup cache mask */
+       move.l  #0x81000200, %d0                /* Setup cache mask */
        movec   %d0, %CACR                      /* Enable cache */
        rts
 

diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 609210de19e0cea738df8846825a766b34c05a57..11f67218972dc3d3b075b6159765a822f32adf0a 100644 (file)
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -150,23 +150,15 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
         * Wait for ready
         */
        j = 0;
-#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
-       icache_invalid();
-#endif
        while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
               (j < MCFFEC_TOUT_LOOP)) {
                udelay(1);
                j++;
-#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
-               icache_invalid();
-#endif
        }
        if (j >= MCFFEC_TOUT_LOOP) {
                printf("TX not ready\n");
        }
-#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
-       icache_invalid();
-#endif
+
        info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
        info->txbd[info->txIdx].cbd_datlen = length;
        info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
@@ -174,21 +166,19 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
        /* Activate transmit Buffer Descriptor polling */
        fecp->tdar = 0x01000000;        /* Descriptor polling active    */
 
-       j = 0;
-#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
+#ifdef CFG_UNIFY_CACHE
        icache_invalid();
 #endif
+       j = 0;
        while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
               (j < MCFFEC_TOUT_LOOP)) {
                udelay(1);
                j++;
-#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
-               icache_invalid();
-#endif
        }
        if (j >= MCFFEC_TOUT_LOOP) {
                printf("TX timeout\n");
        }
+
 #ifdef ET_DEBUG
        printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
               __FILE__, __LINE__, __FUNCTION__, j,
@@ -196,10 +186,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
               (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
 #endif
 
-       /* return only status bits */ ;
-#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
-       icache_invalid();
-#endif
+       /* return only status bits */
        rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
        info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
 
@@ -213,6 +200,9 @@ int fec_recv(struct eth_device *dev)
        int length;
 
        for (;;) {
+#ifdef CFG_UNIFY_CACHE
+                       icache_invalid();
+#endif
                /* section 16.9.23.2 */
                if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
                        length = -1;

diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index c90773c501185a8d458caf999b7f0e09de6e8b6a..d1ac340048124b5020d0c4e1166ebc406357d6ab 100644 (file)
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -47,18 +47,20 @@
 #define CONFIG_WATCHDOG_TIMEOUT        5000    /* timeout in milliseconds, max timeout is 6.71sec */
 
 #define CONFIG_COMMANDS                ( CONFIG_CMD_DFL | \
-                                                         CFG_CMD_CACHE | \
-                                                         CFG_CMD_DATE | \
-                                                         CFG_CMD_ELF | \
-                                                         CFG_CMD_FLASH | \
-                                                         (CFG_CMD_LOADB | CFG_CMD_LOADS) | \
-                                                         CFG_CMD_MEMORY | \
-                                                         CFG_CMD_MISC | \
-                                                         CFG_CMD_MII | \
-                                                         CFG_CMD_NET | \
-                                                         CFG_CMD_PING | \
-                                                         CFG_CMD_REGINFO \
-                                                       )
+                                 CFG_CMD_CACHE | \
+                                 CFG_CMD_DATE | \
+                                 CFG_CMD_ELF | \
+                                 CFG_CMD_FLASH | \
+                                 (CFG_CMD_LOADB | CFG_CMD_LOADS) | \
+                                 CFG_CMD_MEMORY | \
+                                 CFG_CMD_MISC | \
+                                 CFG_CMD_MII | \
+                                 CFG_CMD_NET | \
+                                 CFG_CMD_PING | \
+                                 CFG_CMD_REGINFO \
+                               )
+
+#define CFG_UNIFY_CACHE
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC