qong: support for Dave/DENX QongEVB-LITE board
authorIlya Yanok <yanok@emcraft.com>
Mon, 9 Feb 2009 23:22:31 +0000 (00:22 +0100)
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Mon, 9 Feb 2009 23:22:31 +0000 (00:22 +0100)
This patch adds support for Dave/DENX QongEVB-LITE i.MX31-based board.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
MAINTAINERS
MAKEALL
Makefile
board/davedenx/qong/Makefile [new file with mode: 0644]
board/davedenx/qong/config.mk [new file with mode: 0644]
board/davedenx/qong/lowlevel_init.S [new file with mode: 0644]
board/davedenx/qong/qong.c [new file with mode: 0644]
board/davedenx/qong/qong_fpga.h [new file with mode: 0644]
board/davedenx/qong/u-boot.lds [new file with mode: 0644]
include/configs/qong.h [new file with mode: 0644]

index 38feac8fe3b33c693c6921e4e0d1255736983994..c3157d95b6d0ddb7608ca302c740275d43c07e47 100644 (file)
@@ -655,6 +655,9 @@ Sergey Lapin <slapin@ossfans.org>
 
        afeb9260        ARM926EJS (AT91SAM9260 SoC)
 
+Wolfgang Denk <wd@denx.de>
+       qong            i.MX31
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
diff --git a/MAKEALL b/MAKEALL
index cf05133d197c7c76be224d045ceaaa61450c1c6b..73974f7369cf4af8d3cdb3c1a20b9ba308179236 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -542,6 +542,7 @@ LIST_ARM11="                \
        imx31_litekit   \
        imx31_phycore   \
        mx31ads         \
+       qong            \
        smdk6400        \
 "
 
index 787c5f24bced341a2eff1189c90acab4c2802bab..7508e1dc93fc7790b04394e3fe3b4a32c1e0cad1 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3034,6 +3034,10 @@ mx31ads_config           : unconfig
 omap2420h4_config      : unconfig
        @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
 
+qong_config            : unconfig
+       @$(MKCONFIG) $(@:_config=) arm arm1136 qong davedenx mx31
+
+
 #########################################################################
 ## ARM1176 Systems
 #########################################################################
diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile
new file mode 100644 (file)
index 0000000..93e1985
--- /dev/null
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2009
+# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := qong.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/davedenx/qong/config.mk b/board/davedenx/qong/config.mk
new file mode 100644 (file)
index 0000000..d8d0a57
--- /dev/null
@@ -0,0 +1 @@
+TEXT_BASE = 0x8ff00000
diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S
new file mode 100644 (file)
index 0000000..198dd76
--- /dev/null
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * Based on board/freescale/mx31ads/lowlevel_init.S
+ * by Guennadi Liakhovetski.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+       ldr r2, =\reg
+       ldr r3, =\val
+       str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+       ldr r2, =\reg
+       ldr r3, =\val
+       strb r3, [r2]
+.endm
+
+.macro DELAY loops
+       ldr r2, =\loops
+1:
+       subs    r2, r2, #1
+       nop
+       bcs 1b
+.endm
+
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+       /*
+        * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+        * in SW_PAD_CTL registers
+        */
+
+       /* SDCLK */
+       ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
+       ldr r0, [r1, #0x6C]
+       bic r0, r0, #(1 << 12)
+       str r0, [r1, #0x6C]
+
+       /* CAS */
+       ldr r0, [r1, #0x70]
+       bic r0, r0, #(1 << 22)
+       str r0, [r1, #0x70]
+
+       /* RAS */
+       ldr r0, [r1, #0x74]
+       bic r0, r0, #(1 << 2)
+       str r0, [r1, #0x74]
+
+       /* CS2 (CSD0) */
+       ldr r0, [r1, #0x7C]
+       bic r0, r0, #(1 << 22)
+       str r0, [r1, #0x7C]
+
+       /* DQM3 */
+       ldr r0, [r1, #0x84]
+       bic r0, r0, #(1 << 22)
+       str r0, [r1, #0x84]
+
+       /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+       ldr r2, =22     /* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+       ldr r0, [r1, #0x88]
+       bic r0, r0, #(1 << 22)
+       bic r0, r0, #(1 << 12)
+       bic r0, r0, #(1 << 2)
+       str r0, [r1, #0x88]
+       add r1, r1, #4
+       subs r2, r2, #0x1
+       bne pad_loop
+.endm /* init_drive_strength */
+
+.globl lowlevel_init
+lowlevel_init:
+
+       init_drive_strength
+
+       /* Image Processing Unit: */
+       /* Too early to switch display on? */
+       /* Switch on Display Interface */
+       REG     IPU_CONF, IPU_CONF_DI_EN
+       /* Clock Control Module: */
+       REG     CCM_CCMR, 0x074B0BF5            /* Use CKIH, MCU PLL off */
+
+       DELAY 0x40000
+
+       REG     CCM_CCMR, 0x074B0BF5 | CCMR_MPE                 /* MCU PLL on */
+       /* Switch to MCU PLL */
+       REG     CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+       /* 399-133-66.5 */
+       ldr     r0, =CCM_BASE
+       ldr     r1, =0xFF871650
+       /* PDR0 */
+       str     r1, [r0, #0x4]
+       ldr     r1, MPCTL_PARAM_399
+       /* MPCTL */
+       str     r1, [r0, #0x10]
+
+       /* Set UPLL=240MHz, USB=60MHz */
+       ldr     r1, =0x49FCFE7F
+       /* PDR1 */
+       str     r1, [r0, #0x8]
+       ldr     r1, UPCTL_PARAM_240
+       /* UPCTL */
+       str     r1, [r0, #0x14]
+       /* default CLKO to 1/8 of the ARM core */
+       mov     r1, #0x00000208
+       /* COSR */
+       str     r1, [r0, #0x1c]
+
+       /* Default: 1, 4, 12, 1 */
+       REG     CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+       /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+       REG     0xB8001010, 0x00000004
+       REG     0xB8001004, ((3 << 21) | /* tXP */      \
+                            (0 << 20) | /* tWTR */     \
+                            (2 << 18) | /* tRP */      \
+                            (1 << 16) | /* tMRD */     \
+                            (0 << 15) | /* tWR */      \
+                            (5 << 12) | /* tRAS */     \
+                            (1 << 10) | /* tRRD */     \
+                            (3 << 8)  | /* tCAS */     \
+                            (2 << 4)  | /* tRCD */     \
+                            (7 << 0)    /* tRC */ )
+       REG     0xB8001000, 0x92100000
+       REG     0x80000f00, 0x12344321
+       REG     0xB8001000, 0xa2100000
+       REG     0x80000000, 0x12344321
+       REG     0x80000000, 0x12344321
+       REG     0xB8001000, 0xb2100000
+       REG8    0x80000033, 0xda
+       REG8    0x81000000, 0xff
+       REG     0xB8001000, ((1 << 31) |                                \
+                            (0 << 28) |                                \
+                            (0 << 27) |                                \
+                            (3 << 24) | /* 14 rows */                  \
+                            (2 << 20) | /* 10 cols */                  \
+                            (2 << 16) |                                \
+                            (4 << 13) | /* 3.91us (64ms/16384) */      \
+                            (0 << 10) |                                \
+                            (0 << 8)  |                                \
+                            (1 << 7)  |                                \
+                            (0 << 0))
+       REG     0x80000000, 0xDEADBEEF
+       REG     0xB8001010, 0x0000000c
+
+       mov     pc, lr
+
+MPCTL_PARAM_399:
+       .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
+UPCTL_PARAM_240:
+       .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3  << 0))
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
new file mode 100644 (file)
index 0000000..13b3699
--- /dev/null
@@ -0,0 +1,168 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+                       PHYS_SDRAM_1_SIZE);
+
+       return 0;
+}
+
+int board_init (void)
+{
+       /* Chip selects */
+       /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
+       /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
+       __REG(CSCR_U(0)) = ((0 << 31)   | /* SP */
+                                               (0 << 30)       | /* WP */
+                                               (0 << 28)       | /* BCD */
+                                               (0 << 24)       | /* BCS */
+                                               (0 << 22)       | /* PSZ */
+                                               (0 << 21)       | /* PME */
+                                               (0 << 20)       | /* SYNC */
+                                               (0 << 16)       | /* DOL */
+                                               (3 << 14)       | /* CNC */
+                                               (21 << 8)       | /* WSC */
+                                               (0 << 7)        | /* EW */
+                                               (0 << 4)        | /* WWS */
+                                               (6 << 0)          /* EDC */
+                                          );
+
+       __REG(CSCR_L(0)) = ((2 << 28)   | /* OEA */
+                                               (1 << 24)       | /* OEN */
+                                               (3 << 20)       | /* EBWA */
+                                               (3 << 16)       | /* EBWN */
+                                               (1 << 12)       | /* CSA */
+                                               (1 << 11)       | /* EBC */
+                                               (5 << 8)        | /* DSZ */
+                                               (1 << 4)        | /* CSN */
+                                               (0 << 3)        | /* PSR */
+                                               (0 << 2)        | /* CRE */
+                                               (0 << 1)        | /* WRAP */
+                                               (1 << 0)          /* CSEN */
+                                          );
+
+       __REG(CSCR_A(0)) = ((2 << 28)   | /* EBRA */
+                                               (1 << 24)       | /* EBRN */
+                                               (2 << 20)       | /* RWA */
+                                               (2 << 16)       | /* RWN */
+                                               (0 << 15)       | /* MUM */
+                                               (0 << 13)       | /* LAH */
+                                               (2 << 10)       | /* LBN */
+                                               (0 << 8)        | /* LBA */
+                                               (0 << 6)        | /* DWW */
+                                               (0 << 4)        | /* DCT */
+                                               (0 << 3)        | /* WWU */
+                                               (0 << 2)        | /* AGE */
+                                               (0 << 1)        | /* CNC2 */
+                                               (0 << 0)          /* FCE */
+                                          );
+
+#ifdef CONFIG_QONG_FPGA
+       /* CS1: FPGA/Network Controller/GPIO */
+       /* 16-bit, no DTACK */
+       __REG(CSCR_U(1)) = 0x00000A01;
+       __REG(CSCR_L(1)) = 0x20040501;
+       __REG(CSCR_A(1)) = 0x04020C00;
+
+       /* setup pins for FPGA */
+       mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
+       mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
+       mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
+       mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
+       mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
+#endif
+
+       /* setup pins for UART1 */
+       mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+       mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+       mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+       mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+       /* board id for linux */
+       gd->bd->bi_arch_number = MACH_TYPE_QONG;
+       gd->bd->bi_boot_params = (0x80000100);  /* adress of boot parameters */
+
+       return 0;
+}
+
+int checkboard (void)
+{
+       printf("Board: DAVE/DENX QongEVB-LITE\n");
+       return 0;
+}
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_QONG_FPGA
+       u32 tmp;
+
+       /* FPGA reset */
+       /* rstn = 0 */
+       tmp = __REG(GPIO2_BASE + GPIO_DR);
+       tmp &= (~(1 << QONG_FPGA_RST_PIN));
+       __REG(GPIO2_BASE + GPIO_DR) = tmp;
+       /* set the GPIO as output */
+       tmp = __REG(GPIO2_BASE + GPIO_GDIR);
+       tmp |= (1 << QONG_FPGA_RST_PIN);
+       __REG(GPIO2_BASE + GPIO_GDIR) = tmp;
+       /* wait */
+       udelay(30);
+       /* rstn = 1 */
+       tmp = __REG(GPIO2_BASE + GPIO_DR);
+       tmp |= (1 << QONG_FPGA_RST_PIN);
+       __REG(GPIO2_BASE + GPIO_DR) = tmp;
+       /* set interrupt pin as input */
+       __REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN);
+       /* wait while the FPGA starts */
+       udelay(300);
+
+       tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
+       printf("FPGA:  ");
+       printf("version register = %u.%u.%u\n",
+               (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
+#endif
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
+       return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
+#else
+       return 0;
+#endif
+}
+
diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h
new file mode 100644 (file)
index 0000000..b1cb08a
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef QONG_FPGA_H
+#define QONG_FPGA_H
+
+#ifdef CONFIG_QONG_FPGA
+#define QONG_FPGA_CTRL_BASE            CONFIG_FPGA_BASE
+#define QONG_FPGA_CTRL_VERSION         (QONG_FPGA_CTRL_BASE + 0x00000000)
+#define QONG_FPGA_PERIPH_SIZE          (1 << 24)
+
+#define        QONG_FPGA_TCK_PIN               26
+#define        QONG_FPGA_TMS_PIN               25
+#define        QONG_FPGA_TDI_PIN               8
+#define        QONG_FPGA_TDO_PIN               7
+#define        QONG_FPGA_RST_PIN               16
+#define        QONG_FPGA_IRQ_PIN               8
+#endif
+
+#endif /* QONG_FPGA_H */
+
diff --git a/board/davedenx/qong/u-boot.lds b/board/davedenx/qong/u-boot.lds
new file mode 100644 (file)
index 0000000..04e0642
--- /dev/null
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text :
+       {
+               cpu/arm1136/start.o     (.text)
+               *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data : { *(.data) }
+
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}
diff --git a/include/configs/qong.h b/include/configs/qong.h
new file mode 100644 (file)
index 0000000..fc6e33a
--- /dev/null
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
+ *
+ * Configuration settings for the Dave/DENX QongEVB-LITE board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136         1       /* This is an arm1136 CPU core */
+#define CONFIG_MX31            1       /* in a mx31 */
+#define CONFIG_QONG            1
+#define CONFIG_MX31_HCLK_FREQ  26000000        /* 26MHz */
+#define CONFIG_MX31_CLK32      32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS       1
+#define CONFIG_INITRD_TAG              1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE       128
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART       1
+#define CONFIG_SYS_MX31_UART1  1
+
+/* FPGA */
+#define CONFIG_QONG_FPGA       1
+#define CONFIG_FPGA_BASE       (CS1_BASE)
+
+#ifdef CONFIG_QONG_FPGA
+/* Ethernet */
+#define CONFIG_DNET            1
+#define CONFIG_DNET_BASE       (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
+#define CONFIG_NET_MULTI       1
+
+/*
+ * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
+ * initial TFTP transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT     200UL
+
+#endif /* CONFIG_QONG_FPGA */
+
+#define CONFIG_CONS_INDEX      1
+#define CONFIG_BAUDRATE                115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+
+/*
+ * You can compile in a MAC address and your custom net settings by using
+ * the following syntax.
+ *
+ * #define CONFIG_ETHADDR              xx:xx:xx:xx:xx:xx
+ * #define CONFIG_SERVERIP             <server ip>
+ * #define CONFIG_IPADDR               <board ip>
+ * #define CONFIG_GATEWAYIP            <gateway ip>
+ * #define CONFIG_NETMASK              <your netmask>
+ */
+
+#define CONFIG_BOOTDELAY       5
+
+#define CONFIG_LOADADDR                0x80800000      /* loadaddr env var */
+
+#define xstr(s)        str(s)
+#define str(s) #s
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "netdev=eth0\0"                                                 \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
+       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+       "addip=setenv bootargs ${bootargs} "                            \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
+       "addtty=setenv bootargs ${bootargs}"                            \
+               " console=ttymxc0,${baudrate}\0"                        \
+       "addmisc=setenv bootargs ${bootargs}\0"                         \
+       "uboot_addr=a0000000\0"                                         \
+       "kernel_addr=a0080000\0"                                        \
+       "ramdisk_addr=a0300000\0"                                       \
+       "uboot=qong/u-boot.bin\0"                                       \
+       "kernel_addr_r=80800000\0"                                      \
+       "hostname=qong\0"                                               \
+       "bootfile=qong/uImage\0"                                        \
+       "rootpath=/opt/eldk-4.2-arm/armVFP\0"                           \
+       "flash_self=run ramargs addip addtty addmisc;"                  \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "flash_nfs=run nfsargs addip addtty addmisc;"                   \
+               "bootm ${kernel_addr}\0"                                \
+       "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
+               "run nfsargs addip addtty addmisc;"                     \
+               "bootm\0"                                               \
+       "load=tftp ${loadaddr} ${uboot}\0"                              \
+       "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)             \
+               " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)      \
+               " +${filesize};cp.b ${fileaddr} "                       \
+               xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize};"           \
+               "setenv filesize;saveenv\0"                             \
+       "upd=run load update\0"                                         \
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP            /* undef to save memory */
+#define CONFIG_SYS_PROMPT              "=> "
+#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+               sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             32      /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+
+/* memtest works on first 255MB of RAM */
+#define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END         (PHYS_SDRAM_1 + 0xff000000)
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ                  1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_MISC_INIT_R     1
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE       (128 * 1024)    /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS   1
+#define PHYS_SDRAM_1           CSD0_BASE
+#define PHYS_SDRAM_1_SIZE      0x10000000      /* 256 MB */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE          CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT      1024
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN         0x40000         /* Reserve 256KiB */
+
+#define        CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_SECT_SIZE   0x20000
+#define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE + 0x40000)
+
+/* Address and size of Redundant Environment Sector    */
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI                   1
+/* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER                        1
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE      1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION            1
+
+/*
+ * JFFS2 partitions
+ */
+#define CONFIG_JFFS2_CMDLINE
+
+#endif /* __CONFIG_H */