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spi: cadence_qspi: Better debug information on the SPI clock rate
author
Phil Edworthy
<PHIL.EDWORTHY@renesas.com>
Tue, 29 Nov 2016 12:58:28 +0000
(12:58 +0000)
committer
Jagan Teki
<jagan@amarulasolutions.com>
Thu, 15 Dec 2016 15:57:27 +0000
(16:57 +0100)
Show what the output clock rate actually is.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
drivers/spi/cadence_qspi_apb.c
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diff --git
a/drivers/spi/cadence_qspi_apb.c
b/drivers/spi/cadence_qspi_apb.c
index b5c664fe3608c1ff650875dfc9cf86112c6fd9e2..0a2963de3561efed9ed12c62b0b78d96fa4e4471 100644
(file)
--- a/
drivers/spi/cadence_qspi_apb.c
+++ b/
drivers/spi/cadence_qspi_apb.c
@@
-280,13
+280,13
@@
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
*/
div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
- debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
- ref_clk_hz, sclk_hz, div);
-
/* ensure the baud rate doesn't exceed the max value */
if (div > CQSPI_REG_CONFIG_BAUD_MASK)
div = CQSPI_REG_CONFIG_BAUD_MASK;
+ debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
+ ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
+
reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
writel(reg, reg_base + CQSPI_REG_CONFIG);