powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb

Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash
boot loaders because:
- P1_P2_RDB boards have soldered DDR so no need for SPD
- Also P102x has 256K L2 cache size so becomes a limiting factor for
  size of image that could be loaded in SRAM mode and would require three
  stage boot loader (TPL).

Changes done:
 1. CONFIG_SYS_TEXT_BASE to 0x11000000
 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 44faec3a0be8d718ea733f4cce918e8bff3fc8b5..853044e1cfa70f3eef7f01be8c78efd0aed02e1b 100644 (file)
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -202,6 +202,17 @@ phys_size_t fixed_sdram (void)
        struct cpu_type *cpu;
        ulong ddr_freq, ddr_freq_mhz;
 
+       cpu = gd->cpu;
+       /* P1020 and it's derivatives support max 32bit DDR width */
+       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
+               cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+               ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
+       } else {
+               ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+       }
+#if defined(CONFIG_SYS_RAMBOOT)
+       return ddr_size;
+#endif
        ddr_freq = get_ddr_freq(0);
        ddr_freq_mhz = ddr_freq / 1000000;
 
@@ -220,16 +231,12 @@ phys_size_t fixed_sdram (void)
                panic("Unsupported DDR data rate %s MT/s data rate\n",
                                        strmhz(buf, ddr_freq));
 
-       cpu = gd->cpu;
        /* P1020 and it's derivatives support max 32bit DDR width */
        if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
                cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
                ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
                ddr_cfg_regs.cs[0].bnds = 0x0000001F;
-               ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
        }
-       else
-               ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
        fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
 

diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index a46b1b5670a83f0697ddf1f788b173074b08fd94..9b166b2151c57e8bf190d153ca032dd0d54371a5 100644 (file)
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -80,15 +80,10 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 6, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
-       /* *I*G - L2SRAM */
-       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 7, BOOKE_PAGESZ_256K, 1),
-       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-                       CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 8, BOOKE_PAGESZ_256K, 1),
+#if defined(CONFIG_SYS_RAMBOOT)
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 7, BOOKE_PAGESZ_1G, 1)
 #endif
 };
 

diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index a217bcd08c631d2e8f8e01adedd4d478cf22f2bd..53ec56f211e128c3d1b61391c37a6368a212757d 100644 (file)
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -57,14 +57,14 @@
 
 #ifdef CONFIG_SDCARD
 #define CONFIG_RAMBOOT_SDCARD          1
-#define CONFIG_SYS_TEXT_BASE           0xf8f80000
-#define CONFIG_RESET_VECTOR_ADDRESS    0xf8fffffc
+#define CONFIG_SYS_TEXT_BASE           0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS    0x1107fffc
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH                1
-#define CONFIG_SYS_TEXT_BASE           0xf8f80000
-#define CONFIG_RESET_VECTOR_ADDRESS    0xf8fffffc
+#define CONFIG_SYS_TEXT_BASE           0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS    0x1107fffc
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE