choice
prompt "Target select"
- default TARGET_AXS10X
+ default TARGET_AXS103
config TARGET_TB100
bool "Support tb100"
config TARGET_NSIM
bool "Support standalone nSIM & Free nSIM"
-config TARGET_AXS10X
- bool "Support Synopsys Designware SDP board (AXS101 & AXS103)"
+config TARGET_AXS101
+ bool "Support Synopsys Designware SDP board AXS101"
+
+config TARGET_AXS103
+ bool "Support Synopsys Designware SDP board AXS103"
endchoice
# SPDX-License-Identifier: GPL-2.0+
#
-dtb-$(CONFIG_TARGET_AXS10X) += axs10x.dtb
+dtb-$(CONFIG_TARGET_AXS101) += axs101.dtb
+dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb
dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
#include "skeleton.dtsi"
/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
aliases {
console = &uart0;
};
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
uart0: serial@ff100000 {
compatible = "snps,dw-apb-uart";
reg = <0xff100000 0x1000>;
--- /dev/null
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <750000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
--- /dev/null
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
--- /dev/null
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+
+/include/ "axc001.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
--- /dev/null
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+
+/include/ "axc003.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+++ /dev/null
-/*
- * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/dts-v1/;
-
-#include "skeleton.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- console = &uart0;
- };
-
- clocks {
- apbclk: apbclk {
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- #clock-cells = <0>;
- };
- };
-
- uart0: serial0@e0022000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xe0022000 0x1000>;
- reg-shift = <2>;
- reg-io-width = <4>;
- };
-
- ethernet@e0018000 {
- #interrupt-cells = <1>;
- compatible = "altr,socfpga-stmmac";
- reg = < 0xe0018000 0x2000 >;
- interrupts = < 25 >;
- interrupt-names = "macirq";
- phy-mode = "gmii";
- snps,pbl = < 32 >;
- clocks = <&apbclk>;
- clock-names = "stmmaceth";
- max-speed = <100>;
- };
-
- ehci@0xe0040000 {
- compatible = "generic-ehci";
- reg = < 0xe0040000 0x100 >;
- interrupts = < 8 >;
- };
-
- ohci@0xe0060000 {
- compatible = "generic-ohci";
- reg = < 0xe0060000 0x100 >;
- interrupts = < 8 >;
- };
-};
--- /dev/null
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ axs10x_mb@e0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0xe0000000 0x10000000>;
+ u-boot,dm-pre-reloc;
+
+ clocks {
+ compatible = "simple-bus";
+ u-boot,dm-pre-reloc;
+
+ apbclk: apbclk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
+ uartclk: uartclk {
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ethernet@18000 {
+ #interrupt-cells = <1>;
+ compatible = "altr,socfpga-stmmac";
+ reg = < 0x18000 0x2000 >;
+ interrupts = < 25 >;
+ interrupt-names = "macirq";
+ phy-mode = "gmii";
+ snps,pbl = < 32 >;
+ clocks = <&apbclk>;
+ clock-names = "stmmaceth";
+ max-speed = <100>;
+ };
+
+ ehci@0x40000 {
+ compatible = "generic-ehci";
+ reg = < 0x40000 0x100 >;
+ interrupts = < 8 >;
+ };
+
+ ohci@0x60000 {
+ compatible = "generic-ohci";
+ reg = < 0x60000 0x100 >;
+ interrupts = < 8 >;
+ };
+
+ uart0: serial0@22000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x22000 0x100>;
+ clocks = <&uartclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+ };
+};
#include "skeleton.dtsi"
/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
aliases {
console = &arcuart0;
};
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <70000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
arcuart0: serial@0xc0fc1000 {
compatible = "snps,arc-uart";
reg = <0xc0fc1000 0x100>;
- clock-frequency = <80000000>;
+ clock-frequency = <70000000>;
};
};
#size-cells = <1>;
chosen { };
aliases { };
- memory { device_type = "memory"; reg = <0 0>; };
+
+ cpu_card {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ timer@0 {
+ compatible = "snps,arc-timer";
+ clocks = <&core_clk>;
+ reg = <0 1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256M */
+ };
};
-if TARGET_AXS10X
+if TARGET_AXS101 || TARGET_AXS103
config SYS_BOARD
default "axs10x"
CONFIG_ARC=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_TARGET_AXS101=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=750000000
-CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_DEFAULT_DEVICE_TREE="axs101"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="AXS# "
CONFIG_ISA_ARCV2=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=100000000
-CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_DEFAULT_DEVICE_TREE="axs103"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="AXS# "