$(MAKE) -C tools/updater all || exit 1
env:
- $(MAKE) -C tools/env all || exit 1
+ $(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1
depend dep: version
for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices.
+ */
+void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
+}
+#endif
+
/*************************************************************************
* pci_pre_init
*
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
+#ifdef CONFIG_PCI_PNP
+ hose->fixup_irq = sequoia_pci_fixup_irq;
+#endif
return 1;
}
#endif /* defined(CONFIG_PCI) */
if (argc > 1) {
if (!strcmp(argv[1], "400")) {
- /* PLB=133MHz, PLB/PCI=4 */
+ /* PLB=133MHz, PLB/PCI=3 */
printf("Bootstrapping for 400MHz\n");
sdsdp[0]=0x8678624e;
- sdsdp[1]=0x0947a030;
+ sdsdp[1]=0x095fa030;
sdsdp[2]=0x40082350;
sdsdp[3]=0x0d050000;
} else if (!strcmp(argv[1], "533")) {
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o flash.o
+COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*
- * CPU to flash interface is 8-bit, so make declaration accordingly
- */
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1 0x0555
-#define FLASH_CYCLE2 0x02aa
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- unsigned long size = 0;
- extern void flash_preinit(void);
- ulong flashbase = CFG_FLASH_BASE;
-
- flash_preinit();
-
- /* Init: no FLASHes known */
- memset(&flash_info[0], 0, sizeof(flash_info_t));
-
- flash_info[0].size =
- flash_get_size((FPW *)flashbase, &flash_info[0]);
-
- size = flash_info[0].size;
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- flash_get_info(CFG_MONITOR_BASE));
-#endif
-
-#ifdef CFG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SIZE-1,
- flash_get_info(CFG_ENV_ADDR));
-#endif
-
- return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
- FPWV *base = (FPWV *)(info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
- *base = (FPW)0x00FF00FF; /* Intel Read Mode */
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- *base = (FPW)0x00F000F0; /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
- int i;
- flash_info_t * info;
-
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
- info = & flash_info[i];
- if (info->size && info->start[0] <= base &&
- base <= info->start[0] + info->size - 1)
- break;
- }
-
- return i == CFG_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM116DB:
- printf ("AM29LV116DB (16Mbit, bottom boot sect)\n");
- break;
- case FLASH_AMLV128U:
- printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
- break;
- case FLASH_AM160B:
- printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
- int i;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte.
- * This works for any bus width and any FLASH device width.
- */
- udelay(100);
- switch (addr[0] & 0xff) {
-
- case (uchar)AMD_MANUFACT:
- debug ("Manufacturer: AMD (Spansion)\n");
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case (uchar)INTEL_MANUFACT:
- debug ("Manufacturer: Intel (not supported yet)\n");
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
-
- case (uchar)AMD_ID_LV116DB:
- debug ("Chip: AM29LV116DB\n");
- info->flash_id += FLASH_AM116DB;
- info->sector_count = 35;
- info->size = 0x00200000;
- /*
- * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
- * the other ones are 64 kB
- */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for( i = 4; i < info->sector_count; i++ )
- info->start[i] =
- base + (i * (64 << 10)) - 0x00030000;
- break; /* => 2 MB */
-
- case (FPW)AMD_ID_LV160B:
- debug ("Chip: AM29LV160MB\n");
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- /*
- * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
- * the other ones are 64 kB
- */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for( i = 4; i < info->sector_count; i++ )
- info->start[i] =
- base + (i * 2 * (64 << 10)) - 0x00060000;
- break; /* => 4 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- }
-
- /* Put FLASH back in read mode */
- flash_reset(info);
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- FPWV *addr = (FPWV*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = (FPW)0x00AA00AA;
- addr[0x02AA] = (FPW)0x00550055;
- addr[0x0555] = (FPW)0x00800080;
- addr[0x0555] = (FPW)0x00AA00AA;
- addr[0x02AA] = (FPW)0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FPWV*)(info->start[sect]);
- addr[0] = (FPW)0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FPWV*)(info->start[l_sect]);
- while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (FPWV*)info->start[0];
- addr[0] = (FPW)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- int i, rc = 0;
-
- for (i = 0; i < cnt; i++)
- if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) {
- return (rc);
- }
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
- base = (FPWV *)(info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00F000F0; /* reset bank */
- return (1);
- }
- }
- return (0);
-}
--- /dev/null
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714F0F00
+#define SDRAM_CONFIG1 0x73711930
+#define SDRAM_CONFIG2 0x46770000
+#define SDRAM_TAPDELAY 0x10000000
#include <mpc5xxx.h>
#include <pci.h>
-#if defined(CONFIG_MPC5200_DDR)
+#if defined(CONFIG_DDR_MT46V16M16)
#include "mt46v16m16-75.h"
-#else
+#elif defined(CONFIG_SDR_MT48LC16M16A2)
#include "mt48lc16m16a2-75.h"
+#elif defined(CONFIG_DDR_MT46V32M16)
+#include "mt46v32m16.h"
+#elif defined(CONFIG_DDR_HYB25D512160BF)
+#include "hyb25d512160bf.h"
+#elif defined(CONFIG_DDR_K4H511638C)
+#include "k4h511638c.h"
+#else
+#error "INKA4x0 SDRAM: invalid chip type specified!"
#endif
#ifndef CFG_RAMBOOT
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
- ulong test1, test2;
+ long test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
int misc_init_f (void)
{
- uchar tmp[10];
+ char tmp[10];
int i, br;
i = getenv_r("brightness", tmp, sizeof(tmp));
--- /dev/null
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714F0F00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x46770000
+#define SDRAM_TAPDELAY 0x10000000
#define SDRAM_DDR 1 /* is DDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x714f0f00
+#define SDRAM_CONTROL 0x714F0F00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
--- /dev/null
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714F0F00
+#define SDRAM_CONFIG1 0x73711930
+#define SDRAM_CONFIG2 0x46770000
+#define SDRAM_TAPDELAY 0x10000000
* MA 02111-1307 USA
*/
-#define SDRAM_DDR 1 /* is SDR */
+#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
-/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
-/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
#define SDRAM_CONFIG2 0x8AD70000
-/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#endif
/* TLB-entry for PCI Memory */
#include <405_mal.h>
#include <miiphy.h>
#include <malloc.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
/*
* Only compile for platform with AMCC EMAC ethernet controller and
hw_p->bis = bis;
hw_p->first_init = 1;
- return (1);
+ return 0;
}
#endif
#endif
} /* end for each supported device */
- return (1);
+
+ return 0;
}
#if !defined(CONFIG_NET_MULTI)
#include <asm/processor.h>
#include <asm/io.h>
#include <watchdog.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
#ifdef CONFIG_SERIAL_MULTI
#include <serial.h>
#include <common.h>
#include <commproc.h>
-
+#include <asm/io.h>
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+#if defined(CFG_POST_ALT_WORD_ADDR)
+void post_word_store (ulong a)
+{
+ out_be32((void *)CFG_POST_ALT_WORD_ADDR, a);
+}
+
+ulong post_word_load (void)
+{
+ return in_be32((void *)CFG_POST_ALT_WORD_ADDR);
+}
+#else /* CFG_POST_ALT_WORD_ADDR */
void post_word_store (ulong a)
{
volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
return *(volatile ulong *) save_addr;
}
+#endif /* CFG_POST_ALT_WORD_ADDR */
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/processor.h>
#include <asm/io.h>
#include <watchdog.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
#ifdef CONFIG_SERIAL_MULTI
#include <serial.h>
dcbz r0,r3
addi r3,r3,32
bdnz ..d_ag
+
+ /*
+ * Lock the init-ram/stack in d-cache, so that other regions
+ * may use d-cache as well
+ * Note, that this current implementation locks exactly 4k
+ * of d-cache, so please make sure that you don't define a
+ * bigger init-ram area. Take a look at the lwmon5 440EPx
+ * implementation as a reference.
+ */
+ msync
+ isync
+ /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
+ lis r1,0x0201
+ ori r1,r1,0xf808
+ mtspr dvlim,r1
+ lis r1,0x0808
+ ori r1,r1,0x0808
+ mtspr dnv0,r1
+ mtspr dnv1,r1
+ mtspr dnv2,r1
+ mtspr dnv3,r1
+ mtspr dtv0,r1
+ mtspr dtv1,r1
+ mtspr dtv2,r1
+ mtspr dtv3,r1
+ msync
+ isync
#endif /* CFG_INIT_RAM_DCACHE */
/* 440EP & 440GR are only 440er PPC's without internal SRAM */
mr r4,r10
mr r5,r11
#endif
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /*
+ * Unlock the previously locked d-cache
+ */
+ msync
+ isync
+ /* set TFLOOR/NFLOOR to 0 again */
+ lis r6,0x0001
+ ori r6,r6,0xf800
+ mtspr dvlim,r6
+ lis r6,0x0000
+ ori r6,r6,0x0000
+ mtspr dnv0,r6
+ mtspr dnv1,r6
+ mtspr dnv2,r6
+ mtspr dnv3,r6
+ mtspr dtv0,r6
+ mtspr dtv1,r6
+ mtspr dtv2,r6
+ mtspr dtv3,r6
+ msync
+ isync
+#endif /* CFG_INIT_RAM_DCACHE */
+
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#include <usb.h>
#include "usbdev.h"
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
+++ /dev/null
-/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-
-/*
- * Interrupt vector number definitions to ease the
- * 405 -- 440 porting pain ;-)
- *
- * NOTE: They're not all here yet ... update as needed.
- *
- */
-
-#ifndef _VECNUMS_H_
-#define _VECNUMS_H_
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-/* UIC 0 */
-#define VECNUM_U0 0 /* UART 0 */
-#define VECNUM_U1 1 /* UART 1 */
-#define VECNUM_IIC0 2 /* IIC */
-#define VECNUM_KRD 3 /* Kasumi Ready for data */
-#define VECNUM_KDA 4 /* Kasumi Data Available */
-#define VECNUM_PCRW 5 /* PCI command register write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_IIC1 7 /* IIC */
-#define VECNUM_SPI 8 /* SPI */
-#define VECNUM_EPCISER 9 /* External PCI SERR */
-#define VECNUM_MTE 10 /* MAL TXEOB */
-#define VECNUM_MRE 11 /* MAL RXEOB */
-#define VECNUM_D0 12 /* DMA channel 0 */
-#define VECNUM_D1 13 /* DMA channel 1 */
-#define VECNUM_D2 14 /* DMA channel 2 */
-#define VECNUM_D3 15 /* DMA channel 3 */
-#define VECNUM_UD0 16 /* UDMA irq 0 */
-#define VECNUM_UD1 17 /* UDMA irq 1 */
-#define VECNUM_UD2 18 /* UDMA irq 2 */
-#define VECNUM_UD3 19 /* UDMA irq 3 */
-#define VECNUM_HSB2D 20 /* USB2.0 Device */
-#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */
-#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */
-#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */
-#define VECNUM_EIP94 23 /* Security EIP94 */
-#define VECNUM_ETH0 24 /* Emac 0 */
-#define VECNUM_ETH1 25 /* Emac 1 */
-#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */
-#define VECNUM_EIR4 27 /* External interrupt 4 */
-#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */
-#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_MS (32 + 0) /* MAL SERR */
-#define VECNUM_MTDE (32 + 1) /* MAL TXDE */
-#define VECNUM_MRDE (32 + 2) /* MAL RXDE */
-#define VECNUM_U2 (32 + 3) /* UART 2 */
-#define VECNUM_U3 (32 + 4) /* UART 3 */
-#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */
-#define VECNUM_NDFC (32 + 6) /* NDFC */
-#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */
-#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */
-#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */
-#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */
-#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */
-#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */
-#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */
-#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */
-#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */
-#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */
-#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */
-#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */
-#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */
-#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */
-#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */
-#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */
-#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */
-#define VECNUM_SRE (32 + 24) /* Serial ROM error */
-#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */
-#define VECNUM_RSVD0 (32 + 26) /* Reserved */
-#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */
-#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */
-#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
-#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */
-#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */
-
-#define VECNUM_TXDE VECNUM_MTDE
-#define VECNUM_RXDE VECNUM_MRDE
-
-/* UIC 2 */
-#define VECNUM_EIR5 (62 + 0) /* External interrupt 5 */
-#define VECNUM_EIR6 (62 + 1) /* External interrupt 6 */
-#define VECNUM_OPB (62 + 2) /* OPB to PLB bridge int stat */
-#define VECNUM_EIR2 (62 + 3) /* External interrupt 2 */
-#define VECNUM_EIR3 (62 + 4) /* External interrupt 3 */
-#define VECNUM_DDR2 (62 + 5) /* DDR2 sdram */
-#define VECNUM_MCTX0 (62 + 6) /* MAl intp coalescence TX0 */
-#define VECNUM_MCTX1 (62 + 7) /* MAl intp coalescence TX1 */
-#define VECNUM_MCTR0 (62 + 8) /* MAl intp coalescence TR0 */
-#define VECNUM_MCTR1 (62 + 9) /* MAl intp coalescence TR1 */
-
-#elif defined(CONFIG_440SPE)
-
-/* UIC 0 */
-#define VECNUM_U0 0 /* UART0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_IIC0 2 /* IIC0 */
-#define VECNUM_IIC1 3 /* IIC1 */
-#define VECNUM_PIM 4 /* PCI inbound message */
-#define VECNUM_PCRW 5 /* PCI command reg write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_MSI0 7 /* PCI MSI level 0 */
-#define VECNUM_MSI1 8 /* PCI MSI level 0 */
-#define VECNUM_MSI2 9 /* PCI MSI level 0 */
-#define VECNUM_D0 12 /* DMA channel 0 */
-#define VECNUM_D1 13 /* DMA channel 1 */
-#define VECNUM_D2 14 /* DMA channel 2 */
-#define VECNUM_D3 15 /* DMA channel 3 */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_MS (32 + 1 ) /* MAL SERR */
-#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */
-#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */
-#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */
-#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */
-#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */
-#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */
-#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */
-#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */
-#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */
-#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
-#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
-
-/* UIC 2 */
-#define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */
-#define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */
-#define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */
-#define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */
-#define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */
-#define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */
-
-#elif defined(CONFIG_440SP)
-
-/* UIC 0 */
-#define VECNUM_U0 0 /* UART0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_IIC0 2 /* IIC0 */
-#define VECNUM_IIC1 3 /* IIC1 */
-#define VECNUM_PIM 4 /* PCI inbound message */
-#define VECNUM_PCRW 5 /* PCI command reg write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
-#define VECNUM_MS (32 + 1) /* MAL SERR */
-#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
-#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
-#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
-#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
-#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
-#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
-#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
-#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
-#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
-#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
-#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
-
-#elif defined(CONFIG_440)
-
-/* UIC 0 */
-#define VECNUM_U0 0 /* UART0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_IIC0 2 /* IIC0 */
-#define VECNUM_IIC1 3 /* IIC1 */
-#define VECNUM_PIM 4 /* PCI inbound message */
-#define VECNUM_PCRW 5 /* PCI command reg write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_MSI0 7 /* PCI MSI level 0 */
-#define VECNUM_MSI1 8 /* PCI MSI level 0 */
-#define VECNUM_MSI2 9 /* PCI MSI level 0 */
-#define VECNUM_MTE 10 /* MAL TXEOB */
-#define VECNUM_MRE 11 /* MAL RXEOB */
-#define VECNUM_D0 12 /* DMA channel 0 */
-#define VECNUM_D1 13 /* DMA channel 1 */
-#define VECNUM_D2 14 /* DMA channel 2 */
-#define VECNUM_D3 15 /* DMA channel 3 */
-#define VECNUM_CT0 18 /* GPT compare timer 0 */
-#define VECNUM_CT1 19 /* GPT compare timer 1 */
-#define VECNUM_CT2 20 /* GPT compare timer 2 */
-#define VECNUM_CT3 21 /* GPT compare timer 3 */
-#define VECNUM_CT4 22 /* GPT compare timer 4 */
-#define VECNUM_EIR0 23 /* External interrupt 0 */
-#define VECNUM_EIR1 24 /* External interrupt 1 */
-#define VECNUM_EIR2 25 /* External interrupt 2 */
-#define VECNUM_EIR3 26 /* External interrupt 3 */
-#define VECNUM_EIR4 27 /* External interrupt 4 */
-#define VECNUM_EIR5 28 /* External interrupt 5 */
-#define VECNUM_EIR6 29 /* External interrupt 6 */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_MS (32 + 0 ) /* MAL SERR */
-#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
-#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
-#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */
-#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
-#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
-
-#else /* !defined(CONFIG_440) */
-
-#if defined(CONFIG_405EZ)
-#define VECNUM_D0 0 /* DMA channel 0 */
-#define VECNUM_D1 1 /* DMA channel 1 */
-#define VECNUM_D2 2 /* DMA channel 2 */
-#define VECNUM_D3 3 /* DMA channel 3 */
-#define VECNUM_1588 4 /* IEEE 1588 network synchronization */
-#define VECNUM_U0 5 /* UART0 */
-#define VECNUM_U1 6 /* UART1 */
-#define VECNUM_CAN0 7 /* CAN 0 */
-#define VECNUM_CAN1 8 /* CAN 1 */
-#define VECNUM_SPI 9 /* SPI */
-#define VECNUM_IIC0 10 /* I2C */
-#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
-#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
-#define VECNUM_USBH1 13 /* USB Host 1 */
-#define VECNUM_USBH2 14 /* USB Host 2 */
-#define VECNUM_USBDEV 15 /* USB Device */
-#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
-#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
-
-#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
-#define VECNUM_MS 18 /* MAL_SERR_INT */
-#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
-#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
-
-#define VECNUM_MTE 19 /* MAL TXEOB */
-#define VECNUM_MTE1 20 /* MAL TXEOB1 */
-#define VECNUM_MRE 21 /* MAL RXEOB */
-#define VECNUM_NAND 22 /* NAND Flash controller */
-#define VECNUM_ADC 23 /* ADC */
-#define VECNUM_DAC 24 /* DAC */
-#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
-#define VECNUM_RESERVED0 26 /* Reserved */
-#define VECNUM_EIR0 27 /* External interrupt 0 */
-#define VECNUM_EIR1 28 /* External interrupt 1 */
-#define VECNUM_EIR2 29 /* External interrupt 2 */
-#define VECNUM_EIR3 30 /* External interrupt 3 */
-#define VECNUM_EIR4 31 /* External interrupt 4 */
-
-#elif defined(CONFIG_405EX)
-
-/* UIC 0 */
-#define VECNUM_U0 00
-#define VECNUM_U1 01
-#define VECNUM_IIC0 02
-#define VECNUM_PKA 03
-#define VECNUM_TRNG 04
-#define VECNUM_EBM 05
-#define VECNUM_BGI 06
-#define VECNUM_IIC1 07
-#define VECNUM_SPI 08
-#define VECNUM_EIR0 09
-#define VECNUM_MTE 10 /* MAL Tx EOB */
-#define VECNUM_MRE 11 /* MAL Rx EOB */
-#define VECNUM_DMA0 12
-#define VECNUM_DMA1 13
-#define VECNUM_DMA2 14
-#define VECNUM_DMA3 15
-#define VECNUM_PCIE0AL 16
-#define VECNUM_PCIE0VPD 17
-#define VECNUM_RPCIE0HRST 18
-#define VECNUM_FPCIE0HRST 19
-#define VECNUM_PCIE0TCR 20
-#define VECNUM_PCIEMSI0 21
-#define VECNUM_PCIEMSI1 22
-#define VECNUM_SECURITY 23
-#define VECNUM_ETH0 24
-#define VECNUM_ETH1 25
-#define VECNUM_PCIEMSI2 26
-#define VECNUM_EIR4 27
-#define VECNUM_UIC2NC 28
-#define VECNUM_UIC2C 29
-#define VECNUM_UIC1NC 30
-#define VECNUM_UIC1C 31
-
-/* UIC 1 */
-#define VECNUM_MS (32 + 00) /* MAL SERR */
-#define VECNUM_TXDE (32 + 01) /* MAL TXDE */
-#define VECNUM_RXDE (32 + 02) /* MAL RXDE */
-#define VECNUM_PCIE0BMVC0 (32 + 03)
-#define VECNUM_PCIE0DCRERR (32 + 04)
-#define VECNUM_EBC (32 + 05)
-#define VECNUM_NDFC (32 + 06)
-#define VECNUM_PCEI1DCRERR (32 + 07)
-#define VECNUM_CT8 (32 + 08)
-#define VECNUM_CT9 (32 + 09)
-#define VECNUM_PCIE1AL (32 + 10)
-#define VECNUM_PCIE1VPD (32 + 11)
-#define VECNUM_RPCE1HRST (32 + 12)
-#define VECNUM_FPCE1HRST (32 + 13)
-#define VECNUM_PCIE1TCR (32 + 14)
-#define VECNUM_PCIE1VC0 (32 + 15)
-#define VECNUM_CT3 (32 + 16)
-#define VECNUM_CT4 (32 + 17)
-#define VECNUM_EIR7 (32 + 18)
-#define VECNUM_EIR8 (32 + 19)
-#define VECNUM_EIR9 (32 + 20)
-#define VECNUM_CT5 (32 + 21)
-#define VECNUM_CT6 (32 + 22)
-#define VECNUM_CT7 (32 + 23)
-#define VECNUM_SROM (32 + 24) /* SERIAL ROM */
-#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */
-#define VECNUM_EIR2 (32 + 26)
-#define VECNUM_EIR5 (32 + 27)
-#define VECNUM_EIR6 (32 + 28)
-#define VECNUM_EMAC0WAKE (32 + 29)
-#define VECNUM_EIR1 (32 + 30)
-#define VECNUM_EMAC1WAKE (32 + 31)
-
-/* UIC 2 */
-#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */
-#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */
-#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */
-#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */
-#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */
-#define VECNUM_DDRMCUE (64 + 05)
-#define VECNUM_DDRMCCE (64 + 06)
-#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */
-#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */
-#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */
-#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */
-#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */
-#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */
-#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */
-#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */
-#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */
-#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */
-#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */
-#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */
-#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */
-#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */
-#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */
-#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */
-#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */
-#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */
-#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */
-#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */
-#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */
-#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */
-#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */
-#define VECNUM_USBWAKE (64 + 30) /* USB wakup */
-#define VECNUM_USBOTG (64 + 31) /* USB OTG */
-
-#else /* !CONFIG_405EZ */
-
-#define VECNUM_U0 0 /* UART0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_D0 5 /* DMA channel 0 */
-#define VECNUM_D1 6 /* DMA channel 1 */
-#define VECNUM_D2 7 /* DMA channel 2 */
-#define VECNUM_D3 8 /* DMA channel 3 */
-#define VECNUM_EWU0 9 /* Ethernet wakeup */
-#define VECNUM_MS 10 /* MAL SERR */
-#define VECNUM_MTE 11 /* MAL TXEOB */
-#define VECNUM_MRE 12 /* MAL RXEOB */
-#define VECNUM_TXDE 13 /* MAL TXDE */
-#define VECNUM_RXDE 14 /* MAL RXDE */
-#define VECNUM_ETH0 15 /* Ethernet interrupt status */
-#define VECNUM_EIR0 25 /* External interrupt 0 */
-#define VECNUM_EIR1 26 /* External interrupt 1 */
-#define VECNUM_EIR2 27 /* External interrupt 2 */
-#define VECNUM_EIR3 28 /* External interrupt 3 */
-#define VECNUM_EIR4 29 /* External interrupt 4 */
-#define VECNUM_EIR5 30 /* External interrupt 5 */
-#define VECNUM_EIR6 31 /* External interrupt 6 */
-#endif /* defined(CONFIG_405EZ) */
-
-#endif /* defined(CONFIG_440) */
-
-#endif /* _VECNUMS_H_ */
return (-1);
}
} else {
- memset (buf, blocksize - skipfirst, 0);
+ memset (buf, 0, blocksize - skipfirst);
}
buf += blocksize - skipfirst;
}
--- /dev/null
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+/*
+ * Interrupt vector number definitions to ease the
+ * 405 -- 440 porting pain ;-)
+ *
+ * NOTE: They're not all here yet ... update as needed.
+ *
+ */
+
+#ifndef _VECNUMS_H_
+#define _VECNUMS_H_
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+/* UIC 0 */
+#define VECNUM_U0 0 /* UART 0 */
+#define VECNUM_U1 1 /* UART 1 */
+#define VECNUM_IIC0 2 /* IIC */
+#define VECNUM_KRD 3 /* Kasumi Ready for data */
+#define VECNUM_KDA 4 /* Kasumi Data Available */
+#define VECNUM_PCRW 5 /* PCI command register write */
+#define VECNUM_PPM 6 /* PCI power management */
+#define VECNUM_IIC1 7 /* IIC */
+#define VECNUM_SPI 8 /* SPI */
+#define VECNUM_EPCISER 9 /* External PCI SERR */
+#define VECNUM_MTE 10 /* MAL TXEOB */
+#define VECNUM_MRE 11 /* MAL RXEOB */
+#define VECNUM_D0 12 /* DMA channel 0 */
+#define VECNUM_D1 13 /* DMA channel 1 */
+#define VECNUM_D2 14 /* DMA channel 2 */
+#define VECNUM_D3 15 /* DMA channel 3 */
+#define VECNUM_UD0 16 /* UDMA irq 0 */
+#define VECNUM_UD1 17 /* UDMA irq 1 */
+#define VECNUM_UD2 18 /* UDMA irq 2 */
+#define VECNUM_UD3 19 /* UDMA irq 3 */
+#define VECNUM_HSB2D 20 /* USB2.0 Device */
+#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */
+#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */
+#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */
+#define VECNUM_EIP94 23 /* Security EIP94 */
+#define VECNUM_ETH0 24 /* Emac 0 */
+#define VECNUM_ETH1 25 /* Emac 1 */
+#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */
+#define VECNUM_EIR4 27 /* External interrupt 4 */
+#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */
+#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */
+#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
+
+/* UIC 1 */
+#define VECNUM_MS (32 + 0) /* MAL SERR */
+#define VECNUM_MTDE (32 + 1) /* MAL TXDE */
+#define VECNUM_MRDE (32 + 2) /* MAL RXDE */
+#define VECNUM_U2 (32 + 3) /* UART 2 */
+#define VECNUM_U3 (32 + 4) /* UART 3 */
+#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */
+#define VECNUM_NDFC (32 + 6) /* NDFC */
+#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */
+#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */
+#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */
+#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */
+#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */
+#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */
+#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */
+#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */
+#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */
+#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */
+#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */
+#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */
+#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */
+#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */
+#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */
+#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */
+#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */
+#define VECNUM_SRE (32 + 24) /* Serial ROM error */
+#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */
+#define VECNUM_RSVD0 (32 + 26) /* Reserved */
+#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */
+#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */
+#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
+#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */
+#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */
+
+#define VECNUM_TXDE VECNUM_MTDE
+#define VECNUM_RXDE VECNUM_MRDE
+
+/* UIC 2 */
+#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */
+#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */
+#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */
+#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */
+#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */
+#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */
+#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */
+#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */
+#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */
+#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */
+
+#elif defined(CONFIG_440SPE)
+
+/* UIC 0 */
+#define VECNUM_U0 0 /* UART0 */
+#define VECNUM_U1 1 /* UART1 */
+#define VECNUM_IIC0 2 /* IIC0 */
+#define VECNUM_IIC1 3 /* IIC1 */
+#define VECNUM_PIM 4 /* PCI inbound message */
+#define VECNUM_PCRW 5 /* PCI command reg write */
+#define VECNUM_PPM 6 /* PCI power management */
+#define VECNUM_MSI0 7 /* PCI MSI level 0 */
+#define VECNUM_MSI1 8 /* PCI MSI level 0 */
+#define VECNUM_MSI2 9 /* PCI MSI level 0 */
+#define VECNUM_D0 12 /* DMA channel 0 */
+#define VECNUM_D1 13 /* DMA channel 1 */
+#define VECNUM_D2 14 /* DMA channel 2 */
+#define VECNUM_D3 15 /* DMA channel 3 */
+#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
+
+/* UIC 1 */
+#define VECNUM_MS (32 + 1 ) /* MAL SERR */
+#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */
+#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */
+#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */
+#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */
+#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */
+#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */
+#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */
+#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */
+#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */
+#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
+#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
+
+/* UIC 2 */
+#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */
+#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */
+#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */
+#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */
+#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */
+#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */
+
+#elif defined(CONFIG_440SP)
+
+/* UIC 0 */
+#define VECNUM_U0 0 /* UART0 */
+#define VECNUM_U1 1 /* UART1 */
+#define VECNUM_IIC0 2 /* IIC0 */
+#define VECNUM_IIC1 3 /* IIC1 */
+#define VECNUM_PIM 4 /* PCI inbound message */
+#define VECNUM_PCRW 5 /* PCI command reg write */
+#define VECNUM_PPM 6 /* PCI power management */
+#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
+
+/* UIC 1 */
+#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
+#define VECNUM_MS (32 + 1) /* MAL SERR */
+#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
+#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
+#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
+#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
+#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
+#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
+#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
+#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
+#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
+#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
+#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
+
+#elif defined(CONFIG_440)
+
+/* UIC 0 */
+#define VECNUM_U0 0 /* UART0 */
+#define VECNUM_U1 1 /* UART1 */
+#define VECNUM_IIC0 2 /* IIC0 */
+#define VECNUM_IIC1 3 /* IIC1 */
+#define VECNUM_PIM 4 /* PCI inbound message */
+#define VECNUM_PCRW 5 /* PCI command reg write */
+#define VECNUM_PPM 6 /* PCI power management */
+#define VECNUM_MSI0 7 /* PCI MSI level 0 */
+#define VECNUM_MSI1 8 /* PCI MSI level 0 */
+#define VECNUM_MSI2 9 /* PCI MSI level 0 */
+#define VECNUM_MTE 10 /* MAL TXEOB */
+#define VECNUM_MRE 11 /* MAL RXEOB */
+#define VECNUM_D0 12 /* DMA channel 0 */
+#define VECNUM_D1 13 /* DMA channel 1 */
+#define VECNUM_D2 14 /* DMA channel 2 */
+#define VECNUM_D3 15 /* DMA channel 3 */
+#define VECNUM_CT0 18 /* GPT compare timer 0 */
+#define VECNUM_CT1 19 /* GPT compare timer 1 */
+#define VECNUM_CT2 20 /* GPT compare timer 2 */
+#define VECNUM_CT3 21 /* GPT compare timer 3 */
+#define VECNUM_CT4 22 /* GPT compare timer 4 */
+#define VECNUM_EIR0 23 /* External interrupt 0 */
+#define VECNUM_EIR1 24 /* External interrupt 1 */
+#define VECNUM_EIR2 25 /* External interrupt 2 */
+#define VECNUM_EIR3 26 /* External interrupt 3 */
+#define VECNUM_EIR4 27 /* External interrupt 4 */
+#define VECNUM_EIR5 28 /* External interrupt 5 */
+#define VECNUM_EIR6 29 /* External interrupt 6 */
+#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
+
+/* UIC 1 */
+#define VECNUM_MS (32 + 0 ) /* MAL SERR */
+#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
+#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
+#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */
+#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
+#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
+
+#else /* !defined(CONFIG_440) */
+
+#if defined(CONFIG_405EZ)
+#define VECNUM_D0 0 /* DMA channel 0 */
+#define VECNUM_D1 1 /* DMA channel 1 */
+#define VECNUM_D2 2 /* DMA channel 2 */
+#define VECNUM_D3 3 /* DMA channel 3 */
+#define VECNUM_1588 4 /* IEEE 1588 network synchronization */
+#define VECNUM_U0 5 /* UART0 */
+#define VECNUM_U1 6 /* UART1 */
+#define VECNUM_CAN0 7 /* CAN 0 */
+#define VECNUM_CAN1 8 /* CAN 1 */
+#define VECNUM_SPI 9 /* SPI */
+#define VECNUM_IIC0 10 /* I2C */
+#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
+#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
+#define VECNUM_USBH1 13 /* USB Host 1 */
+#define VECNUM_USBH2 14 /* USB Host 2 */
+#define VECNUM_USBDEV 15 /* USB Device */
+#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
+#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
+
+#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
+#define VECNUM_MS 18 /* MAL_SERR_INT */
+#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
+#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
+
+#define VECNUM_MTE 19 /* MAL TXEOB */
+#define VECNUM_MTE1 20 /* MAL TXEOB1 */
+#define VECNUM_MRE 21 /* MAL RXEOB */
+#define VECNUM_NAND 22 /* NAND Flash controller */
+#define VECNUM_ADC 23 /* ADC */
+#define VECNUM_DAC 24 /* DAC */
+#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
+#define VECNUM_RESERVED0 26 /* Reserved */
+#define VECNUM_EIR0 27 /* External interrupt 0 */
+#define VECNUM_EIR1 28 /* External interrupt 1 */
+#define VECNUM_EIR2 29 /* External interrupt 2 */
+#define VECNUM_EIR3 30 /* External interrupt 3 */
+#define VECNUM_EIR4 31 /* External interrupt 4 */
+
+#elif defined(CONFIG_405EX)
+
+/* UIC 0 */
+#define VECNUM_U0 00
+#define VECNUM_U1 01
+#define VECNUM_IIC0 02
+#define VECNUM_PKA 03
+#define VECNUM_TRNG 04
+#define VECNUM_EBM 05
+#define VECNUM_BGI 06
+#define VECNUM_IIC1 07
+#define VECNUM_SPI 08
+#define VECNUM_EIR0 09
+#define VECNUM_MTE 10 /* MAL Tx EOB */
+#define VECNUM_MRE 11 /* MAL Rx EOB */
+#define VECNUM_DMA0 12
+#define VECNUM_DMA1 13
+#define VECNUM_DMA2 14
+#define VECNUM_DMA3 15
+#define VECNUM_PCIE0AL 16
+#define VECNUM_PCIE0VPD 17
+#define VECNUM_RPCIE0HRST 18
+#define VECNUM_FPCIE0HRST 19
+#define VECNUM_PCIE0TCR 20
+#define VECNUM_PCIEMSI0 21
+#define VECNUM_PCIEMSI1 22
+#define VECNUM_SECURITY 23
+#define VECNUM_ETH0 24
+#define VECNUM_ETH1 25
+#define VECNUM_PCIEMSI2 26
+#define VECNUM_EIR4 27
+#define VECNUM_UIC2NC 28
+#define VECNUM_UIC2C 29
+#define VECNUM_UIC1NC 30
+#define VECNUM_UIC1C 31
+
+/* UIC 1 */
+#define VECNUM_MS (32 + 00) /* MAL SERR */
+#define VECNUM_TXDE (32 + 01) /* MAL TXDE */
+#define VECNUM_RXDE (32 + 02) /* MAL RXDE */
+#define VECNUM_PCIE0BMVC0 (32 + 03)
+#define VECNUM_PCIE0DCRERR (32 + 04)
+#define VECNUM_EBC (32 + 05)
+#define VECNUM_NDFC (32 + 06)
+#define VECNUM_PCEI1DCRERR (32 + 07)
+#define VECNUM_CT8 (32 + 08)
+#define VECNUM_CT9 (32 + 09)
+#define VECNUM_PCIE1AL (32 + 10)
+#define VECNUM_PCIE1VPD (32 + 11)
+#define VECNUM_RPCE1HRST (32 + 12)
+#define VECNUM_FPCE1HRST (32 + 13)
+#define VECNUM_PCIE1TCR (32 + 14)
+#define VECNUM_PCIE1VC0 (32 + 15)
+#define VECNUM_CT3 (32 + 16)
+#define VECNUM_CT4 (32 + 17)
+#define VECNUM_EIR7 (32 + 18)
+#define VECNUM_EIR8 (32 + 19)
+#define VECNUM_EIR9 (32 + 20)
+#define VECNUM_CT5 (32 + 21)
+#define VECNUM_CT6 (32 + 22)
+#define VECNUM_CT7 (32 + 23)
+#define VECNUM_SROM (32 + 24) /* SERIAL ROM */
+#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */
+#define VECNUM_EIR2 (32 + 26)
+#define VECNUM_EIR5 (32 + 27)
+#define VECNUM_EIR6 (32 + 28)
+#define VECNUM_EMAC0WAKE (32 + 29)
+#define VECNUM_EIR1 (32 + 30)
+#define VECNUM_EMAC1WAKE (32 + 31)
+
+/* UIC 2 */
+#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */
+#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */
+#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */
+#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */
+#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */
+#define VECNUM_DDRMCUE (64 + 05)
+#define VECNUM_DDRMCCE (64 + 06)
+#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */
+#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */
+#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */
+#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */
+#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */
+#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */
+#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */
+#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */
+#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */
+#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */
+#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */
+#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */
+#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */
+#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */
+#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */
+#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */
+#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */
+#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */
+#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */
+#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */
+#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */
+#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */
+#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */
+#define VECNUM_USBWAKE (64 + 30) /* USB wakup */
+#define VECNUM_USBOTG (64 + 31) /* USB OTG */
+
+#else /* !CONFIG_405EZ */
+
+#define VECNUM_U0 0 /* UART0 */
+#define VECNUM_U1 1 /* UART1 */
+#define VECNUM_D0 5 /* DMA channel 0 */
+#define VECNUM_D1 6 /* DMA channel 1 */
+#define VECNUM_D2 7 /* DMA channel 2 */
+#define VECNUM_D3 8 /* DMA channel 3 */
+#define VECNUM_EWU0 9 /* Ethernet wakeup */
+#define VECNUM_MS 10 /* MAL SERR */
+#define VECNUM_MTE 11 /* MAL TXEOB */
+#define VECNUM_MRE 12 /* MAL RXEOB */
+#define VECNUM_TXDE 13 /* MAL TXDE */
+#define VECNUM_RXDE 14 /* MAL RXDE */
+#define VECNUM_ETH0 15 /* Ethernet interrupt status */
+#define VECNUM_EIR0 25 /* External interrupt 0 */
+#define VECNUM_EIR1 26 /* External interrupt 1 */
+#define VECNUM_EIR2 27 /* External interrupt 2 */
+#define VECNUM_EIR3 28 /* External interrupt 3 */
+#define VECNUM_EIR4 29 /* External interrupt 4 */
+#define VECNUM_EIR5 30 /* External interrupt 5 */
+#define VECNUM_EIR6 31 /* External interrupt 6 */
+#endif /* defined(CONFIG_405EZ) */
+
+#endif /* defined(CONFIG_440) */
+
+#endif /* _VECNUMS_H_ */
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
+#if defined (CONFIG_NAND_U_BOOT)
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
#define CFG_NAND_OOBSIZE 16
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+#endif
#ifdef CFG_ENV_IS_IN_NAND
/*
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CFG_NAND_QUIET_TEST 1
/*
* Internal Definitions
/* USB */
#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
#define CONFIG_USB_OHCI_NEW
+#define CFG_OHCI_BE_CONTROLLER
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
"cp.l 100000 f0000b28 1\0" \
"ideargs=setenv bootargs root=/dev/hda1 rw\0" \
"ide_boot=ext2load ide 0:1 200000 uImage;" \
- "run ideargs addip addcons enable_disp;bootm" \
+ "run ideargs addip addcons enable_disp;bootm\0" \
"brightness=255\0" \
""
/*
* Flash configuration
*/
-#define CFG_FLASH_BASE 0xFFE00000
-
-#define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */
-#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
-
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */
-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_BASE 0xffe00000
+#define CFG_FLASH_SIZE 0x00200000
+#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_OVERWRITE 1
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*
* Memory map
#define CFG_SDRAM_BASE 0x00000000
#define CFG_DEFAULT_MBAR 0x80000000
-#define CONFIG_MPC5200_DDR
+/*
+ * SDRAM controller configuration
+ */
+#undef CONFIG_SDR_MT48LC16M16A2
+#undef CONFIG_DDR_MT46V16M16
+#undef CONFIG_DDR_MT46V32M16
+#undef CONFIG_DDR_HYB25D512160BF
+#define CONFIG_DDR_K4H511638C
/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
# define CFG_RAMBOOT 1
#endif
-#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
-#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
-
+/*
+ * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
+ * the POST_WORD from OCM to a 440EPx register that preserves it's
+ * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
+ * for logbuffer only.
+ */
+#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
+ /* unused GPT0 COMP reg */
/*-----------------------------------------------------------------------
* Serial Port
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
-#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#define GPT0_COMP6 0x00000098
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_USB2D0CR 0x0320
"SPR test",
"spr",
"This test checks SPR contents.",
- POST_ROM | POST_ALWAYS | POST_PREREL,
+ POST_RAM | POST_ALWAYS,
&spr_post_test,
NULL,
NULL,
CPPFLAGS := -Wall -DUSE_HOSTCC
+ifeq ($(MTD_VERSION),old)
+CPPFLAGS += -DMTD_OLD
+endif
+
all: $(obj)fw_printenv
$(obj)fw_printenv: $(SRCS) $(HEADERS)
#define CONFIG_FILE "/etc/fw_env.config"
in fw_env.h.
+For building against older versions of the MTD headers (meaning before
+v2.6.8-rc1) it is required to pass the argument "MTD_VERSION=old" to
+make.
+
See comments in the fw_env.config file for definitions for the
particular board.
#include <sys/ioctl.h>
#include <sys/stat.h>
#include <unistd.h>
-#include <linux/mtd/mtd.h>
-#include "fw_env.h"
-typedef unsigned char uchar;
+#ifdef MTD_OLD
+# include <linux/mtd/mtd.h>
+#else
+# define __user /* nothing */
+# include <mtd/mtd-user.h>
+#endif
+
+#include "fw_env.h"
#define CMD_GETENV "fw_printenv"
#define CMD_SETENV "fw_setenv"
typedef struct envdev_s {
- uchar devname[16]; /* Device name */
+ char devname[16]; /* Device name */
ulong devoff; /* Device offset */
ulong env_size; /* environment size */
ulong erase_size; /* device erase size */
typedef struct environment_s {
ulong crc; /* CRC32 over data bytes */
- uchar flags; /* active or obsolete */
- uchar *data;
+ unsigned char flags; /* active or obsolete */
+ char *data;
} env_t;
static env_t environment;
static int HaveRedundEnv = 0;
-static uchar active_flag = 1;
-static uchar obsolete_flag = 0;
+static unsigned char active_flag = 1;
+static unsigned char obsolete_flag = 0;
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
-static uchar default_environment[] = {
+static char default_environment[] = {
#if defined(CONFIG_BOOTARGS)
"bootargs=" CONFIG_BOOTARGS "\0"
#endif
};
static int flash_io (int mode);
-static uchar *envmatch (uchar * s1, uchar * s2);
+static char *envmatch (char * s1, char * s2);
static int env_init (void);
static int parse_config (void);
* Search the environment for a variable.
* Return the value, if found, or NULL, if not found.
*/
-unsigned char *fw_getenv (unsigned char *name)
+char *fw_getenv (char *name)
{
- uchar *env, *nxt;
+ char *env, *nxt;
if (env_init ())
return (NULL);
for (env = environment.data; *env; env = nxt + 1) {
- uchar *val;
+ char *val;
for (nxt = env; *nxt; ++nxt) {
if (nxt >= &environment.data[ENV_SIZE]) {
*/
void fw_printenv (int argc, char *argv[])
{
- uchar *env, *nxt;
+ char *env, *nxt;
int i, n_flag;
if (env_init ())
}
for (i = 1; i < argc; ++i) { /* print single env variables */
- uchar *name = argv[i];
- uchar *val = NULL;
+ char *name = argv[i];
+ char *val = NULL;
for (env = environment.data; *env; env = nxt + 1) {
int fw_setenv (int argc, char *argv[])
{
int i, len;
- uchar *env, *nxt;
- uchar *oldval = NULL;
- uchar *name;
+ char *env, *nxt;
+ char *oldval = NULL;
+ char *name;
if (argc < 2) {
return (EINVAL);
while ((*env = *name++) != '\0')
env++;
for (i = 2; i < argc; ++i) {
- uchar *val = argv[i];
+ char *val = argv[i];
*env = (i == 2) ? '=' : ' ';
while ((*++env = *val++) != '\0');
WRITE_FLASH:
/* Update CRC */
- environment.crc = crc32 (0, environment.data, ENV_SIZE);
+ environment.crc = crc32 (0, (uint8_t*) environment.data, ENV_SIZE);
/* write environment back to flash */
if (flash_io (O_RDWR)) {
* If the names match, return the value of s2, else NULL.
*/
-static uchar *envmatch (uchar * s1, uchar * s2)
+static char *envmatch (char * s1, char * s2)
{
while (*s1 == *s2++)
static int env_init (void)
{
int crc1, crc1_ok;
- uchar *addr1;
+ char *addr1;
int crc2, crc2_ok;
- uchar flag1, flag2, *addr2;
+ char flag1, flag2, *addr2;
if (parse_config ()) /* should fill envdevices */
return 1;
return (errno);
}
- crc1_ok = ((crc1 = crc32 (0, environment.data, ENV_SIZE))
+ crc1_ok = ((crc1 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE))
== environment.crc);
if (!HaveRedundEnv) {
if (!crc1_ok) {
return (errno);
}
- crc2_ok = ((crc2 = crc32 (0, environment.data, ENV_SIZE))
+ crc2_ok = ((crc2 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE))
== environment.crc);
flag2 = environment.flags;
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
-extern void fw_printenv(int argc, char *argv[]);
-extern unsigned char *fw_getenv (unsigned char *name);
-extern int fw_setenv (int argc, char *argv[]);
+extern void fw_printenv(int argc, char *argv[]);
+extern char *fw_getenv (char *name);
+extern int fw_setenv (int argc, char *argv[]);
extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned);
projects / oweals / u-boot.git / commitdiff