arm: vf610: Add clock support for DSPI

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>

diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 1bb9b8ed1d0ae7fb0409b516b146441812be177f..05c401dc73ce66529d7033325c5424aff1b9711e 100644 (file)
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -198,6 +198,11 @@ static u32 get_i2c_clk(void)
        return get_ipg_clk();
 }
 
+static u32 get_dspi_clk(void)
+{
+       return get_ipg_clk();
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {
@@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_fec_clk();
        case MXC_I2C_CLK:
                return get_i2c_clk();
+       case MXC_DSPI_CLK:
+               return get_dspi_clk();
        default:
                break;
        }

diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
index 535adadd79068cb9563c0d86c979c989e22f273d..e5a5c6d28f36ae8f230d5f00a255a78232d89bde 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -17,6 +17,7 @@ enum mxc_clock {
        MXC_ESDHC_CLK,
        MXC_FEC_CLK,
        MXC_I2C_CLK,
+       MXC_DSPI_CLK,
 };
 
 void enable_ocotp_clk(unsigned char enable);

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index bc6db2a5a55d5de37cc283be4972148611aa1827..fdb45e9954c4693abaa035e08db6af7fa2227e66 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -189,6 +189,8 @@ struct anadig_reg {
 #define CCM_REG_CTRL_MASK                      0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK              (0x3 << 16)
+#define CCM_CCGR0_DSPI0_CTRL_MASK              (0x3 << 24)
+#define CCM_CCGR0_DSPI1_CTRL_MASK              (0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK                        (0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK             (0x3 << 28)
@@ -206,6 +208,8 @@ struct anadig_reg {
 #define CCM_CCGR4_GPC_CTRL_MASK                        (0x3 << 24)
 #define CCM_CCGR4_I2C0_CTRL_MASK               (0x3 << 12)
 #define CCM_CCGR6_OCOTP_CTRL_MASK              (0x3 << 10)
+#define CCM_CCGR6_DSPI2_CTRL_MASK              (0x3 << 24)
+#define CCM_CCGR6_DSPI3_CTRL_MASK              (0x3 << 26)
 #define CCM_CCGR6_DDRMC_CTRL_MASK              (0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK              (0x3 << 4)
 #define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)