powerpc/85xx: Support for Freescale P1024/P1025 processor

Add Support for Freescale P1024/P1025 (dual core) and
P1015/P1016 (single core) processors.

P1024 is a variant of P1020 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1025 is a variant of P1021 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1015 is a variant of P1024 processor with single core and P1016 is a
variant of P1025 processor with single core.

Added comments in config_mpc85xx.h to denote single core versions of
processors.

Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 5791be019d6e72628f8d22bd418e1fcf30c63c29..d61d34c905b386a5c91fbe6a5612129f202b4b1e 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -55,9 +55,13 @@ COBJS-$(CONFIG_P1011)        += ddr-gen3.o
 COBJS-$(CONFIG_P1012)  += ddr-gen3.o
 COBJS-$(CONFIG_P1013)  += ddr-gen3.o
 COBJS-$(CONFIG_P1014)  += ddr-gen3.o
+COBJS-$(CONFIG_P1015)  += ddr-gen3.o
+COBJS-$(CONFIG_P1016)  += ddr-gen3.o
 COBJS-$(CONFIG_P1020)  += ddr-gen3.o
 COBJS-$(CONFIG_P1021)  += ddr-gen3.o
 COBJS-$(CONFIG_P1022)  += ddr-gen3.o
+COBJS-$(CONFIG_P1024)  += ddr-gen3.o
+COBJS-$(CONFIG_P1025)  += ddr-gen3.o
 COBJS-$(CONFIG_P2010)  += ddr-gen3.o
 COBJS-$(CONFIG_P2020)  += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)      += ddr-gen3.o
@@ -92,11 +96,15 @@ COBJS-$(CONFIG_P1011)       += p1021_serdes.o
 COBJS-$(CONFIG_P1012)  += p1021_serdes.o
 COBJS-$(CONFIG_P1013)  += p1022_serdes.o
 COBJS-$(CONFIG_P1014)  += p1010_serdes.o
+COBJS-$(CONFIG_P1015)  += p1021_serdes.o
+COBJS-$(CONFIG_P1016)  += p1021_serdes.o
 COBJS-$(CONFIG_P1017)  += p1023_serdes.o
 COBJS-$(CONFIG_P1020)  += p1021_serdes.o
 COBJS-$(CONFIG_P1021)  += p1021_serdes.o
 COBJS-$(CONFIG_P1022)  += p1022_serdes.o
 COBJS-$(CONFIG_P1023)  += p1023_serdes.o
+COBJS-$(CONFIG_P1024)  += p1021_serdes.o
+COBJS-$(CONFIG_P1025)  += p1021_serdes.o
 COBJS-$(CONFIG_P2010)  += p2020_serdes.o
 COBJS-$(CONFIG_P2020)  += p2020_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index d2baaf0c2daca407358d225694243076c7b3ef5e..39b304ae99bf8d7b56a1e7819accee4f162ff650 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -74,6 +74,10 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(P1013, P1013_E, 1),
        CPU_TYPE_ENTRY(P1014, P1014_E, 1),
        CPU_TYPE_ENTRY(P1014, P1014, 1),
+       CPU_TYPE_ENTRY(P1015, P1015_E, 1),
+       CPU_TYPE_ENTRY(P1015, P1015, 1),
+       CPU_TYPE_ENTRY(P1016, P1016_E, 1),
+       CPU_TYPE_ENTRY(P1016, P1016, 1),
        CPU_TYPE_ENTRY(P1017, P1017, 1),
        CPU_TYPE_ENTRY(P1017, P1017, 1),
        CPU_TYPE_ENTRY(P1020, P1020, 2),
@@ -84,6 +88,10 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(P1022, P1022_E, 2),
        CPU_TYPE_ENTRY(P1023, P1023, 2),
        CPU_TYPE_ENTRY(P1023, P1023_E, 2),
+       CPU_TYPE_ENTRY(P1024, P1024, 2),
+       CPU_TYPE_ENTRY(P1024, P1024_E, 2),
+       CPU_TYPE_ENTRY(P1025, P1025, 2),
+       CPU_TYPE_ENTRY(P1025, P1025_E, 2),
        CPU_TYPE_ENTRY(P2010, P2010, 1),
        CPU_TYPE_ENTRY(P2010, P2010_E, 1),
        CPU_TYPE_ENTRY(P2020, P2020, 2),

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 94373011ebb55b8650c48a0ea8dd5155249e02af..040e71b977df92285c728f886e4e2749e7b37fdb 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -92,20 +92,27 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 
+/* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+/* P1012 is single core version of P1021 */
 #elif defined(CONFIG_P1012)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+/* P1013 is single core version of P1022 */
 #elif defined(CONFIG_P1013)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12
@@ -121,6 +128,27 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 
+/* P1015 is single core version of P1024 */
+#elif defined(CONFIG_P1015)
+#define CONFIG_MAX_CPUS                        1
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
+#define CONFIG_SYS_FSL_SEC_COMPAT      2
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+/* P1016 is single core version of P1025 */
+#elif defined(CONFIG_P1016)
+#define CONFIG_MAX_CPUS                        1
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
+#define CONFIG_SYS_FSL_SEC_COMPAT      2
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+/* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12
@@ -137,6 +165,8 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_P1021)
 #define CONFIG_MAX_CPUS                        2
@@ -144,6 +174,8 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_P1022)
 #define CONFIG_MAX_CPUS                        2
@@ -164,6 +196,27 @@
 #define CONFIG_SYS_QMAN_NUM_PORTALS    3
 #define CONFIG_SYS_BMAN_NUM_PORTALS    3
 
+/* P1024 is lower end variant of P1020 */
+#elif defined(CONFIG_P1024)
+#define CONFIG_MAX_CPUS                        2
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
+#define CONFIG_SYS_FSL_SEC_COMPAT      2
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+/* P1025 is lower end variant of P1021 */
+#elif defined(CONFIG_P1025)
+#define CONFIG_MAX_CPUS                        2
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
+#define CONFIG_SYS_FSL_SEC_COMPAT      2
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+/* P2010 is single core version of P2020 */
 #elif defined(CONFIG_P2010)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                12
@@ -220,6 +273,7 @@
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
 
+/* P5010 is single core version of P5020 */
 #elif defined(CONFIG_PPC_P5010)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                32

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index d8b8f34017c9955e4f6e67fdfc46279857d273a4..f5bf4dd4fd40af7884ce79e50c10e96ddec5fba4 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1048,6 +1048,10 @@
 #define SVR_P1013_E    0x80EF00
 #define SVR_P1014      0x80F101
 #define SVR_P1014_E    0x80F901
+#define SVR_P1015      0x80E502
+#define SVR_P1015_E    0x80ED02
+#define SVR_P1016      0x80E503
+#define SVR_P1016_E    0x80ED03
 #define SVR_P1017      0x80F700
 #define SVR_P1017_E    0x80FF00
 #define SVR_P1020      0x80E400
@@ -1058,6 +1062,10 @@
 #define SVR_P1022_E    0x80EE00
 #define SVR_P1023      0x80F600
 #define SVR_P1023_E    0x80FE00
+#define SVR_P1024      0x80E402
+#define SVR_P1024_E    0x80EC02
+#define SVR_P1025      0x80E403
+#define SVR_P1025_E    0x80EC03
 #define SVR_P2010      0x80E300
 #define SVR_P2010_E    0x80EB00
 #define SVR_P2020      0x80E200