armv8: fsl-lsch3: add clock support for the second eSDHC

Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index bc268e207c89ca6228950f018ebf15f6287572bf..a5540f2b9d4a23b2529e060267efb65e23aa4c1c 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP Semiconductors
  *
  * Derived from arch/power/cpu/mpc85xx/speed.c
  */
@@ -214,6 +215,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_i2c_freq(0);
 #if defined(CONFIG_FSL_ESDHC)
        case MXC_ESDHC_CLK:
+       case MXC_ESDHC2_CLK:
                return get_sdhc_freq(0);
 #endif
        case MXC_DSPI_CLK:

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
index cf058d22a95710871b1d65f6d330f03d4b08dde1..b37a08d265382dbbde18783e5afa2d41d7f72111 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP Semiconductors
  *
  */
 
@@ -14,6 +15,7 @@ enum mxc_clock {
        MXC_BUS_CLK,
        MXC_UART_CLK,
        MXC_ESDHC_CLK,
+       MXC_ESDHC2_CLK,
        MXC_I2C_CLK,
        MXC_DSPI_CLK,
 };