arm: mx6: ddr: configure MMDC for slow_pd

According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).

Configure MMDC for slow pd.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 6e6f3373acebc574d0e43cd357dca95bfd749fe7..d22f232238d8078cf6a24dc16f6939b0f526bb73 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -469,6 +469,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
        mmdc0->mdpdc = (tcke & 0x7) << 16 |
                        5            << 12 |  /* PWDT_1: 256 cycles */
                        5            <<  8 |  /* PWDT_0: 256 cycles */
+                       1            <<  7 |  /* SLOW_PD */
                        1            <<  6 |  /* BOTH_CS_PD */
                        (tcksrx & 0x7) << 3 |
                        (tcksre & 0x7);