CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1275_revB"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm017_dc3"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104_revC"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu106"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu111"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zc1275 RevB
- *
- * (C) Copyright 2018 Xilinx, Inc.
- */
-
-#ifndef __CONFIG_ZYNQMP_ZC1275_REVB_H
-#define __CONFIG_ZYNQMP_ZC1275_REVB_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZC1275_REVB_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zc1751 XM015 DC1
- *
- * (C) Copyright 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
-#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zc1751 XM017 DC3
- *
- * (C) Copyright 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H
-#define __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zc1751 XM019 DC5
- *
- * (C) Copyright 2015 Xilinx, Inc.
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
-#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zcu100
- *
- * (C) Copyright 2015 - 2016 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZCU100_H
-#define __CONFIG_ZYNQMP_ZCU100_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZCU100_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zcu102
- *
- * (C) Copyright 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZCU102_H
-#define __CONFIG_ZYNQMP_ZCU102_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZCU102_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zcu104
- *
- * (C) Copyright 2017 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZCU104_H
-#define __CONFIG_ZYNQMP_ZCU104_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZCU104_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zcu104
- *
- * (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZCU104_REVC_H
-#define __CONFIG_ZYNQMP_ZCU104_REVC_H
-
-#include <configs/xilinx_zynqmp_zcu104.h>
-
-#endif /* __CONFIG_ZYNQMP_ZCU104_REVC_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zcu106
- *
- * (C) Copyright 2016 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZCU106_H
-#define __CONFIG_ZYNQMP_ZCU106_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZCU106_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Xilinx ZynqMP zcu111
- *
- * (C) Copyright 2017 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#ifndef __CONFIG_ZYNQMP_ZCU111_H
-#define __CONFIG_ZYNQMP_ZCU111_H
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZCU111_H */